KR20040004873A - Method for forming trench type isolation layer in semiconductor device - Google Patents
Method for forming trench type isolation layer in semiconductor device Download PDFInfo
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- A61F2/02—Prostheses implantable into the body
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- A61F2/00—Filters implantable into blood vessels; Prostheses, i.e. artificial substitutes or replacements for parts of the body; Appliances for connecting them with the body; Devices providing patency to, or preventing collapsing of, tubular structures of the body, e.g. stents
- A61F2/02—Prostheses implantable into the body
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- A61F2002/30001—Additional features of subject-matter classified in A61F2/28, A61F2/30 and subgroups thereof
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- A61F2/00—Filters implantable into blood vessels; Prostheses, i.e. artificial substitutes or replacements for parts of the body; Appliances for connecting them with the body; Devices providing patency to, or preventing collapsing of, tubular structures of the body, e.g. stents
- A61F2/02—Prostheses implantable into the body
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- A61F2/32—Joints for the hip
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- A61F2/00—Filters implantable into blood vessels; Prostheses, i.e. artificial substitutes or replacements for parts of the body; Appliances for connecting them with the body; Devices providing patency to, or preventing collapsing of, tubular structures of the body, e.g. stents
- A61F2/02—Prostheses implantable into the body
- A61F2/30—Joints
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- A61F2/02—Prostheses implantable into the body
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- A61F2/32—Joints for the hip
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Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 소자간의 전기적 분리를위한 소자분리 공정에 관한 것이며, 더 자세히는 트렌치형 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a device isolation process for electrical separation between devices, and more particularly, to a method of forming a trench type device isolation film.
전통적인 소자분리 공정인 실리콘국부산화(LOCOS) 공정은 근본적으로 버즈비크(Bird's beak)로부터 자유로울 수 없으며, 버즈비크에 의한 활성영역의 감소로 인하여 초고집적 반도체 소자에 적용하기 어렵게 되었다.The silicon isolation process (LOCOS) process, which is a traditional device isolation process, cannot fundamentally be free from Bird's beak and is difficult to apply to ultra-high density semiconductor devices due to the reduction of the active area caused by Buzzbeek.
한편, 트렌치 소자분리(shallow trench isolation, STI) 공정은 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인을 근본적으로 해결할 수 있고, 활성영역의 확보에 유리한 소자분리 공정으로 부각되고 있으며, 향후 1G DRAM 또는 4G DRAM급 이상의 초고집적 반도체 소자 제조 공정에의 적용이 유망한 기술이다.Meanwhile, the trench trench isolation (STI) process can fundamentally solve instability factors such as deterioration of the field oxide film due to the reduction of the design rule of the semiconductor device, and is advantageous for securing the active region. It is emerging as a device separation process, and it is a promising technology to be applied to an ultra-high density semiconductor device manufacturing process of 1G DRAM or 4G DRAM level in the future.
종래의 STI 공정은 실리콘 기판 상에 패드 산화막 및 패드 질화막을 형성하고, 이를 선택 식각하여 트렌치 마스크를 형성한 다음, 패터닝된 패드 질화막을 식각 마스크로 사용하여 실리콘 기판을 건식 식각함으로써 트렌치를 형성하고, 계속하여 측벽 열산화 공정을 실시하고, 고밀도플라즈마(high density plasma, HDP) 산화막을 증착하여 트렌치를 매립하고, 화학·기계적 연마(chemical mechanical polishing, CMP) 공정을 실시하여 평탄화를 이룬 다음, 패드 질화막 및 패드 산화막을 제거하여 소자분리막을 형성하게 된다.In the conventional STI process, a trench is formed by forming a pad oxide film and a pad nitride film on a silicon substrate, selectively etching the trench mask to form a trench mask, and then dry etching the silicon substrate using the patterned pad nitride film as an etching mask, Subsequently, a sidewall thermal oxidation process is performed, a high density plasma (HDP) oxide film is deposited to fill the trench, and a chemical mechanical polishing (CMP) process is performed to planarize the pad nitride film. And removing the pad oxide layer to form an isolation layer.
전술한 바와 같이 STI 공정은 주로 트렌치 매립 산화막 증착 후에는 평탄화를 위하여 CMP 공정을 필수적으로 적용하고 있다. 트렌치 매립 산화막의 CMP 공정을 수행하기 위해서는 연마 정지막으로서 두꺼운 질화막(500∼2000Å)을 필요로 한다. 뿐만 아니라 더미 활성 영역을 형성해야 하고, 광역 필드 영역의 보정을 위해서는 사진 공정을 수반한 평탄화 식각 공정을 요하기 때문에 소자분리 공정에 소요되는 시간과 비용이 큰 문제점이 지적되고 있다.As described above, the STI process essentially applies the CMP process for planarization after the deposition of the trench buried oxide. In order to perform the CMP process of the trench buried oxide film, a thick nitride film (500 to 2000 microseconds) is required as the polishing stop film. In addition, since a dummy active region has to be formed and a planar etching process involving a photo process is required to correct the wide field region, a large time and cost for the device isolation process are pointed out.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 트렌치 매립 산화막의 평탄화에 소요되는 공정 시간과 비용을 줄일 수 있는 반도체 소자의 트렌치형 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for forming a trench type isolation layer for a semiconductor device which can reduce the process time and cost required to planarize the trench buried oxide film. .
도 1 내지 도 7은 본 발명의 일 실시예에 따른 STI 공정도.1 to 7 are STI process diagram according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판10: silicon substrate
11 : 패드 산화막11: pad oxide film
12 : 패드 질화막12: pad nitride film
13 : 포토레지스트 패턴13: photoresist pattern
14 : 측벽 산화막14: sidewall oxide film
15 : HDP 산화막15: HDP oxide film
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 실리콘 기판 상에 질화막을 포함하는 트렌치 마스크 패턴을 형성하는 단계; 노출된 상기 실리콘 기판을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 트렌치가 형성된 전체 구조 상부에 트렌치 매립 산화막을 형성하는 단계; 수평 방향으로 식각용 레이저를 조사하여 상기 트렌치 매립 산화막을 식각하는 단계; 및 상기 트렌치 마스크 패턴을 제거하는 단계를 포함하는 반도체 소자의 트렌치형 소자분리막 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, forming a trench mask pattern including a nitride film on a silicon substrate; Selectively etching the exposed silicon substrate to form a trench; Forming a trench buried oxide layer on the entire structure of the trench; Etching the trench buried oxide film by irradiating an etching laser in a horizontal direction; And removing the trench mask pattern.
본 발명은 트렌치 매립 산화막의 평탄화를 위해 레이저 에칭(Laser etching) 방식을 사용한다. 레이저 에칭 방식은 기존의 CMP 공정에 비해 공정 시간이 짧고 공정 단가가 낮은 장점이 있다.The present invention uses a laser etching method to planarize the trench buried oxide film. The laser etching method has the advantages of shorter process time and lower process cost than the conventional CMP process.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1 내지 도 7은 본 발명의 일 실시예에 따른 STI 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 to 7 illustrate an STI process according to an embodiment of the present invention, which will be described with reference to the following.
본 실시예에 따른 STI 공정은 우선, 도 1에 도시된 바와 같이 실리콘 기판(10) 표면을 열산화시켜 50∼200Å 두께의 패드 산화막(11)을 형성한다.In the STI process according to the present embodiment, first, as shown in FIG. 1, the surface of the silicon substrate 10 is thermally oxidized to form a pad oxide film 11 having a thickness of 50 to 200 Å.
다음으로, 도 2에 도시된 바와 같이 패드 산화막(11) 상에 패드 질화막(12)을 증착한다. 이때, 패드 질화막(12)의 두께는 300Å 정도면 충분하다.Next, as shown in FIG. 2, a pad nitride film 12 is deposited on the pad oxide film 11. At this time, the thickness of the pad nitride film 12 is about 300 kPa.
이어서, 도 3에 도시된 바와 같이 패드 질화막(12) 상에 포토레지스트를 도포하고, 소자분리 마스크를 이용한 노광 및 현상 공정을 실시하여 포토레지스트 패턴(13)을 형성한 다음, 패드 질화막(11) 및 패드 산화막(11)을 차례로 선택 식각하고, 노출된 실리콘 기판(10)을 2000∼5000Å 깊이로 건식 식각함으로써 트렌치를 형성한다. 이때, 트렌치 식각은 도면과 같이 포토레지스트 패턴(13)을 사용할 수도 있으며, 패드 질화막(11)을 식각 베리어로 사용하는 경우도 있다.Subsequently, as shown in FIG. 3, a photoresist is applied on the pad nitride layer 12, an exposure and development process using an element isolation mask is performed to form the photoresist pattern 13, and then the pad nitride layer 11 is formed. And the pad oxide film 11 are sequentially etched to form a trench by dry etching the exposed silicon substrate 10 to a depth of 2000 to 5000 kPa. In this case, the trench etching may use the photoresist pattern 13 as shown in the drawing, and the pad nitride film 11 may be used as an etching barrier.
계속하여, 도 4에 도시된 바와 같이 포토레지스트 패턴(13)을 제거하고, 후세정 공정을 실시한 다음, 열산화 공정을 실시하여 노출된 트렌치 영역에 20∼200Å 두께의 측벽 산화막(14)을 형성한다.Subsequently, as shown in FIG. 4, the photoresist pattern 13 is removed, a post-cleaning process is performed, and then a thermal oxidation process is performed to form a sidewall oxide film 14 having a thickness of 20 to 200 占 퐉 in the exposed trench region. do.
다음으로, 도 5에 도시된 바와 같이 전체 구조 상부에 HDP 산화막(15)을 증착하여 트렌치 갭-필을 이룬다. 이때, HDP 산화막(15)은 소자분리 영역을 기준으로6000Å 이상의 두께로 증착하는 것이 바람직하다.Next, as shown in FIG. 5, an HDP oxide film 15 is deposited on the entire structure to form a trench gap-fill. At this time, the HDP oxide film 15 is preferably deposited to a thickness of 6000 Å or more based on the device isolation region.
이어서, 도 6에 도시된 바와 같이 레이저 에칭 방식을 사용하여 수평 방향으로 HDP 산화막(15)을 깍아내고, 후세정을 실시한다. HDP 산화막(15)의 식각이 진행되면서 패드 질화막(12)이 노출될 경우, 질화막과 산화막의 매질 차이에 의해 식각 정지를 유도한다. 한편, 레이저는 10Å 레벨로 조절되는 식각용 레이저를 사용하며 웨이퍼의 좌우를 왕복하면서 식각하는 것이 바람직하며, 공정이 진행되는 챔버를 고진공 상태로 유지하는 것이 바람직하다.Subsequently, as shown in FIG. 6, the HDP oxide film 15 is scraped off in the horizontal direction using a laser etching method and subjected to post-cleaning. When the pad nitride layer 12 is exposed while the HDP oxide layer 15 is etched, the etch stop is induced by the difference between the nitride layer and the oxide layer. On the other hand, the laser uses an etching laser that is adjusted to a level of 10 kHz, it is preferable to etch while reciprocating the left and right sides of the wafer, it is preferable to maintain the chamber in which the process is in a high vacuum state.
계속하여, 도 7에 도시된 바와 같이 질화막 식각 용액(예컨대, 인산 용액)을 사용하여 노출된 패드 질화막(12)을 습식 제거한다.Subsequently, as shown in FIG. 7, the exposed pad nitride film 12 is wet-removed using a nitride film etching solution (eg, a phosphoric acid solution).
이후, 패드 산화막(11)을 습식 제거하여 STI 공정을 완료한다.Thereafter, the pad oxide layer 11 is wet removed to complete the STI process.
전술한 바와 같이 STI 공정을 수행하는 경우, 트렌치 매립 산화막의 평탄화를 위해 공정 단가가 높은 CMP 공정을 수행하지 않고, 비교적 공정 단가가 낮은 레이저 에칭 방식을 사용하기 때문에 전체적인 공정 단가를 줄일 수 있다. 한편, CMP 공정을 사용하지 않기 때문에 패드 질화막을 두껍게 증착하지 않아도 되며, 더미 활성 영역을 생성하지 않아도 되고, 광역 필드 영역의 보정을 위한 사진 공정을 수반한 평탄화 식각 공정을 요하지 않기 때문에 STI 공정을 단순화하고, 공정 시간을 단축할 수 있다.As described above, when the STI process is performed, the overall process cost can be reduced because a laser etching method having a relatively low process cost is used without performing a CMP process having a high process cost to planarize the trench buried oxide film. On the other hand, since the CMP process is not used, the pad nitride film does not need to be thickly deposited, dummy active regions are not generated, and the planar etching process involving the photo process for correcting the wide field field is not required. The process time can be shortened.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 트렌치 식각 후 트렌치 측벽 산화막을 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 트렌치 측벽 열산화 공정을 수행하는 않는 경우에도 적용될 수 있다.For example, in the above-described embodiment, a case in which the trench sidewall oxide layer is formed after the trench etching is described as an example. However, the present invention may be applied to a case in which the trench sidewall thermal oxidation process is not performed.
또한, 전술한 실시예에서는 트렌치 매립 산화막으로 HDP 산화막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 트렌치 매립 산화막으로 다른 산화막을 사용하는 경우에도 적용될 수 있다.In addition, in the above-described embodiment, the case where the HDP oxide film is used as the trench buried oxide film has been described as an example. However, the present invention may be applied to the case where another oxide film is used as the trench buried oxide film.
전술한 본 발명은 STI 공정을 단순화하고, STI 공정 시간을 크게 단축하며, STI 공정의 공정 단가를 줄일 수 있는 효과가 있다.The present invention described above has the effect of simplifying the STI process, greatly shortening the STI process time, and reducing the process cost of the STI process.
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KR100696052B1 (en) * | 2005-12-28 | 2007-03-16 | 동부일렉트로닉스 주식회사 | Method of forming trench type field isolation layer |
US9425395B2 (en) | 2014-10-14 | 2016-08-23 | Samsung Electronics Co., Ltd. | Method of fabricating a variable resistance memory device |
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KR100696052B1 (en) * | 2005-12-28 | 2007-03-16 | 동부일렉트로닉스 주식회사 | Method of forming trench type field isolation layer |
US9425395B2 (en) | 2014-10-14 | 2016-08-23 | Samsung Electronics Co., Ltd. | Method of fabricating a variable resistance memory device |
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