JPH05275528A - Forming method of element isolating region - Google Patents

Abstract

PURPOSE:To selectively form silicon oxide film in a trench without dispersion on a wafer surface thereby enabling a trench type isolating region in high mass productivity to be formed by a method wherein amorphous silicon is buried-in the trench to be an element isolating region to be annealed later. CONSTITUTION:A silicon oxide film 2, a silicon nitride film 3 and another silicon oxide film 4 are successively formed on a silicon sibstrate 1 and then the part to be an element isolating region 10 is etched away to form a trench 5. Next, the other silicon oxide film 6 and another silicon nitride film 7 are formed inside the trench 5 to form a sidewall on the trench 5 side simultaneously removing the silicon oxide film 6 and the silicon nitride film 7 to expose the silicon substrate 1. Next, amorphous silicon 8 is deposited on the whole surface previously implanted with ions so as to bury-in a single crystalline silicon 9 inside the trench 5 by annealing step and then oxidized to form the element isolating region 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation region.

[0002]

2. Description of the Related Art In the ideal IC / LSI separation area,
It is desired to have a high isolation breakdown voltage and a high inversion voltage in the smallest possible area. Among them, the trench isolation method is
This is the technology that can currently achieve the smallest separation.

The conventional process for forming an element isolation region using a trench (trench isolation method) will be described below.
FIG. 2 shows a process of forming a device isolation region using a conventional trench. First, the silicon oxide film 2 is formed on the silicon substrate 1.
After the silicon nitride film 3 and the silicon nitride film 3 are sequentially deposited, the silicon nitride film 3, the silicon oxide film 2 and the silicon substrate 1 in the region to be the element isolation region are etched to form the trench 5 (FIG. 2A).

Next, a silicon oxide film 6 is formed on the inner surface of the trench 5 by a thermal oxidation method, and then a silicon nitride film 7 is formed on the entire surface by a CVD method and etched back to form a sidewall on the side surface of the trench 5. Together with forming
The silicon substrate 1 on the bottom surface of the trench 5 is exposed, and impurities for a channel stopper are ion-implanted. After depositing polysilicon 11 on the entire surface, a resist 12 is spin-coated and completely flattened (FIG. 2B).

Next, etching is carried out under the etching conditions such that the etching rate of the polysilicon 11 and the resist 12 is 1: 1, leaving the polysilicon 11 only in the trench 5 (FIG. 2 (c)) and performing thermal oxidation. Then, the polysilicon 11 in the trench 5 is completely oxidized to form the element isolation region 10 (FIG. 2D).

[0006]

When the above steps are used, the polysilicon 11 is buried in the trench 5 and the resist 12 is used for flattening. Since it becomes considerably thick, the etching time becomes long, and the polysilicon 11 and the resist 1
In order to make the etching ratio with 2 to 1: 1, the process becomes complicated and the variation in the wafer surface becomes large.
Not suitable for mass production.

It is an object of the present invention to provide a method for forming an element isolation region suitable for mass production, in which a silicon oxide film is selectively buried in a trench without using a planarization technique using a resist.

[0008]

A method of forming an element isolation region according to the present invention comprises a step of sequentially forming a first silicon oxide film, a first silicon nitride film and a second silicon oxide film on a silicon substrate, and element isolation. The step of etching the first and second silicon oxide films, the first silicon nitride film and the silicon substrate in a region to be a region to form a groove having a predetermined depth, and the same bottom surface of the groove as the silicon substrate. A step of ion-implanting a conductivity type impurity; a step of forming a sidewall of a third silicon oxide film and a second silicon nitride film in the groove; a step of forming the second silicon oxide film, a second silicon nitride film and a silicon substrate. A step of depositing amorphous silicon on the amorphous silicon and annealing the amorphous silicon to a predetermined thickness in the groove; After selective removal of, it is characterized in that a step of oxidizing the single crystal silicon.

[0009]

By using the above invention, it is possible to fill amorphous silicon in a trench, form single crystal silicon in the trench by annealing, and form a locos oxide film by thermal oxidation without using a resist for flattening and ashing. it can.

[0010]

The present invention will be described in detail below based on an example.

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention. First, thermal oxidation is performed on a silicon substrate 1 at about 1050 ° C. to form a silicon oxide film 2 having a film thickness of about 500Å, and C
The silicon nitride film 3 is formed to a film thickness of about 1200Å by the VD method, and the non-doped silicon oxide film 4 is formed to a film thickness of 2000Å by the continuous CVD method. The non-doped silicon oxide film 4 is formed in order to selectively remove the amorphous silicon 8. Next, the silicon oxide films 2 and 4 and the silicon nitride film 3 in the regions to be the element isolation regions are removed, the silicon substrate 1 is etched by about 3000 Å, and trenches 5 are formed (FIG. 1A).

Next, a silicon oxide film 6 having a film thickness of about 500 Å is formed on the inner surface of the trench 5 by thermal oxidation at about 1050 ° C. Then, a silicon nitride film 7 is formed on the entire surface by a CVD method. About 1500 Å is deposited, CF ₄ and CHF ₃ are flown as etching gas at a flow rate of about 90 SCCM and about 30 SCCM, respectively, and etch back is performed at a pressure of about 1600 mTorr to form a sidewall on the side surface of the trench 5 and, at the same time, to oxidize silicon on the bottom surface of the trench 5. The film 6 and the silicon nitride film 7 are removed to expose the silicon substrate 1. Then, for forming a channel stopper, the acceleration energy is about 50 keV and the dose is about 4 × 10 ¹³ ion.
Boron ion implantation is performed under the condition of s / cm ² . Next, by a low pressure CVD method, for example, disilane (Si ₂ H ₆ ) is hydrogen-reduced at a temperature of about 500 ° C. and a pressure of about 190 mTorr to form amorphous silicon 8 on the entire surface to a film thickness of about 1500Å (see FIG. b)).

Next, 30 to 60 at 1000 to 1100 ° C.
By performing the annealing treatment for a minute, only the amorphous silicon 8 in the trench 5 is single-crystallized from the portion in contact with the silicon substrate 1 (FIG. 1C).

Next, the amorphous silicon 8 which has not been single-crystallized is treated with potassium hydroxide (KOH) or hydrofluoric acid (H).
F) / nitric acid (HNO ₃ ) is removed by wet etching, and then the silicon oxide film 4 is removed by wet etching using hydrofluoric acid (HF) (FIG. 1).
(D)).

Next, at about 1050 ° C. for about 100 minutes, O ₂ /
The single crystallized silicon 9 in the trench 5 is oxidized in an H ₂ atmosphere to form a silicon oxide film 10 serving as an element isolation region (FIG. 1E).

[0016]

As described above in detail, according to the present invention, a silicon oxide film is selectively formed in a trench by embedding amorphous silicon in a trench to be an element isolation region and performing an annealing treatment. be able to. Therefore, there is no variation within the wafer surface as in the case of using the flattening technique using a resist, long-time etching is not required, and it is possible to form a trench type element isolation region rich in mass productivity.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an example of the present invention.

FIG. 2 is a process diagram of forming a conventional element isolation region.

[Explanation of symbols]

 1 Silicon Substrate 2,4,6,10 Silicon Oxide Film 5 Trench 3,7 Silicon Nitride Film 8 Amorphous Silicon 9 Single Crystalline Silicon 11 Polysilicon 12 Resist

Claims (1)

[Claims] 1. A first silicon oxide film on a silicon substrate,
A step of sequentially forming a first silicon nitride film and a second silicon oxide film, and etching the first and second silicon oxide films, the first silicon nitride film and the silicon substrate in a region to be an element isolation region to a predetermined depth. A step of forming a groove having a same height, a step of ion-implanting an impurity of the same conductivity type as that of the silicon substrate into a bottom surface of the groove, and a sidewall formed of a third silicon oxide film and a second silicon nitride film in the groove part. And a step of depositing amorphous silicon on the second silicon oxide film, the second silicon nitride film and the silicon substrate, and annealing the amorphous silicon to a predetermined thickness in the groove by annealing. A step of oxidizing the single crystallized silicon after selectively removing the amorphous silicon. Forming method of the release area.