JPH05304203A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH05304203A
JPH05304203A JP4107997A JP10799792A JPH05304203A JP H05304203 A JPH05304203 A JP H05304203A JP 4107997 A JP4107997 A JP 4107997A JP 10799792 A JP10799792 A JP 10799792A JP H05304203 A JPH05304203 A JP H05304203A
Authority
JP
Japan
Prior art keywords
opening
semiconductor
semiconductor substrate
silicon substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4107997A
Other languages
Japanese (ja)
Inventor
Tomoyuki Hikita
智之 疋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4107997A priority Critical patent/JPH05304203A/en
Publication of JPH05304203A publication Critical patent/JPH05304203A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a small area isolation region by depositing an amorphous semiconductor entirely on the surface of a semiconductor substrate while leaving an insulation film only on the surface of the semiconductor substrate and the side wall of opening and then performing annealing. CONSTITUTION:A first insulation film 2a is formed on the surface of a silicon substrate 1. The first insulation film 2a is then patterned into a predetermined shape and an opening 3 is made in the silicon substrate 1 through etching. A second insulation film 2b is then formed on the surface of the silicon substrate 1 including the opening 3 and subsequently etched so that the second insulation film 2b is left only on the side wall 3a of the opening. An amorphous silicon 4 is deposited entirely on the surface of the silicon substrate 1, which is then annealed and the amorphous silicon 4 is removed selectively from the surface of the silicon substrate 1 thus isolating the active region. This method realizes an isolation region having quite small area.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、より詳細には特にIC、LSI等の集積回路の活
性領域を分離する半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for isolating active regions of integrated circuits such as IC and LSI.

【0002】[0002]

【従来の技術】従来より、シリコン基板に溝を形成し、
その溝側面に絶縁膜を選択的に残存させ、溝内を単結晶
シリコンで埋設するといった微細分離技術がいくつか提
案されている。例えば、特開平2−82551には図3
に示したような半導体装置の製造方法が開示されてい
る。
2. Description of the Related Art Conventionally, a groove is formed on a silicon substrate,
Several fine separation techniques have been proposed in which an insulating film is selectively left on the side surface of the groove and the inside of the groove is filled with single crystal silicon. For example, in Japanese Patent Laid-Open No. 2-82551, FIG.
There is disclosed a method of manufacturing a semiconductor device as shown in FIG.

【0003】まず、半導体基板11を所定形状にパター
ニングし、エッチングにより半導体基板11に凹部12
を形成する。そして、さらに凹部12が形成された半導
体基板11全面に絶縁膜13を形成し、この絶縁膜13
を異方性エッチングによりエッチバックして半導体基板
11の凹部12の側壁のみに残存させる。その後、半導
体基板11全面に半導体基板11に形成した凹部12の
深さよりも十分に厚い単結晶シリコン14を堆積する
(図3(a))。
First, the semiconductor substrate 11 is patterned into a predetermined shape, and a recess 12 is formed in the semiconductor substrate 11 by etching.
To form. Then, an insulating film 13 is formed on the entire surface of the semiconductor substrate 11 in which the recess 12 is further formed.
Is etched back by anisotropic etching so that only the side wall of the recess 12 of the semiconductor substrate 11 remains. Then, single crystal silicon 14 having a thickness sufficiently thicker than the depth of the recess 12 formed in the semiconductor substrate 11 is deposited on the entire surface of the semiconductor substrate 11 (FIG. 3A).

【0004】次いで、レジスト等の平坦化材料15を回
転塗布し、半導体基板11表面を完全に平坦化する(図
3(b))。そして、半導体基板11全面をエッチバッ
クすることにより、半導体基板11凹部12内に単結晶
シリコン14を埋設する(図3(c))。また、特開平
2−214138及び特開平3−141660には図4
に示したような半導体装置の製造方法が開示されてい
る。
Next, a flattening material 15 such as a resist is spin-coated to completely flatten the surface of the semiconductor substrate 11 (FIG. 3B). Then, the entire surface of the semiconductor substrate 11 is etched back to embed the single crystal silicon 14 in the recess 12 of the semiconductor substrate 11 (FIG. 3C). In addition, in Japanese Patent Laid-Open Nos. 2-214138 and 3-141660, FIG.
There is disclosed a method of manufacturing a semiconductor device as shown in FIG.

【0005】まず、上記の方法と同様の方法によりシリ
コン基板11に開口部12を形成し、シリコン基板11
表面と開口部12側壁のみに絶縁膜13を残存させた後
(図4(a))、選択的にシリコン基板11の開口部1
2内に単結晶シリコン14を成長させる(図4
(b))。
First, the opening 12 is formed in the silicon substrate 11 by the same method as described above, and then the silicon substrate 11 is formed.
After leaving the insulating film 13 only on the surface and the sidewall of the opening 12 (FIG. 4A), the opening 1 of the silicon substrate 11 is selectively formed.
2 grows single crystal silicon 14 (FIG. 4).
(B)).

【0006】[0006]

【発明が解決しようとする課題】上記の半導体装置の製
造方法において、半導体基板11の凹部12側壁のみに
絶縁膜13を残存させ、その上に単結晶シリコン14を
堆積し、レジスト等の平坦化材料15を堆積してエッチ
バックを行う方法では、平坦化材料15をかなり厚膜化
させる必要があり、その厚膜化に伴い、平坦化材料15
のウェハ面内均一性の問題や長時間にわたるエッチバッ
クによるスループットの低下等の問題があった。
In the method of manufacturing a semiconductor device described above, the insulating film 13 is left only on the side wall of the recess 12 of the semiconductor substrate 11, the single crystal silicon 14 is deposited on the insulating film 13, and the resist or the like is planarized. In the method of depositing the material 15 and performing the etch back, it is necessary to make the planarizing material 15 a considerably thick film, and the planarizing material 15 is accompanied by the thickening of the film.
However, there were problems such as in-plane uniformity of wafer and decrease in throughput due to etchback for a long time.

【0007】また、シリコン基板11に開口部12を形
成し、シリコン基板11表面と開口部12側壁のみに絶
縁膜13を残存させた後、選択的にシリコン基板11の
開口部12内に単結晶シリコン14を成長させる方法に
おいて、シリコン基板11と絶縁膜13との選択性が完
全となる条件下における単結晶シリコンの成長法は、そ
の成長速度が極めて小さく、量産技術として極めて不適
当であるという問題があった。
Further, after forming the opening 12 in the silicon substrate 11 and leaving the insulating film 13 only on the surface of the silicon substrate 11 and the sidewall of the opening 12, the single crystal is selectively formed in the opening 12 of the silicon substrate 11. In the method of growing the silicon 14, the growth rate of single crystal silicon under the condition that the selectivity between the silicon substrate 11 and the insulating film 13 is perfect is extremely low, and is extremely unsuitable as a mass production technology. There was a problem.

【0008】本発明はこのような問題に鑑みなされたも
のであり、平坦性を損なうことなく、量産性に富んだ、
極めて小面積の素子分離領域を形成することができる半
導体装置の製造方法を提供することを目的としている。
The present invention has been made in view of the above problems, and is excellent in mass productivity without impairing flatness.
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming an element isolation region having an extremely small area.

【0009】[0009]

【課題を解決するための手段】上記記載の問題を解決す
るために本発明によれば、(i) 半導体基板表面に第1の
絶縁膜を形成する工程、(ii)前記第1の絶縁膜を所定の
形状にパターニングするとともに前記半導体基板をエッ
チングして開口部を形成する工程、(iii) 前記開口部を
含む半導体基板表面に第2の絶縁膜を形成した後、エッ
チングにより前記開口部側壁のみに前記第2の絶縁膜を
残存させる工程、(iv)前記半導体基板上全面にアモルフ
ァス半導体を堆積し、アニール処理を行った後、半導体
基板上の前記アモルファス半導体を選択的に除去する工
程、を含んで活性領域を分離する半導体装置の製造方法
が提供される。
In order to solve the above-mentioned problems, according to the present invention, (i) a step of forming a first insulating film on the surface of a semiconductor substrate, (ii) the first insulating film Patterning to a predetermined shape and etching the semiconductor substrate to form an opening, (iii) forming a second insulating film on the surface of the semiconductor substrate including the opening, and then etching the sidewall of the opening. Leaving only the second insulating film, (iv) depositing an amorphous semiconductor on the entire surface of the semiconductor substrate, performing an annealing treatment, and then selectively removing the amorphous semiconductor on the semiconductor substrate, There is provided a method of manufacturing a semiconductor device including an active region, the active region being isolated.

【0010】本発明において、半導体基板(例えば、シ
リコン基板)上に形成される第1の絶縁膜としては、例
えば、SiO2 膜、SiN膜等が挙げられ、好ましくは
SiO2 膜であり、その膜厚は1500〜2000Å程
度である。また、第2の絶縁膜としては、例えば、Si
2 膜、SiN膜等が挙げられ、好ましくはSiO2
であり、その膜厚は2000〜2500Å程度である。
これらの絶縁膜は公知の方法、例えば、熱酸化、CVD
法等によって形成することができる。
In the present invention, examples of the first insulating film formed on the semiconductor substrate (for example, a silicon substrate) include SiO 2 film and SiN film, and the SiO 2 film is preferable. The film thickness is about 1500 to 2000Å. Further, as the second insulating film, for example, Si
Examples thereof include an O 2 film and a SiN film, and a SiO 2 film is preferable, and the film thickness thereof is about 2000 to 2500Å.
These insulating films are formed by a known method such as thermal oxidation or CVD.
It can be formed by a method or the like.

【0011】また、活性領域を形成する領域に形成する
開口部は、好ましくは深さが2500〜3000Å程度
であり、通常のエッチング方法、例えば、トレンチエッ
チ等によって形成することができる。さらに、第1及び
第2の絶縁膜をエッチングして、半導体基板表面及び開
口部側壁のみに絶縁膜を残存させる方法は、公知の方
法、例えば、異方性エッチングにより行うことができ
る。
The opening formed in the region for forming the active region preferably has a depth of about 2500 to 3000Å and can be formed by a usual etching method such as trench etching. Further, the method of etching the first and second insulating films to leave the insulating film only on the surface of the semiconductor substrate and the sidewalls of the opening can be performed by a known method, for example, anisotropic etching.

【0012】本発明において、アモルファス半導体は公
知の方法、例えば、CVD法等により形成することがで
き、このアモルファス半導体を単結晶化する方法は、ア
モルファス半導体を単結晶半導体に接触させて、N2
はAr雰囲気下、常圧、1000〜1100℃程度の温
度範囲で30〜60分間程度アニール処理することによ
り達成することができる。そして、開口部内に埋設され
たアモルファス半導体部分が完全に単結晶化した後、単
結晶化されていない、半導体基板上のアモルファス半導
体のみを、例えば、KOH、HF/HNO3 系エッチャ
ントによるスピンエッチにより、その廃液中のSi濃度
の変化を検知し、表面のSiO2 が露出した時点でエッ
チャントの供給を止める方法等により、選択的にエッチ
ング除去するものである。
In the present invention, the amorphous semiconductor can be formed by a known method, for example, the CVD method, and the method of single crystallizing the amorphous semiconductor is to bring the amorphous semiconductor into contact with the single crystal semiconductor to form N 2 Alternatively, it can be achieved by annealing in an Ar atmosphere at atmospheric pressure and in a temperature range of about 1000 to 1100 ° C. for about 30 to 60 minutes. Then, after the amorphous semiconductor portion embedded in the opening is completely single-crystallized, only the amorphous semiconductor on the semiconductor substrate which is not single-crystallized is spin-etched by, for example, KOH or HF / HNO 3 -based etchant. In this method, the change in Si concentration in the waste liquid is detected, and when the SiO 2 on the surface is exposed, the supply of the etchant is stopped and the etching is selectively removed.

【0013】このような方法で分離された活性領域には
所望の半導体素子を形成することができる。
A desired semiconductor element can be formed in the active region separated by such a method.

【0014】[0014]

【作用】上記した方法によれば、半導体基板に開口部を
形成し、前記半導体基板表面及び前記開口部側壁のみに
絶縁膜を残存させた後、前記半導体基板上全面にアモル
ファス半導体を堆積してアニール処理を行い、半導体基
板上の前記アモルファス半導体を選択的に除去する工程
を含んで活性領域を分離するので、アモルファス半導体
が自己整合的に、容易に単結晶化されることとなる。
According to the above method, the opening is formed in the semiconductor substrate, the insulating film is left only on the surface of the semiconductor substrate and the sidewall of the opening, and then the amorphous semiconductor is deposited on the entire surface of the semiconductor substrate. Since the active region is separated by performing an annealing process and selectively removing the amorphous semiconductor on the semiconductor substrate, the amorphous semiconductor is easily monocrystallized in a self-aligned manner.

【0015】[0015]

【実施例】本発明に係る半導体装置の製造方法の実施例
を図1及び図2に基づいて説明する。まず、シリコン基
板1を酸化し、2000Å程度の膜厚の第1の絶縁膜で
あるSiO2 膜2aを形成した(図1(a))。
EXAMPLE An example of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. First, the silicon substrate 1 was oxidized to form a SiO 2 film 2a as a first insulating film having a film thickness of about 2000 Å (FIG. 1A).

【0016】SiO2 膜2aを所定の形状にパターニン
グすると同時に、シリコン基板1を3000Å程度エッ
チングして開口部3を形成した(図1(b))。そし
て、開口部3表面に200Å程度の酸化膜を形成したの
ち、開口部3を含むシリコン基板1上全面にSiH4
びO2 を用いたCVD法により第2の絶縁膜であるSi
2 膜2bを2500Å程度形成した(図1(c))。
次いで、SiO2 膜2bを2500Å程度、開口部3底
面のシリコン基板1が完全に露出するまで、異方性エッ
チングによりエッチング除去し、シリコン基板1表面の
SiO2 膜2及びシリコン基板1の開口部側壁3aのS
iO2 膜2のみを残存させた(図1(d))。
Simultaneously with patterning the SiO 2 film 2a into a predetermined shape, the silicon substrate 1 was etched by about 3000 Å to form an opening 3 (FIG. 1 (b)). Then, after forming an oxide film of about 200 Å on the surface of the opening 3, the second insulating film Si, which is the second insulating film, is formed on the entire surface of the silicon substrate 1 including the opening 3 by the CVD method using SiH 4 and O 2.
An O 2 film 2b was formed on the order of 2500 Å (FIG. 1 (c)).
Then, the SiO 2 film 2b is etched away by about 2500 Å by anisotropic etching until the silicon substrate 1 on the bottom surface of the opening 3 is completely exposed, and the SiO 2 film 2 on the surface of the silicon substrate 1 and the opening of the silicon substrate 1 are removed. Side wall 3a S
Only the iO 2 film 2 was left (FIG. 1 (d)).

【0017】次いで、シリコン基板1上全面にアモルフ
ァスシリコン4を3000Å程度堆積し(図1
(e))、N2 雰囲気下、約1100℃で60分間程度
アニール処理を行った。このアニール処理により、シリ
コン基板1と直接接触している部分からアモルファスシ
リコン4が単結晶化し、開口部3内に埋設されたアモル
ファスシリコン4がほぼ完全に単結晶化する(図2
(f))。その後、SiO2 膜2を介してシリコン基板
1上に堆積された、単結晶化されていないアモルファス
シリコン4を選択的に除去した(図2(g))。
Next, about 3000 Å of amorphous silicon 4 is deposited on the entire surface of the silicon substrate 1 (see FIG. 1).
(E)), annealing treatment was performed at about 1100 ° C. for about 60 minutes in an N 2 atmosphere. By this annealing treatment, the amorphous silicon 4 is single-crystallized from the portion in direct contact with the silicon substrate 1, and the amorphous silicon 4 buried in the opening 3 is almost completely single-crystallized (FIG. 2).
(F)). Then, the non-single-crystallized amorphous silicon 4 deposited on the silicon substrate 1 through the SiO 2 film 2 was selectively removed (FIG. 2G).

【0018】そして、シリコン基板1上に形成されてい
るSiO2 膜2を選択的に、2000Å程度エッチング
することにより除去した(図2(h))。これにより、
SiO2 膜2で分離された、極めて小面積の活性領域を
形成することができた。次いで、シリコン基板1に不純
物を拡散させて所望の導電性に振り分けた後、シリコン
基板1上にゲート酸化膜である100Å程度のSiO2
膜6を形成し、さらにSiO2 膜6上に3500Å程度
のポリシリコンを堆積し、所定の形状にパターニングす
ることにより、ゲート電極7を形成した(図2
(i))。そして、ゲート電極7をマスクとして、例え
ば、不純物としてAsイオン(7)を80KeV、3×
1015ions/cm2 で注入した後、800℃の温度
で1時間の熱処理を行い、ソース/ドレイン領域8を形
成して(図2(j))半導体装置を作成した。
Then, the SiO 2 film 2 formed on the silicon substrate 1 was selectively removed by etching about 2000 Å (FIG. 2 (h)). This allows
It was possible to form an extremely small active area separated by the SiO 2 film 2. Then, impurities are diffused into the silicon substrate 1 and distributed to a desired conductivity, and then a SiO 2 film of about 100 Å which is a gate oxide film is formed on the silicon substrate 1.
The gate electrode 7 is formed by forming the film 6 and further depositing about 3500 Å polysilicon on the SiO 2 film 6 and patterning it into a predetermined shape (FIG. 2).
(I)). Then, using the gate electrode 7 as a mask, for example, As ions (7) as impurities are added at 80 KeV, 3 ×.
After implanting at 10 15 ions / cm 2 , heat treatment was performed at a temperature of 800 ° C. for 1 hour to form the source / drain regions 8 (FIG. 2 (j)), and the semiconductor device was prepared.

【0019】[0019]

【発明の効果】本発明に係る半導体装置の製造方法によ
れば、半導体基板に開口部を形成し、前記半導体基板表
面及び前記開口部側壁のみに絶縁膜を残存させた後、前
記半導体基板上全面にアモルファス半導体を堆積してア
ニール処理を行い、半導体基板上の前記アモルファス半
導体を選択的に除去する工程を含んで活性領域を分離す
るので、アモルファス半導体を自己整合的に単結晶化す
ることができる。
According to the method of manufacturing a semiconductor device of the present invention, an opening is formed in a semiconductor substrate, and an insulating film is left only on the surface of the semiconductor substrate and side walls of the opening, and then on the semiconductor substrate. An amorphous semiconductor is deposited on the entire surface, an annealing process is performed, and the active region is separated including a step of selectively removing the amorphous semiconductor on the semiconductor substrate, so that the amorphous semiconductor can be monocrystallized in a self-aligned manner. it can.

【0020】従って、従来のような、複雑で長時間を要
する工程を行うことなく、極めて小面積の素子分離領域
を形成することができ、ICあるいはLSI等の集積回
路の量産に寄与することが可能となる。
Therefore, it is possible to form an element isolation region having an extremely small area without performing a complicated and time-consuming process as in the prior art, which can contribute to mass production of integrated circuits such as ICs and LSIs. It will be possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の製造方法の実施例を
示す製造工程説明図である。
FIG. 1 is a manufacturing process explanatory view showing an embodiment of a semiconductor device manufacturing method according to the present invention.

【図2】本発明に係る半導体装置の製造方法の実施例を
示す製造工程説明図である。
FIG. 2 is a manufacturing process explanatory view showing the embodiment of the method of manufacturing a semiconductor device according to the present invention.

【図3】従来の半導体装置の製造方法を示す概略断面図
である。
FIG. 3 is a schematic cross-sectional view showing a conventional method for manufacturing a semiconductor device.

【図4】従来の半導体装置の製造方法を示す概略断面図
である。
FIG. 4 is a schematic cross-sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板(半導体基板) 2 SiO2 膜(絶縁膜) 2a SiO2 膜(第1の絶縁膜) 2b SiO2 膜(第2の絶縁膜) 3 開口部 3a 開口部側壁 4 アモルファスシリコン(アモルファス半導体)1 Silicon Substrate (Semiconductor Substrate) 2 SiO 2 Film (Insulating Film) 2a SiO 2 Film (First Insulating Film) 2b SiO 2 Film (Second Insulating Film) 3 Opening 3a Opening Sidewall 4 Amorphous Silicon (Amorphous Semiconductor) )

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 (i) 半導体基板表面に第1の絶縁膜を形
成する工程、 (ii)前記第1の絶縁膜を所定の形状にパターニングする
とともに前記半導体基板をエッチングして開口部を形成
する工程、 (iii) 前記開口部を含む半導体基板表面に第2の絶縁膜
を形成した後、エッチングにより前記開口部側壁のみに
前記第2の絶縁膜を残存させる工程、 (iv)前記半導体基板上全面にアモルファス半導体を堆積
し、アニール処理を行った後、半導体基板上の前記アモ
ルファス半導体を選択的に除去する工程、 を含んで活性領域を分離することを特徴とする半導体装
置の製造方法。
1. A step of forming (i) a first insulating film on a surface of a semiconductor substrate, and (ii) patterning the first insulating film into a predetermined shape and etching the semiconductor substrate to form an opening. And (iii) forming a second insulating film on the surface of the semiconductor substrate including the opening, and then leaving the second insulating film only on the side wall of the opening by etching, (iv) the semiconductor substrate A method of manufacturing a semiconductor device, comprising the steps of: depositing an amorphous semiconductor on the entire upper surface, performing an annealing treatment, and then selectively removing the amorphous semiconductor on the semiconductor substrate.
JP4107997A 1992-04-27 1992-04-27 Fabrication of semiconductor device Pending JPH05304203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4107997A JPH05304203A (en) 1992-04-27 1992-04-27 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4107997A JPH05304203A (en) 1992-04-27 1992-04-27 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05304203A true JPH05304203A (en) 1993-11-16

Family

ID=14473370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4107997A Pending JPH05304203A (en) 1992-04-27 1992-04-27 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05304203A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8784972B2 (en) 2007-11-26 2014-07-22 Kao Corporation Composite sheet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8784972B2 (en) 2007-11-26 2014-07-22 Kao Corporation Composite sheet

Similar Documents

Publication Publication Date Title
US20030049893A1 (en) Method for isolating semiconductor devices
US4658495A (en) Method of forming a semiconductor structure
US20030170941A1 (en) Method for low topography semiconductor device formation
JPH06232247A (en) Manufacturing of semiconductor layer isolated on insulation layer
JP2000036536A (en) Structure and method for isolating semiconductor device
JPH05304203A (en) Fabrication of semiconductor device
JPH0974189A (en) Manufacture of semiconductor device
JPH10303313A (en) Manufacture of cmos circuit
JP3003598B2 (en) Method for manufacturing semiconductor device
JPS5812732B2 (en) Manufacturing method for semiconductor devices
JPH09321131A (en) Semiconductor device and manufacture thereof
JPH04245662A (en) Manufacture of semiconductor device
JPH05275528A (en) Forming method of element isolating region
JP3321527B2 (en) Method for manufacturing semiconductor device
JPH06132292A (en) Semiconductor device and manufacture thereof
JPH11145274A (en) Semiconductor device and its manufacture
JPH06296016A (en) Semiconductor device
JP3057511B2 (en) Method for manufacturing semiconductor device having recess filling step
JPS59177941A (en) Manufacture of element isolation region
JPH07122752A (en) Manufacture of thin film transistor
JPS6068656A (en) Manufacture of semiconductor device
JP3445929B2 (en) Method for manufacturing semiconductor device
JPH06283676A (en) Manufacture of semiconductor device
JPH0624231B2 (en) Method for manufacturing semiconductor device
JPH0750274A (en) Formation of pattern selective tungsten growth

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040106

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040308

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040601

A521 Written amendment

Effective date: 20040621

Free format text: JAPANESE INTERMEDIATE CODE: A523

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040720

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040802

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 6

Free format text: PAYMENT UNTIL: 20100820

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 7

Free format text: PAYMENT UNTIL: 20110820

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 8

Free format text: PAYMENT UNTIL: 20120820

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20130820