JPS59177941A - Manufacture of element isolation region - Google Patents

Abstract

PURPOSE:To suppress small to the utmost the size conversion difference between mask size and an actually completed product, and to enable to form an element isolation region suitable for high integration by a method wherein bird beaks are removed, and moreover the influence of a channel stopper boron layer is removed. CONSTITUTION:A silicon dioxide film 22 is formed on the surface of a P type silicon single crystal substrate 21, moreover a silicon nitride film 23 is formed on the surface thereof, and the surface other than a groove forming region is covered with a photo resist 24. Then the silicon nitride film 23 and the silicon dioxide film 22 are removed using the photo resist 24 as a mask, moreover after the substrate 21 is etched to provide a groove A, the photo resist 24 is removed, moreover silicon dioxide films 25 are formed on the sides and the base of the groove A, and then a boron diffusion layer 26 is formed on the base of the groove A. Then after a silicon dioxide film 27 is formed on the whole surface of a wafer, a polycrystalline silicon layer 28 is grown thick moreover on the surface to bury a groove B, and the surface is flattened. Then the silicon layer 28 is removed from the surface, and after a silicon layer 28A is left only in the groove B, the silicon dioxide film 27 is thinned up to the middle, and moreover phosphorus is thermally diffused to the silicon dioxide film 27 thereof. After the silicon dioxide film 27A is removed, the silicon layer 28A and the silicon nitride films 23A are removed to form an element isolation region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a silicon dioxide film layer for isolation between elements.

Currently, as semiconductor devices become more highly integrated, MOS I
In C, device dimensions such as gate dimensions and aluminum wiring widths are becoming increasingly finer. Accordingly, the width of the isolation region between elements is also required to be miniaturized.

1,0CO as element isolation technology in conventional MO8IC
The 8th method is well known.

FIG. 1 is a diagram schematically showing a cross section of this LOGO8 structure, in which 11 is a p-type silicon single crystal substrate, 12 is a silicon dioxide film, 13 is a silicon nitride film as a heat-resistant oxide film, and I4 is a silicon nitride film as a heat-resistant oxide film.
A boron diffusion layer is used as a channel stopper, 15 is a thick silicon dioxide film formed in the field, and 15A is a bird's beak.

Such conventional LOCO8 method has the disadvantages that 1) bird's beak occurs, and 2) when the channel width becomes narrow, a narrow channel effect appears due to seepage of channel stopper boron into the device region. Bird's beak refers to a portion of the silicon dioxide film that occurs when forming the LOCO8 structure and penetrates into the element region, and its size is approximately 0.5 μm in the lateral direction.

For this reason, the dimensions of the actually completed element must be designed taking into account the amount of masking.

Furthermore, the narrow channel effect results in an increase in threshold voltage and a decrease in current drive capability. 5. The LOCO8 structure has a very large problem in terms of high integration.

The present invention eliminates the bird's beak, suppresses the difference in dimension conversion between the mask dimension and the actually completed product, and eliminates the influence of the channel stopper box, thereby making element isolation suitable for high integration. The purpose is to provide a manufacturing method for the area.

According to the present invention, a step of forming a groove on a silicon crystal substrate, a step of depositing a silicon dioxide film on the entire surface of the silicon substrate to completely fill the groove, and a step of forming polycrystalline silicon on the entire surface and then performing a sputter etching technique. phosphorous diffusion to the entire surface using the polycrystalline silicon as a mask to remove the polycrystalline silicon from the surface and leaving the polycrystalline silicon only in the upper part of the groove, and remove the dioxide formed in areas other than the inside of the groove. A device comprising the steps of selectively diffusing phosphorus only into a silicon film, and selectively etching away the silicon dioxide film into which the phosphorus has been diffused, leaving the silicon dioxide film inside the groove. A method for manufacturing a separation region is obtained.

Hereinafter, a typical embodiment of the present invention will be described in detail using FIG. 2.

FIG. 2 (al) shows that a silicon dioxide film 22 is formed on the surface of a p-type silicon single crystal substrate 21 by a thermal oxidation method, and a silicon nitride film 23 is further formed on that surface by a CVD method. It shows the state covered with photoresist 24.

The second Hbl is formed by etching the silicon nitride film 23. using the photoresist 24 as an etching-resistant mask. The silicon dioxide film 22 is etched away, and the silicon single crystal substrate 2
1 to form a trench A, the photoresist U is removed, and a silicon dioxide film 25 is formed on the side and bottom surfaces of the trench A by a thermal oxidation method. A boron diffusion layer 26 as a channel stopper is formed at the bottom of the trench A by ion implantation using 23A as a mask for ion implantation.

Figure 2 +01 is a CVD film that can sufficiently fill the groove A.
After forming a silicon dioxide film n on the entire surface of the wafer by the method,
Furthermore, a state in which polycrystalline silicon is grown thickly on the surface by the CVD method to sufficiently fill the groove B and to flatten the surface is shown.

FIG. 2 (11) shows that the polycrystalline silicon 4 is etched away from the surface and only the groove B is filled with polycrystalline silicon 28A.
After leaving the polycrystalline silicon 28A as an etching-resistant mask, the silicon dioxide film n is etched halfway to make it thinner, and phosphorus is then thermally diffused and pushed into the thinner silicon dioxide film 27. There is. The highly concentrated phosphorus diffused into the silicon dioxide film 27A stops at the surface of the silicon nitride film 23A. On the other hand, the polycrystalline silicon 2
Since the phosphorus diffused into the polycrystalline silicon 28A has a large interaction coefficient between the polycrystalline silicon and the silicon dioxide film,
The silicon dioxide film 27 formed at the bottom of the trench B from
B+= only a low concentration of phosphorus is diffused. Therefore, there is a large difference (more than one order of magnitude) in etching rate between the silicon dioxide film 27B formed inside the groove A and the silicon dioxide film 27A formed in other parts due to the difference in phosphorus concentration due to phosphorus diffusion. . The silicon dioxide film 27A in which phosphorus has been diffused can be etched using an etching solution in which hydrofluoric acid is sufficiently diluted with pure water, for example, a solution diluted 30 times. 27
Since the etching rate of B becomes slower, the silicon dioxide film 27B can be left only in the groove A with better control.

FIG. 2+e) shows the silicon dioxide film 27A in which phosphorus is diffused using the polycrystalline silicon 28A as an anti-etching mask.
After etching away the polycrystalline silicon 28A and the silicon nitride film 23A, the element isolation region is formed. As described above, there is a large difference in etching rate between the inside of the groove B and other parts of the silicon dioxide film depending on the presence or absence of phosphorus diffusion. Therefore, the silicon dioxide film 27B in the groove B
can be left without significant over-etching.

The present invention has the following features compared to the conventional LOCO8 method.

1) Since the silicon dioxide film 27C is buried in the trench by the CVD method to perform element isolation, there is no bird's beak, and the difference in pattern size conversion from the mask size is very small.

2) Since a boron diffusion layer as a channel stopper is formed at the bottom of the groove A, if the groove is made deep enough, the influence of boron on the device characteristics can be almost eliminated.

3) Since the wafer surface becomes flat after the element isolation region is formed, when patterning is subsequently performed using a photoresist, no change in the pannular dimension due to surface irregularities occurs.

4) Since device isolation is performed by burying a silicon dioxide film in the trench using the CVD method, there is no need for a high-temperature, long-term heat treatment process.

Therefore, the redistribution of impurities can be kept small.

As described above, according to the present invention, the pattern dimension conversion difference from the mask dimension is very small and is not affected by the channel stopper boron. A method for manufacturing a membrane layer is obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an inter-element isolation region formed by the conventionally known LOCO8 method, and FIG.
(bl, fol, (di, tel
+ is a schematic sectional view showing a non-example of the present invention following the process. In the figure, each symbol represents the following. 11, 12: Silicon substrate, 12, 23, 23A:
Silicon nitride film, 13, 26: Channel stopper, 1
4, 22, 2527.278.27C: Silicon dioxide film, 27A Niline-diffused silicon dioxide film, 28, 28
A: Polycrystalline silicon 24: Photoresist. ,,,／ ,−−・, For patent attorneys! ! Z Back/Pa. '-- (9) Fig. 1 Fig. 2 (a and 2 b)

Claims (1)

[Claims] A step of providing a groove on a silicon crystal substrate, a step of depositing a silicon dioxide film on the entire surface of the silicon substrate to completely fill the groove, and after forming polycrystalline silicon on the entire surface. using a sputter etching technique [removing the polycrystalline silicon from the surface and leaving the polycrystalline silicon only in the upper part of the groove;
a step of diffusing phosphorus over the entire surface using the polycrystalline silicon as a mask and selectively diffusing phosphorus only into the silicon dioxide film formed outside the trench; selectively diffusing the silicon dioxide film in which the phosphorus has been diffused; A method of manufacturing an element isolation region, comprising the step of etching away the silicon dioxide film to leave the silicon dioxide film inside the trench.