JPH0661343A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0661343A
JPH0661343A JP20767592A JP20767592A JPH0661343A JP H0661343 A JPH0661343 A JP H0661343A JP 20767592 A JP20767592 A JP 20767592A JP 20767592 A JP20767592 A JP 20767592A JP H0661343 A JPH0661343 A JP H0661343A
Authority
JP
Japan
Prior art keywords
silicon dioxide
dioxide film
single crystal
substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20767592A
Other languages
Japanese (ja)
Other versions
JP3109549B2 (en
Inventor
Toshihiro Ogawa
智弘 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP04207675A priority Critical patent/JP3109549B2/en
Publication of JPH0661343A publication Critical patent/JPH0661343A/en
Application granted granted Critical
Publication of JP3109549B2 publication Critical patent/JP3109549B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To form the element isolation region in a semiconductor device, which is provided on a semiconductor substrate with the surface consisting of a single crystal silicon layer, in an even film thickness regardless of the size of the width of the region. CONSTITUTION:A silicon dioxide film 102 is formed on a silicon substrate 101 by ion-implanting oxygen, an element isolation region formation part in a single crystal silicon layer 103 on the surface of the substrate 101 is selectively removed to form a recessed part, in which the film 102 is exposed, on the bottom of the layer 103 and a silicon dioxide film 105 is selectively formed in this recessed part by a liquid phase growth method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に素子分離領域の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an element isolation region.

【0002】[0002]

【従来の技術】素子分離は大きく2つの目的がある。ま
ず第1は、トランジスタなど半導体基板表面に形成され
た素子と素子との絶縁を行なうことである。第2は、ト
ランジスタなど半導体基板表面に形成された素子の無い
部分を厚い(数百nm〜10μm)絶縁膜でおおうこと
により、この絶縁膜上の配線や素子と半導体基板との間
の浮遊容量の低減を行なうことである。
2. Description of the Related Art Element isolation has two main purposes. The first is to insulate elements such as transistors formed on the surface of a semiconductor substrate from each other. Second, by covering a portion such as a transistor, which is not formed on the surface of the semiconductor substrate, with a thick insulating film (several hundreds nm to 10 μm), a floating capacitance between the wiring on the insulating film and the device and the semiconductor substrate is formed. Is to reduce.

【0003】半導体装置の製造方法を説明するための工
程順の断面図である図4を参照すると、従来の素子分離
領域の形成方法は、初めに、シリコン基板201上に窒
化シリコン膜202を形成する。次に、ホトレジスト2
00をマスクに窒化シリコン202のパターニングを行
なう〔図4(a)〕。続いて、ホトレジスト200に被
われていない部分のシリコン基板201を等方性エッチ
ングによりエッチングする〔図4(b)〕。次に、ホト
レジスト200除去後、窒化シリコン膜203を形成す
る〔図4(c)〕。次に窒化シリコン膜202の下側に
位置する部分を除き、異方性エッチングにより窒化シリ
コン膜203を除去する〔図4(d)〕。次に、水蒸気
酸化を行ない、窒化シリコン膜202,203に被われ
ていない部分のシリコン基板201表面を2酸化シリコ
ン膜204に変換する〔図4(e)〕。次に、窒化シリ
コン膜202,203を除去し、図4(f)に示す構造
を得る。
Referring to FIG. 4 which is a sectional view in the order of steps for explaining a method for manufacturing a semiconductor device, in the conventional method for forming an element isolation region, first, a silicon nitride film 202 is formed on a silicon substrate 201. To do. Next, photoresist 2
The silicon nitride 202 is patterned using 00 as a mask [FIG. 4 (a)]. Subsequently, the portion of the silicon substrate 201 not covered with the photoresist 200 is etched by isotropic etching [FIG. 4 (b)]. Next, after removing the photoresist 200, a silicon nitride film 203 is formed [FIG. 4 (c)]. Next, the silicon nitride film 203 is removed by anisotropic etching except the portion located below the silicon nitride film 202 [FIG. 4 (d)]. Next, steam oxidation is performed to convert the surface of the silicon substrate 201 not covered with the silicon nitride films 202 and 203 into a silicon dioxide film 204 [FIG. 4 (e)]. Next, the silicon nitride films 202 and 203 are removed to obtain the structure shown in FIG.

【0004】半導体装置の製造方法を説明するための工
程順の断面図である図5を参照すると、従来の素子分離
領域の別の形成方法は、まず、シリコン基板211上に
ホトレジスト212をパターニングし、次に異方性エッ
チングによりシリコン基板211に溝を形成する〔図5
(a)〕。次に、2酸化シリコン膜213を化学的気相
成長法(CVD)により形成する〔図5(b)〕。次
に、2酸化シリコン膜213をエッチングし、図5
(c)に示す構造を得る。
Referring to FIG. 5, which is a sectional view in order of steps for explaining a method for manufacturing a semiconductor device, another conventional method for forming an element isolation region is to pattern a photoresist 212 on a silicon substrate 211. Then, a groove is formed in the silicon substrate 211 by anisotropic etching [FIG.
(A)]. Next, a silicon dioxide film 213 is formed by chemical vapor deposition (CVD) [FIG. 5 (b)]. Next, the silicon dioxide film 213 is etched to obtain the structure shown in FIG.
The structure shown in (c) is obtained.

【0005】[0005]

【発明が解決しようとする課題】上述した従来の半導体
装置の素子分離領域の形成方法では、以下に示す欠点を
有していた。まず第1の方法では、ホトレジスト200
のパターンに比べ、2酸化シリコン膜204は横方向に
広がり、素子分離領域の幅を増大させる。このことは半
導体装置の微細化を行なう上での障害となる。また、第
2の方法では、シリコン基板211の溝の幅が広い場
合、2酸化シリコン膜213の膜厚が溝の中央付近で薄
くなる。このため広い幅の素子分離領域を形成できない
という欠点を有していた。
The above-described conventional method for forming the element isolation region of the semiconductor device has the following drawbacks. First, in the first method, the photoresist 200
The silicon dioxide film 204 expands in the lateral direction as compared with the above pattern, increasing the width of the element isolation region. This hinders miniaturization of the semiconductor device. In the second method, when the width of the groove of the silicon substrate 211 is wide, the film thickness of the silicon dioxide film 213 becomes thin near the center of the groove. For this reason, there is a drawback that a wide element isolation region cannot be formed.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、表面が単結晶シリコンからなる半導体基体に
設けられた半導体装置の素子分離領域の形成方法におい
て、半導体基体の表面の素子分離領域が形成される領域
に、底面に第1の2酸化シリコン膜を有する凹部を形成
する第1の工程と、この凹部に、液相成長による第2の
2酸化シリコン膜を埋設する第2の工程とを有してい
る。
According to a method of manufacturing a semiconductor device of the present invention, in a method of forming an element isolation region of a semiconductor device provided on a semiconductor substrate whose surface is made of single crystal silicon, element isolation on the surface of the semiconductor substrate is performed. A first step of forming a recess having a first silicon dioxide film on the bottom surface in a region where the region is formed, and a second step of burying a second silicon dioxide film by liquid phase growth in the recess. And the process.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0008】半導体装置の製造方法を説明するための工
程順の断面図である図1を参照すると、本発明の第1の
実施例は、まず、シリコン基板101に酸素をイオン注
入(例えばエネルギー200keV,ドース量1018
-2)し、この部分のシリコンを2酸化シリコン膜10
2に変換し、シリコン基板101から単結晶シリコン層
103を電気的に分離する〔図1(a)〕。
Referring to FIG. 1 which is a sectional view in order of steps for explaining a method for manufacturing a semiconductor device, according to a first embodiment of the present invention, first, oxygen is ion-implanted into a silicon substrate 101 (for example, energy is 200 keV). , Dose amount 10 18 c
m -2 ) and the silicon dioxide film 10
2, and the single crystal silicon layer 103 is electrically separated from the silicon substrate 101 [FIG. 1 (a)].

【0009】次に、ホトレジスト104を単結晶シリコ
ン層103上に形成し、リソグラフィにより素子分離領
域形成予定部分のホトレジスト104を除去し、パター
ニングを行なう。次に、異方性エッチングによりホトレ
ジスト104に被われていない部分の単結晶シリコン層
103を除去する〔図1(b)〕。
Next, a photoresist 104 is formed on the single crystal silicon layer 103, the photoresist 104 in a portion where an element isolation region is to be formed is removed by lithography, and patterning is performed. Next, the single crystal silicon layer 103 which is not covered with the photoresist 104 is removed by anisotropic etching [FIG. 1 (b)].

【0010】次に、ホトレジスト104除去後、2酸化
シリコン膜105を液相成長法(LPD)により、2酸
化シリコン膜102の露出している部分にのみ選択成長
し、単結晶シリコン層103の上面と2酸化シリコン膜
105の上面とをほぼ同じ高さにする〔図1(c)〕。
なお、ホトレジスト104の除去は2酸化シリコン膜1
05形成後でもよい。
Next, after removing the photoresist 104, the silicon dioxide film 105 is selectively grown by liquid phase epitaxy (LPD) only on the exposed portion of the silicon dioxide film 102, and the upper surface of the single crystal silicon layer 103 is grown. And the upper surface of the silicon dioxide film 105 are made substantially at the same height [FIG. 1 (c)].
The photoresist 104 is removed by the silicon dioxide film 1
05 It may be after formation.

【0011】上記液相成長法は、例えばH2 SiF6
0wt%の水溶液1リットルに対してH3 BO4 0.6
wt%の水溶液を1時間に10〜50ミリリットル添加
する溶液に、したことにより成膜される。このとき、凹
部の底部に露出した2酸化シリコン膜102上にのみ選
択的にLPD法によるこの2酸化シリコン膜105の成
長が起る。
The above liquid phase growth method is, for example, H 2 SiF 6 4
H 3 BO 4 0.6 per liter of 0 wt% aqueous solution
A film is formed by applying a wt% aqueous solution to a solution to which 10 to 50 milliliters are added per hour. At this time, the growth of the silicon dioxide film 105 by the LPD method occurs selectively only on the silicon dioxide film 102 exposed at the bottom of the recess.

【0012】半導体装置の製造方法を説明するための工
程順の断面図である図2を参照すると、本発明の第2の
実施例は、まず、第1の単結晶シリコン基板(図示せ
ず)の表面に膜厚約1μmの2酸化シリコン膜111を
形成する。次に、この2酸化シリコン膜111の表面に
第2の単結晶シリコン基板(図示せず)を接着し、この
第2の単結晶シリコン基板の表面の研削を行ない、膜厚
2〜3μmの単結晶シリコン層112を形成する〔図2
(a)〕。以下、上記第1の実施例と同様の方法によ
り、ホトレジスト113をマスクに単結晶シリコン層1
12の異方性エッチングを行なう〔図2(b)〕。次
に、ホトレジスト113の除去後、液相成長法により2
酸化シリコン膜114を形成する〔図2(c)〕。
Referring to FIG. 2 which is a sectional view in order of steps for explaining a method for manufacturing a semiconductor device, a second embodiment of the present invention will be described below. First, a first single crystal silicon substrate (not shown) will be described. A silicon dioxide film 111 having a film thickness of about 1 μm is formed on the surface of. Next, a second single crystal silicon substrate (not shown) is adhered to the surface of the silicon dioxide film 111, and the surface of the second single crystal silicon substrate is ground to obtain a single crystal film having a thickness of 2 to 3 μm. A crystalline silicon layer 112 is formed [FIG.
(A)]. Thereafter, the single crystal silicon layer 1 is formed by using the photoresist 113 as a mask by the same method as in the first embodiment.
12 is anisotropically etched [FIG. 2 (b)]. Next, after the photoresist 113 is removed, 2
A silicon oxide film 114 is formed [FIG. 2 (c)].

【0013】なお、上記第1,および第2の実施例は、
本発明をSOI基板に適用したものであるが、石英基板
の表面にエピタキシャルシリコン層を有する半導体基体
に対しても本発明は適用できる。
The first and second embodiments are as follows.
Although the present invention is applied to an SOI substrate, the present invention can also be applied to a semiconductor substrate having an epitaxial silicon layer on the surface of a quartz substrate.

【0014】半導体装置の製造方法を説明するための工
程順の断面図である図3を参照すると、本発明の第3の
実施例は、まず、p- 型のシリコン基板121の上面よ
りヒ素を拡散させ、n+ 埋め込み層122を形成する。
次に、この上に膜厚約1μmのn- エピタキシャル層1
23を形成する〔図3(a)〕。
Referring to FIG. 3 which is a sectional view in the order of steps for explaining a method for manufacturing a semiconductor device, in the third embodiment of the present invention, first, arsenic is removed from the upper surface of a p type silicon substrate 121. Diffusion is performed to form the n + buried layer 122.
Next, an n - epitaxial layer 1 having a film thickness of about 1 μm is formed thereon.
23 is formed (FIG. 3A).

【0015】次に、ホトレジスト124をマスクに異方
性シリコンエッチングを行ない、素子分離領域形成予定
部分のn- エピタキシャル層123を除去し、n+ 埋め
込み層122を露出させる〔図3(b)〕。
Next, anisotropic silicon etching is performed using the photoresist 124 as a mask to remove the n - epitaxial layer 123 in the portion where the element isolation region is to be formed and expose the n + buried layer 122 [FIG. 3 (b)]. .

【0016】次に、ホトレジスト124除去後、熱酸化
を行ないn- エピタキシャル層123およびn+ 埋め込
み層122の表面に2酸化シリコン膜125を形成す
る。このとき、n- エピタキシャル層123に比べn+
埋め込み層122は酸化速度が速いため、この部分の2
酸化シリコン膜125は他に比べ厚くなる〔図3
(c)〕。
Next, after removing the photoresist 124, thermal oxidation is performed to form a silicon dioxide film 125 on the surfaces of the n epitaxial layer 123 and the n + buried layer 122. At this time, compared with the n epitaxial layer 123, n +
Since the buried layer 122 has a high oxidation rate, 2
The silicon oxide film 125 becomes thicker than the others [FIG.
(C)].

【0017】次に、希フッ酸溶液を用いて2酸化シリコ
ン膜125をエッチングする。
Next, the silicon dioxide film 125 is etched using a dilute hydrofluoric acid solution.

【0018】このときのエッチング時間はn- エピタキ
シャル層123上の2酸化シリコン膜125は完全に除
去し、n+ 埋め込み層122上の2酸化シリコン膜12
5は残存する条件に設定する〔図3(d)〕。
At this time, the etching time is such that the silicon dioxide film 125 on the n epitaxial layer 123 is completely removed, and the silicon dioxide film 12 on the n + buried layer 122 is removed.
5 is set to the remaining condition [FIG. 3 (d)].

【0019】次に、上記第1,第2の実施例と同様に、
液相成長法により2酸化シリコン膜126を形成する
〔図3(e)〕。
Next, similarly to the above first and second embodiments,
A silicon dioxide film 126 is formed by a liquid phase growth method [FIG. 3 (e)].

【0020】[0020]

【発明の効果】以上説明したように本発明は、素子分離
領域の溝の底部に形成した第1の2酸化シリコン膜上に
選択的に第2の2酸化シリコン膜を成長するため、素子
分離領域幅の大小にかかわらず均一な膜厚のシリコン酸
化膜を得ることができる。
As described above, according to the present invention, the second silicon dioxide film is selectively grown on the first silicon dioxide film formed at the bottom of the trench in the device isolation region. A silicon oxide film having a uniform film thickness can be obtained regardless of the size of the region width.

【0021】また、本発明の方法は、従来の方法で問題
となった2酸化シリコン膜の横方向への拡幅を生じない
ため、パターニングしたホトレジストと同じ幅の素子分
離領域を形成することができる。このため非常に細い
(ホトレジストの加工限界)の素子分離領域形成が可能
である。これにより半導体装置の高集積化と高集積化に
よる配線長短縮,寄生容量低減,抵抗低減による高性能
化が可能となるという効果を有する。
Further, since the method of the present invention does not cause the lateral widening of the silicon dioxide film, which has been a problem in the conventional method, an element isolation region having the same width as the patterned photoresist can be formed. . Therefore, it is possible to form an extremely thin element isolation region (processing limit of photoresist). As a result, there is an effect that high integration of the semiconductor device and reduction of wiring length due to high integration, reduction of parasitic capacitance, and high performance by reduction of resistance are possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための工程順
の断面図である。
1A to 1D are cross-sectional views in order of processes for explaining a first embodiment of the present invention.

【図2】本発明の第2の実施例を説明するための工程順
の断面図である。
2A to 2D are cross-sectional views in order of a process, for illustrating a second embodiment of the present invention.

【図3】本発明の第3の実施例を説明するための工程順
の断面図である。
FIG. 3 is a cross-sectional view in process order for explaining a third embodiment of the present invention.

【図4】従来の半導体装置の製造方法を説明するための
工程順の断面図である。
4A to 4C are cross-sectional views in order of processes for explaining a conventional method for manufacturing a semiconductor device.

【図5】従来の半導体装置の別の製造方法を説明するた
めの工程順の断面図である。
FIG. 5 is a cross-sectional view in process order for explaining another conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

101,121,201,211 シリコン基板 102,105,111,114,125,126,2
04,213 2酸化シリコン膜 103,112 単結晶シリコン層 104,113,124,200,212 ホトレジ
スト 122 n+ 埋め込み層 123 n- エピタキシャル層 202,203 窒化シリコン膜
101, 121, 201, 211 Silicon substrate 102, 105, 111, 114, 125, 126, 2
04,213 silicon dioxide film 103,112 single crystal silicon layer 104,113,124,200,212 photoresist 122 n + buried layer 123 n - epitaxial layer 202,203 silicon nitride film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 表面が単結晶シリコンからなる半導体基
体に設けられた半導体装置の素子分離領域の形成方法に
おいて、 前記半導体基体の表面の前記素子分離領域が形成される
領域に、底面に第1の2酸化シリコン膜を有する凹部を
形成する第1の工程と、 前記凹部を液相成長法による第2の2酸化シリコン膜で
埋設する工程と、 を有することを特徴とする半導体装置の製造方法。
1. A method of forming an element isolation region of a semiconductor device, the surface of which is provided on a semiconductor substrate made of single crystal silicon, comprising: a first surface on a bottom surface of the semiconductor substrate on which the element isolation region is formed. 1. A method of manufacturing a semiconductor device, comprising: a first step of forming a concave portion having a silicon dioxide film of 2; and a step of filling the concave portion with a second silicon dioxide film of a liquid phase growth method. .
【請求項2】 前記半導体基体が、所定に深さに酸素の
イオン注入により形成された2酸化シリコン層を有する
単結晶シリコン基板であることと、 前記第1の2酸化シリコン膜が、該2酸化シリコン層で
あることと、 を併せて特徴とする請求項1記載の半導体装置の製造方
法。
2. The semiconductor substrate is a single crystal silicon substrate having a silicon dioxide layer formed by ion implantation of oxygen to a predetermined depth, and the first silicon dioxide film is formed of the silicon dioxide film. The method of manufacturing a semiconductor device according to claim 1, further comprising: being a silicon oxide layer.
【請求項3】 前記半導体基体が、第1の単結晶シリコ
ン基板と、前記第1の単結晶シリコン基板の表面に形成
された前記第1の2酸化シリコン膜と、前記第1の2酸
化シリコン膜の表面に接着された第2の単結晶シリコン
基板とからなることを特徴とする請求項1記載の半導体
装置の製造方法。
3. The semiconductor substrate comprises a first single crystal silicon substrate, the first silicon dioxide film formed on the surface of the first single crystal silicon substrate, and the first silicon dioxide. 2. The method of manufacturing a semiconductor device according to claim 1, comprising a second single crystal silicon substrate adhered to the surface of the film.
【請求項4】 前記半導体基体が、石英基板と、前記石
英基板の表面に形成されたエピタキシャルシリコン層
と、からなることを特徴とする請求項1記載の半導体装
置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate comprises a quartz substrate and an epitaxial silicon layer formed on the surface of the quartz substrate.
【請求項5】 前記半導体基体が、一導電型の単結晶シ
リコン基板と、前記一導電型の単結晶シリコン基板の表
面に形成された高濃度の逆導電型の埋め込み層と、前記
高濃度の逆導電型の埋め込み層の表面に設けられた低濃
度の逆導電型の単結晶シリコン層とからなることと、 前記第1の工程が、前記単結晶シリコン層の表面の前記
素子分離領域が形成される領域に、前記底面が前記高濃
度の逆導電型の埋め込み層からなる前記凹部を形成する
工程と、前記凹部の底面に露出した前記高濃度の逆導電
型の埋め込み層の表面,および前記単結晶シリコン層の
表面に、熱酸化による2酸化シリコン膜を形成する工程
と、前記単結晶シリコン層の上面が露出するまで前記熱
酸化による2酸化シリコン膜を除去し、前記凹部の底面
に露出した前記高濃度の逆導電型の埋め込み層の表面に
前記熱酸化による2酸化シリコン膜からなる前記第1の
2酸化シリコン膜を形成する工程とからなることとを併
せて特徴とする請求項1記載の半導体装置の製造方法。
5. The semiconductor substrate comprises one conductivity type single crystal silicon substrate, a high concentration reverse conductivity type buried layer formed on a surface of the one conductivity type single crystal silicon substrate, and the high concentration A low-concentration reverse-conductivity-type single-crystal silicon layer provided on the surface of the reverse-conductivity-type buried layer; and the first step includes forming the element isolation region on the surface of the single-crystal silicon layer. In the region where the bottom surface is formed of the high-concentration reverse conductivity type buried layer, a surface of the high-concentration reverse conductivity type buried layer exposed on the bottom surface of the recess, and Forming a silicon dioxide film by thermal oxidation on the surface of the single crystal silicon layer; removing the silicon dioxide film by thermal oxidation until the upper surface of the single crystal silicon layer is exposed, and exposing the bottom surface of the recess. Said Takano 2. The semiconductor device according to claim 1, further comprising the step of forming the first silicon dioxide film made of the silicon dioxide film by the thermal oxidation on the surface of the reverse conductivity type buried layer. Manufacturing method.
【請求項6】 前記第2の工程が、少なくともフッ素を
含有する水溶液中で行なわれることと、 前記第2の2酸化シリコン膜が、フッ素を含有すること
とを併せて特徴とする請求項1記載の半導体装置の製造
方法。
6. The method according to claim 1, wherein the second step is performed in an aqueous solution containing at least fluorine, and the second silicon dioxide film contains fluorine. A method for manufacturing a semiconductor device as described above.
JP04207675A 1992-08-04 1992-08-04 Method for manufacturing semiconductor device Expired - Fee Related JP3109549B2 (en)

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Application Number Priority Date Filing Date Title
JP04207675A JP3109549B2 (en) 1992-08-04 1992-08-04 Method for manufacturing semiconductor device

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JPH0661343A true JPH0661343A (en) 1994-03-04
JP3109549B2 JP3109549B2 (en) 2000-11-20

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07201972A (en) * 1993-12-28 1995-08-04 Nec Corp Manufacture of semiconductor device
US5561076A (en) * 1992-04-02 1996-10-01 Nec Corporation Method of fabricating an isolation region for a semiconductor device using liquid phase deposition
KR20020046477A (en) * 2000-12-14 2002-06-21 박종섭 Method for making isolation layer of semicondcutor device
US6417073B2 (en) 2000-03-21 2002-07-09 Nec Corporation Method for forming element isolating region

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561076A (en) * 1992-04-02 1996-10-01 Nec Corporation Method of fabricating an isolation region for a semiconductor device using liquid phase deposition
JPH07201972A (en) * 1993-12-28 1995-08-04 Nec Corp Manufacture of semiconductor device
US6417073B2 (en) 2000-03-21 2002-07-09 Nec Corporation Method for forming element isolating region
KR20020046477A (en) * 2000-12-14 2002-06-21 박종섭 Method for making isolation layer of semicondcutor device

Also Published As

Publication number Publication date
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