JPH0555361A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH0555361A
JPH0555361A JP21700591A JP21700591A JPH0555361A JP H0555361 A JPH0555361 A JP H0555361A JP 21700591 A JP21700591 A JP 21700591A JP 21700591 A JP21700591 A JP 21700591A JP H0555361 A JPH0555361 A JP H0555361A
Authority
JP
Japan
Prior art keywords
oxide film
film
trench
silicon
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP21700591A
Other languages
Japanese (ja)
Inventor
Tatsuya Deguchi
達也 出口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21700591A priority Critical patent/JPH0555361A/en
Publication of JPH0555361A publication Critical patent/JPH0555361A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device provided with a trench as an element isolating region, where a substrate on which elements are formed is lessened in stress and level difference by a method wherein the change of processes which can be easily carried out is executed. CONSTITUTION:A semiconductor device is provided with a trench 1a as an element isolating region, a silicon thermal oxide film 3, a silicon nitride film 4, and a silicon oxide film 5 are successively inside the trench 1a, and a polysilicon film 6 whose surface is covered with a thermal oxide film 6a is formed so as to film the center part of the trench 1a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、素子分離領域としてト
レンチを備えた半導体装置及びその製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench as an element isolation region and a method of manufacturing the same.

【0002】近年の半導体装置の高集積化に伴う微細化
に対応するためには、素子分離領域として用いる面積を
できる限り小さくすることが必要であり、また製品歩留
の低下を防止するためには素子を形成する基板のストレ
スを減少させ、形成される段差を減少させるようにする
ことが要求されている。
In order to cope with the miniaturization of semiconductor devices in recent years due to higher integration, it is necessary to make the area used as an element isolation region as small as possible, and to prevent a decrease in product yield. Are required to reduce the stress of the substrate on which the device is formed and to reduce the steps formed.

【0003】以上のような状況からできる限り小さな面
積内に素子を形成する基板のストレスを減少させ、形成
される段差を減少させることが可能な素子分離領域を備
えた半導体装置及びその製造方法が要望されている。
Under the circumstances as described above, a semiconductor device having an element isolation region capable of reducing stress on a substrate on which an element is formed and reducing a step formed in an area as small as possible, and a method of manufacturing the same are provided. Is requested.

【0004】[0004]

【従来の技術】従来のトレンチを素子分離領域として用
いる半導体装置及びその製造方法について図5〜図8に
より詳細に説明する。
2. Description of the Related Art A conventional semiconductor device using a trench as an element isolation region and a method of manufacturing the same will be described in detail with reference to FIGS.

【0005】図5は従来の半導体装置のトレンチ部を示
す側断面図、図6〜図8は従来の半導体装置の製造方法
を工程順に示す側断面図である。従来のトレンチを素子
分離領域として用いている半導体装置は、図5に示すよ
うに、半導体基板11に形成されているトレンチ11a 内
に、シリコン熱酸化膜13,シリコン窒化膜14が順次積層
して形成されており、表面が熱酸化膜16a にて被覆され
たポリシリコン膜16が、このトレンチ11a の中心部を充
填するように形成されている。
FIG. 5 is a side sectional view showing a trench portion of a conventional semiconductor device, and FIGS. 6 to 8 are side sectional views showing a method of manufacturing the conventional semiconductor device in the order of steps. As shown in FIG. 5, a conventional semiconductor device using a conventional trench as an element isolation region has a silicon thermal oxide film 13 and a silicon nitride film 14 sequentially stacked in a trench 11a formed in a semiconductor substrate 11. The polysilicon film 16 which is formed and whose surface is covered with the thermal oxide film 16a is formed so as to fill the central portion of the trench 11a.

【0006】このような半導体装置の製造方法を図6〜
図8により工程順に詳細に説明する。まず図6(a) に示
すように、半導体基板11の表面にレジストを塗布してレ
ジスト膜12を形成し、マスクを用いるフォトリソグラフ
ィ技術によりこのレジスト膜をパターニングしてトレン
チ11a 形成部に開口12a を形成し、ドライエッチング法
によりこの半導体基板11に幅1.0 μm , 深さ5.0 μm の
トレンチ11a を形成した後、レジスト膜12をマスクとし
てイオン注入法によりイオンを注入してチャンネルカッ
ト11b をトレンチ11a の底部に形成する。
A method of manufacturing such a semiconductor device will be described with reference to FIGS.
Details will be described in order of steps with reference to FIG. First, as shown in FIG. 6A, a resist is applied to the surface of the semiconductor substrate 11 to form a resist film 12, and the resist film is patterned by a photolithography technique using a mask to form an opening 12a in the trench 11a forming portion. Then, a trench 11a with a width of 1.0 μm and a depth of 5.0 μm is formed in the semiconductor substrate 11 by dry etching, and then ion is implanted by ion implantation using the resist film 12 as a mask to form a channel cut 11b in the trench 11a. Formed on the bottom of the.

【0007】つぎにレジスト膜12を除去し、半導体基板
11を1,000 °Cに加熱して半導体基板11の表面及びトレ
ンチ11a の側壁と底面に延在するシリコン熱酸化膜を形
成すると、図6(b) に示すようにトレンチ11a の側壁が
膜厚 3,000Åのシリコン熱酸化膜13になりトレンチ11a
の幅は約 7,000Åになる。
Next, the resist film 12 is removed to remove the semiconductor substrate.
When 11 is heated to 1,000 ° C to form a silicon thermal oxide film extending on the surface of the semiconductor substrate 11 and the sidewalls and bottom of the trench 11a, the sidewall of the trench 11a has a film thickness of 3,000 as shown in Fig. 6 (b). Å Silicon thermal oxide film 13 becomes trench 11a
Is about 7,000Å.

【0008】ついで図7(a) に示すようにこのシリコン
熱酸化膜13の全面に膜厚 500Åのシリコン窒化膜14をC
VD法により形成すると、トレンチ11a の幅は約 6,000
Åになる。
Then, as shown in FIG. 7A, a silicon nitride film 14 having a film thickness of 500 Å is formed on the entire surface of the silicon thermal oxide film 13 by C.
When formed by the VD method, the width of the trench 11a is about 6,000.
Become Å.

【0009】更に図7(b) に示すように、半導体基板11
の表面及びトレンチの側壁と底面に延在するこのシリコ
ン窒化膜14の表面に膜厚2μm のポリシリコン膜16をC
VD法により成長させると、トレンチの中心部はポリシ
リコン膜16にて充填される。
Further, as shown in FIG. 7B, the semiconductor substrate 11
A polysilicon film 16 having a thickness of 2 μm is formed on the surface of the silicon nitride film 14 and the surface of the silicon nitride film 14 extending to the side wall and the bottom surface of the trench.
When grown by the VD method, the central portion of the trench is filled with the polysilicon film 16.

【0010】ここでこのポリシリコン膜16をドライエッ
チングにより全面エッチングすると、図8(a) に示すよ
うにトレンチ内にはポリシリコン膜16が残り、半導体基
板11の表面ではシリコン窒化膜14が露出する。
When the entire surface of the polysilicon film 16 is etched by dry etching, the polysilicon film 16 remains in the trench and the silicon nitride film 14 is exposed on the surface of the semiconductor substrate 11 as shown in FIG. 8 (a). To do.

【0011】そして半導体基板11を900〜1,000°Cに加
熱すると、図8(b) に示すようにポリシリコン膜16の表
面が熱酸化されて熱酸化膜16aが形成されるが、トレン
チ11aの境界部の膜厚が中央部の膜厚よりも薄く形成さ
れる。
When the semiconductor substrate 11 is heated to 900 to 1,000 ° C., the surface of the polysilicon film 16 is thermally oxidized to form a thermal oxide film 16a as shown in FIG. 8 (b). The film thickness at the boundary is formed thinner than that at the center.

【0012】最後にドライエッチングを行うと、表面の
膜厚約 500Åのシリコン窒化膜14が除去され、図5に示
すようにトレンチ11a の境界部の熱酸化膜16a の膜厚が
中央部の膜厚よりも薄くなっている。
Finally, when dry etching is performed, the silicon nitride film 14 having a film thickness of about 500 Å on the surface is removed, and as shown in FIG. 5, the thermal oxide film 16a at the boundary of the trench 11a has a film thickness at the center. It is thinner than the thickness.

【0013】[0013]

【発明が解決しようとする課題】以上説明した製造方法
により製造した半導体装置においては、図5に示すよう
にトレンチ11a 内に充填したポリシリコン膜16を熱酸化
して表面をシリコンの熱酸化膜16a にした場合に、シリ
コン窒化膜14と接している部分においては酸素の供給不
足のために、形成される熱酸化膜16a の膜厚が中央部に
比して薄くなるので、この部分の膜厚を必要な厚さにす
ると、中央部の膜厚が必要以上に厚くなって半導体基板
1のストレスが大きくなり、この熱酸化膜16a とシリコ
ン熱酸化膜13との段差も大きくなるという問題点があっ
た。
In the semiconductor device manufactured by the manufacturing method described above, as shown in FIG. 5, the polysilicon film 16 filled in the trench 11a is thermally oxidized to form a silicon thermal oxide film on the surface. In the case of 16a, the film thickness of the thermal oxide film 16a formed in the portion in contact with the silicon nitride film 14 is smaller than that in the central portion due to insufficient oxygen supply, so the film in this portion is formed. If the thickness is made necessary, the thickness of the central portion becomes unnecessarily thick, the stress of the semiconductor substrate 1 becomes large, and the step between the thermal oxide film 16a and the silicon thermal oxide film 13 becomes large. was there.

【0014】本発明は以上のような状況から、容易に行
うことが可能な工程の変更により、素子を形成する基板
のストレスを減少させ、形成される段差を減少させるこ
とが可能となる半導体装置及びその製造方法の提供を目
的としたものである。
In view of the above situation, the present invention can reduce the stress on the substrate on which the element is formed and the steps formed by changing the process that can be easily performed. And a method for manufacturing the same.

【0015】[0015]

【課題を解決するための手段】本発明の半導体装置は、
素子分離領域としてトレンチを備えた半導体装置であっ
て、半導体基板に形成されているこのトレンチ内に、シ
リコン熱酸化膜, シリコン窒化膜, シリコン酸化膜が順
次積層して形成されており、表面が熱酸化膜にて被覆さ
れたポリシリコン膜が、このトレンチの中心部を充填す
るように構成される。
The semiconductor device of the present invention comprises:
A semiconductor device having a trench as an element isolation region, in which a silicon thermal oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked in a trench formed in a semiconductor substrate, and the surface is A polysilicon film covered with a thermal oxide film is configured to fill the center of this trench.

【0016】本発明の半導体装置の製造方法は、上記の
半導体装置の製造方法であって、底部にチャンネルカッ
トが形成され、この半導体基板に形成されているトレン
チの側壁と底面及びこの半導体基板の表面に延在するシ
リコン熱酸化膜を形成し、このシリコン熱酸化膜の全面
にシリコン窒化膜とシリコン酸化膜とを順次形成する工
程と、このトレンチの中心部及びこのシリコン酸化膜の
表面に延在するポリシリコン膜を形成する工程と、この
ポリシリコン膜を全面エッチングし、前記シリコン酸化
膜の表面を露出させる工程と、このポリシリコン膜の表
面を熱酸化して熱酸化膜を形成する工程と、この半導体
基板の表面のこのシリコン酸化膜及びこのシリコン窒化
膜を除去する工程とを含むように構成する。
A method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device described above, wherein a channel cut is formed in a bottom portion, a sidewall and a bottom surface of a trench formed in the semiconductor substrate, and the semiconductor substrate. A step of forming a silicon thermal oxide film extending on the surface and sequentially forming a silicon nitride film and a silicon oxide film on the entire surface of this silicon thermal oxide film, and a step of forming a silicon nitride film and a silicon oxide film on the center part of this trench and the surface of this silicon oxide film. A step of forming an existing polysilicon film, a step of completely etching the polysilicon film to expose the surface of the silicon oxide film, and a step of thermally oxidizing the surface of the polysilicon film to form a thermal oxide film. And a step of removing the silicon oxide film and the silicon nitride film on the surface of the semiconductor substrate.

【0017】[0017]

【作用】即ち本発明においては、トレンチ内に形成した
シリコン窒化膜の全面にシリコン酸化膜を形成した後、
ポリシリコン膜を充填し、このポリシリコン膜を熱酸化
して熱酸化膜を形成するので、この酸化工程においてト
レンチ1aの境界部の酸化膜が中央部よりも厚くなるの
で、中央部において必要とする膜厚の熱酸化膜を形成す
るだけで良いから、熱酸化膜全体の膜厚を薄くすること
が可能となり、素子を形成する半導体基板のストレスを
減少させ、形成される段差を減少させるようにすること
が可能となる。
That is, in the present invention, after the silicon oxide film is formed on the entire surface of the silicon nitride film formed in the trench,
Since the polysilicon film is filled and the polysilicon film is thermally oxidized to form a thermal oxide film, the oxide film at the boundary portion of the trench 1a becomes thicker than the central portion in this oxidation step. Since it suffices to form a thermal oxide film having a desired thickness, it is possible to reduce the thickness of the entire thermal oxide film, reduce the stress on the semiconductor substrate that forms the element, and reduce the steps formed. It becomes possible to

【0018】[0018]

【実施例】以下図1〜図4 により本発明の一実施例のト
レンチを素子分離領域として用いる半導体装置及びその
製造方法について詳細に説明する。
1 to 4, a semiconductor device using a trench as an element isolation region and a method of manufacturing the same according to an embodiment of the present invention will be described in detail below.

【0019】図1は本発明による一実施例の半導体装置
のトレンチ部を示す側断面図、図2〜図4は本発明によ
る一実施例の半導体装置の製造方法を工程順に示す側断
面図である。
FIG. 1 is a side sectional view showing a trench portion of a semiconductor device according to one embodiment of the present invention, and FIGS. 2 to 4 are side sectional views showing a method of manufacturing a semiconductor device according to one embodiment of the present invention in the order of steps. is there.

【0020】本発明の一実施例のトレンチを素子分離領
域として用いている半導体装置は、図1に示すように半
導体基板1に形成されているトレンチ1a内に、シリコン
熱酸化膜3, シリコン窒化膜4, シリコン酸化膜5が順
次積層して形成されており、表面が熱酸化膜6aにて被覆
されたポリシリコン膜6がこのトレンチ1aの中心部に充
填されている。
A semiconductor device using a trench as an element isolation region according to one embodiment of the present invention has a silicon thermal oxide film 3 and a silicon nitride film in a trench 1a formed in a semiconductor substrate 1 as shown in FIG. A film 4 and a silicon oxide film 5 are sequentially laminated and formed, and a polysilicon film 6 whose surface is covered with a thermal oxide film 6a is filled in the central portion of the trench 1a.

【0021】このような半導体装置の製造方法を図2〜
図4により工程順に詳細に説明する。まず図2(a) に示
すように、半導体基板1の表面にレジストを塗布してレ
ジスト膜2を形成し、マスクを用いるフォトリソグラフ
ィ技術によりこのレジスト膜をパターニングしてトレン
チ1a形成部に開口2aを形成し、ドライエッチング法によ
りこの半導体基板1に幅1.0 μm , 深さ5.0 μm のトレ
ンチ1aを形成した後、レジスト膜2をマスクとして下記
条件のイオン注入法によりイオンを注入してチャンネル
カット1bをトレンチ1aの底部に形成する。
A method of manufacturing such a semiconductor device will be described with reference to FIGS.
Detailed description will be given in order of steps with reference to FIG. First, as shown in FIG. 2A, a resist film 2 is formed by applying a resist on the surface of the semiconductor substrate 1, and the resist film is patterned by a photolithography technique using a mask to form an opening 2a in the trench 1a forming portion. Then, a trench 1a having a width of 1.0 μm and a depth of 5.0 μm is formed in this semiconductor substrate 1 by dry etching, and then ion is implanted by the ion implantation method under the following conditions using the resist film 2 as a mask to form a channel cut 1b. Are formed at the bottom of the trench 1a.

【0022】 イオン種──────ボロン(B+),注入エネルギー─
──────20 keV ドーズ量──────5×1012cm-2 つぎにレジスト膜2を除去し、半導体基板1を1,000 °
Cに加熱して半導体基板1の表面及びトレンチ1aの側壁
と底面に延在するシリコン熱酸化膜を形成すると、図2
(b) に示すようにトレンチ1aの側壁が膜厚 3,000Åのシ
リコン熱酸化膜3になりトレンチ1aの幅は約 7,000Åに
なる。
Ion species ────── Boron (B + ), implantation energy ─
────── 20 keV Dose ────── 5 × 10 12 cm -2 Next, the resist film 2 is removed, and the semiconductor substrate 1 is heated to 1,000 °.
When the silicon thermal oxide film is formed on the surface of the semiconductor substrate 1 and the sidewalls and bottom surface of the trench 1a by heating to C, as shown in FIG.
As shown in (b), the side wall of the trench 1a becomes the silicon thermal oxide film 3 having a film thickness of 3,000Å, and the width of the trench 1a becomes about 7,000Å.

【0023】ついで図3(a) に示すようにこのシリコン
熱酸化膜3の全面に膜厚 500Åのシリコン窒化膜4をC
VD法により形成し、続いてこのシリコン窒化膜4の全
面に膜厚 500Åのシリコン酸化膜5をCVD法により形
成すると、トレンチ1aの幅は約 5,000Åになる。
Then, as shown in FIG. 3 (a), a silicon nitride film 4 having a film thickness of 500 Å is formed on the entire surface of the silicon thermal oxide film 3 by C.
When the silicon oxide film 5 having a film thickness of 500 Å is formed on the entire surface of the silicon nitride film 4 by the CVD method by the VD method, the width of the trench 1a becomes about 5,000 Å.

【0024】更に図3(b) に示すように、半導体基板1
の表面及びトレンチの側壁と底面に延在するこのシリコ
ン窒化膜4の表面に膜厚2μm のポリシリコン膜6をC
VD法により成長させると、トレンチの中心部はポリシ
リコン膜6にて充填される。
Further, as shown in FIG. 3 (b), the semiconductor substrate 1
A polysilicon film 6 having a film thickness of 2 μm is formed on the surface of the silicon nitride film 4 and the surface of the silicon nitride film 4 extending to the side wall and the bottom surface of the trench.
When grown by the VD method, the central part of the trench is filled with the polysilicon film 6.

【0025】ここでこのポリシリコン膜6をドライエッ
チングにより全面エッチングすると図4(a) に示すよう
にトレンチ内にはポリシリコン膜6が残り、半導体基板
1の表面にはシリコン酸化膜5が露出する。
When the entire surface of the polysilicon film 6 is etched by dry etching, the polysilicon film 6 remains in the trench and the silicon oxide film 5 is exposed on the surface of the semiconductor substrate 1 as shown in FIG. 4 (a). To do.

【0026】そして半導体基板1を900〜1,000°Cに加
熱すると、図4(b) に示すようにポリシリコン膜6の表
面が熱酸化されて約4,000Åの熱酸化膜6aが形成され
る。最後にドライエッチングを行うと、表面の膜厚約 5
00Åのシリコン酸化膜5とその下の膜厚約 500Åのシリ
コン窒化膜4が除去され、図1に示すようなトレンチ1a
の境界部の酸化膜厚が厚い熱酸化膜6aを備えた半導体装
置を製造することが可能となる。
When the semiconductor substrate 1 is heated to 900 to 1,000 ° C., the surface of the polysilicon film 6 is thermally oxidized to form a thermal oxide film 6a of about 4,000 liters as shown in FIG. 4 (b). When dry etching is performed at the end, the surface film thickness is about 5
The silicon oxide film 5 of 00 Å and the silicon nitride film 4 under it having a film thickness of about 500 Å are removed, and the trench 1a as shown in FIG. 1 is removed.
It is possible to manufacture a semiconductor device including the thermal oxide film 6a having a thick oxide film at the boundary portion of the.

【0027】上記の実施例では図2(b) の工程において
半導体基板1の表面のシリコン熱酸化膜3とトレンチ1a
内側壁のシリコン熱酸化膜3とを同時に形成している
が、予め半導体基板1の表面にシリコン熱酸化膜を形成
しておき、その後トレンチ1a内のシリコン熱酸化膜3を
形成することも可能である。
In the above embodiment, the silicon thermal oxide film 3 and the trench 1a on the surface of the semiconductor substrate 1 are processed in the step of FIG. 2 (b).
Although the silicon thermal oxide film 3 on the inner wall is formed at the same time, it is also possible to previously form the silicon thermal oxide film on the surface of the semiconductor substrate 1 and then form the silicon thermal oxide film 3 in the trench 1a. Is.

【0028】[0028]

【発明の効果】以上の説明から明らかなように、本発明
によれば極めて簡単な構造の変更により、素子を形成す
る基板のストレスを減少させ、形成される段差を減少さ
せることが可能となる等の利点があり、著しい経済的及
び、信頼性向上の効果が期待できる半導体装置及びその
製造方法の提供が可能である。
As is apparent from the above description, according to the present invention, it is possible to reduce the stress on the substrate on which the element is formed and to reduce the step difference formed by the extremely simple structure change. It is possible to provide a semiconductor device and a method for manufacturing the same, which have advantages such as the above, and can be expected to achieve significant economic and reliability improvement effects.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明による一実施例の半導体装置のトレン
チ部を示す側断面図、
FIG. 1 is a side sectional view showing a trench portion of a semiconductor device according to an embodiment of the present invention,

【図2】 本発明による一実施例の半導体装置の製造方
法を工程順に示す側断面図(1) 、
FIG. 2 is a sectional side view (1) showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps,

【図3】 本発明による一実施例の半導体装置の製造方
法を工程順に示す側断面図(2) 、
FIG. 3 is a side sectional view (2) showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

【図4】 本発明による一実施例の半導体装置の製造方
法を工程順に示す側断面図(3) 、
FIG. 4 is a side sectional view (3) showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

【図5】 従来の半導体装置のトレンチ部を示す側断面
図、
FIG. 5 is a side sectional view showing a trench portion of a conventional semiconductor device,

【図6】 従来の半導体装置の製造方法を工程順に示す
側断面図(1) 、
FIG. 6 is a side sectional view (1) showing a conventional semiconductor device manufacturing method in the order of steps;

【図7】 従来の半導体装置の製造方法を工程順に示す
側断面図(2) 、
FIG. 7 is a side sectional view (2) showing a conventional method of manufacturing a semiconductor device in the order of steps.

【図8】 従来の半導体装置の製造方法を工程順に示す
側断面図(3) 、
FIG. 8 is a sectional side view (3) showing a conventional method of manufacturing a semiconductor device in the order of steps,

【符号の説明】[Explanation of symbols]

1は半導体基板、 1aはトレンチ、 1b
はチャンネルカット、2はレジスト膜、 2aは開
口、 3はシリコン熱酸化膜、4はシリコ
ン窒化膜、 5はシリコン酸化膜、 6はポリシリ
コン膜、6aは熱酸化膜、
1 is a semiconductor substrate, 1a is a trench, 1b
Is a channel cut, 2 is a resist film, 2a is an opening, 3 is a silicon thermal oxide film, 4 is a silicon nitride film, 5 is a silicon oxide film, 6 is a polysilicon film, 6a is a thermal oxide film,

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 素子分離領域としてトレンチ(1a)を備え
た半導体装置であって、 半導体基板(1) に形成されている該トレンチ(1a)内に、
シリコン熱酸化膜(3),シリコン窒化膜(4),シリコン酸化
膜(5) が順次積層して形成されており、表面が熱酸化膜
(6a)にて被覆されたポリシリコン膜(6) が、前記トレン
チ(1a)の中心部を充填するように形成されていることを
特徴とする半導体装置。
1. A semiconductor device having a trench (1a) as an element isolation region, wherein the trench (1a) formed in a semiconductor substrate (1) comprises:
A silicon thermal oxide film (3), a silicon nitride film (4), and a silicon oxide film (5) are sequentially stacked, and the surface is a thermal oxide film.
A semiconductor device characterized in that a polysilicon film (6) covered with (6a) is formed so as to fill the central portion of the trench (1a).
【請求項2】 請求項1記載の半導体装置の製造方法で
あって、 底部にチャンネルカット(1b)が形成され、前記半導体基
板(1) に形成されているトレンチ(1a)の側壁と底面及び
前記半導体基板(1) の表面に延在するシリコン熱酸化膜
(3) を形成し、該シリコン熱酸化膜(3) の全面にシリコ
ン窒化膜(4) とシリコン酸化膜(5) とを順次形成する工
程と、 前記トレンチ(1a)の中心部及び前記シリコン酸化膜(5)
の表面に延在するポリシリコン膜(6) を形成する工程
と、 該ポリシリコン膜(6) を全面エッチングし、前記シリコ
ン酸化膜(5) の表面を露出させる工程と、 前記ポリシリコン膜(6) の表面を熱酸化して熱酸化膜(6
a)を形成する工程と、 前記半導体基板(1) の表面の前記シリコン酸化膜(5) 及
び前記シリコン窒化膜(4) を除去する工程と、 を含むことを特徴とする半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein a channel cut (1b) is formed on a bottom portion, and a sidewall and a bottom surface of a trench (1a) formed on the semiconductor substrate (1), Silicon thermal oxide film extending on the surface of the semiconductor substrate (1)
(3) and then sequentially forming a silicon nitride film (4) and a silicon oxide film (5) on the entire surface of the silicon thermal oxide film (3), the center portion of the trench (1a) and the silicon. Oxide film (5)
A step of forming a polysilicon film (6) extending on the surface of the silicon oxide film, a step of completely etching the polysilicon film (6) to expose the surface of the silicon oxide film (5), and the polysilicon film (6). The surface of (6) is thermally oxidized to form a thermal oxide film (6
a), and a step of removing the silicon oxide film (5) and the silicon nitride film (4) on the surface of the semiconductor substrate (1). ..
JP21700591A 1991-08-28 1991-08-28 Semiconductor device and manufacture thereof Withdrawn JPH0555361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21700591A JPH0555361A (en) 1991-08-28 1991-08-28 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21700591A JPH0555361A (en) 1991-08-28 1991-08-28 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0555361A true JPH0555361A (en) 1993-03-05

Family

ID=16697334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21700591A Withdrawn JPH0555361A (en) 1991-08-28 1991-08-28 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0555361A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335627A (en) * 1995-06-07 1996-12-17 Nittetsu Semiconductor Kk Semiconductor device and manufacture thereof
JPH0964164A (en) * 1995-08-24 1997-03-07 Nittetsu Semiconductor Kk Semiconductor device and its fabrication method
US6274919B1 (en) 1995-06-07 2001-08-14 Nippon Steel Semiconductor Corporation Semiconductor device having a field-shield device isolation structure
US6469345B2 (en) 2000-01-14 2002-10-22 Denso Corporation Semiconductor device and method for manufacturing the same
US6521538B2 (en) 2000-02-28 2003-02-18 Denso Corporation Method of forming a trench with a rounded bottom in a semiconductor device
US6864532B2 (en) 2000-01-14 2005-03-08 Denso Corporation Semiconductor device and method for manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335627A (en) * 1995-06-07 1996-12-17 Nittetsu Semiconductor Kk Semiconductor device and manufacture thereof
US6274919B1 (en) 1995-06-07 2001-08-14 Nippon Steel Semiconductor Corporation Semiconductor device having a field-shield device isolation structure
JPH0964164A (en) * 1995-08-24 1997-03-07 Nittetsu Semiconductor Kk Semiconductor device and its fabrication method
US6469345B2 (en) 2000-01-14 2002-10-22 Denso Corporation Semiconductor device and method for manufacturing the same
US6864532B2 (en) 2000-01-14 2005-03-08 Denso Corporation Semiconductor device and method for manufacturing the same
US7354829B2 (en) 2000-01-14 2008-04-08 Denso Corporation Trench-gate transistor with ono gate dielectric and fabrication process therefor
US6521538B2 (en) 2000-02-28 2003-02-18 Denso Corporation Method of forming a trench with a rounded bottom in a semiconductor device

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