KR0183971B1 - Semiconductor element isolation method - Google Patents
Semiconductor element isolation method Download PDFInfo
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- KR0183971B1 KR0183971B1 KR1019900018350A KR900018350A KR0183971B1 KR 0183971 B1 KR0183971 B1 KR 0183971B1 KR 1019900018350 A KR1019900018350 A KR 1019900018350A KR 900018350 A KR900018350 A KR 900018350A KR 0183971 B1 KR0183971 B1 KR 0183971B1
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- trench
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- polycrystalline silicon
- isolation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- Power Engineering (AREA)
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Abstract
본 발명은 반도체소자 분리방법에 관한 것으로서 실리콘기판에 트렌치를 형성하는 공정과, 상기 트렌치를 포함하는 상기 실리콘기판의 전표면에 산화막을 형성하고 에치 백하여 상기 트렌치의 측면에 산화격리막을 형성하는 공정과, 상기 트렌치내에 다결정실리콘을 채우는 공정과, 상기 트렌치 내의 상기 다결정실리콘을 소자의 활성영역으로 이용할 수 있도록 열처리하여 재결정화하는 공정을 구비한다. 따라서, 소자격리막을 깊고 좁게 형성하므로 소자 분리 영역을 감소하여 소자의 집적도를 향상시킬 수 있다.The present invention relates to a method for separating a semiconductor device, comprising: forming a trench in a silicon substrate; and forming an oxide isolation layer on an entire surface of the silicon substrate including the trench and etching back to form an oxide isolation layer on the side of the trench. And filling the polycrystalline silicon in the trench, and heat treating and recrystallizing the polycrystalline silicon in the trench to serve as an active region of the device. Therefore, since the device isolation layer is formed deep and narrow, the device isolation region can be reduced to improve the degree of integration of the device.
Description
제1a~f도는 종래의 반도체소자 분리방법을 도시하는 공정도.1A to F are process drawings showing a conventional method of separating semiconductor devices.
제2a~i도는 본 발명에 따른 반도체소자 분리방법을 도시하는 공정도.2a to i are process drawings showing a semiconductor device separation method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘웨이퍼 2 : 포토레지스트1: Silicon Wafer 2: Photoresist
3 : 트렌치영역 4 : 산화막3: trench region 4: oxide film
5 : 다결정실리콘 5' : 재결정된 다결정실리콘5: polycrystalline silicon 5 ': recrystallized polycrystalline silicon
6 : 소자6 element
본 발명은 반도체소자 분리방법에 관한 것으로서, 특히, 트렌치의 측면에 소자 분리용 산화막을 형성하고 트렌치 내에 다결정실리콘을 채우고 재결정화시켜 이 영역을 반도체의 소자 형성영역으로 사용하므로써 소자 분리영역의 미세화가 가능하므로 소자의 집적도를 향상시킬 수 있는 반도체소자 분리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for separating semiconductor devices, and in particular, by forming an oxide film for isolation on the side of the trench, filling polycrystalline silicon in the trench, and recrystallizing it, thereby minimizing the device isolation region. Therefore, the present invention relates to a semiconductor device separation method capable of improving the integration degree of the device.
제1도(a)~(f)는 종래 기술에 따른 트렌치(trench)를 이용한 반도체소자의 분리방법을 도시하는 공정도이다.1 (a) to (f) are process diagrams illustrating a method of separating a semiconductor device using a trench according to the prior art.
제1도(a)와 같은 실리콘웨이퍼(1) 상에 제1도(b)와 같이 포토 공정에 의해 트렌치 형성을 위한 마스크(2)를 형성한다. 그리고, 제1도(c)에 도시된 바와 같이 마스크(2)를 이용하여 실리콘웨이퍼(1)의 노출된 부분을 식각하여 트렌치(3)를 형성한다.The mask 2 for forming the trench is formed on the silicon wafer 1 as shown in FIG. 1 by a photo process as shown in FIG. As illustrated in FIG. 1C, the exposed portion of the silicon wafer 1 is etched using the mask 2 to form the trench 3.
그 다음, 제1도(d)와 같이 마스크(2)를 제거하고 트렌치(3) 내부 표면을 포함하는 실리콘웨이퍼(1) 상에 산화막(4)을 형성한다. 그리고, 제1도(e)와 같이 실리콘웨이퍼(1) 상에 트렌치(3)를 채우도록 다결정실리콘(5)을 증착한 후 이 트렌치(3) 내에만 잔류하도록 제거하여 소자 분리를 위한 트렌치 공정은 종료된다. 이때, 실리콘웨이퍼(1) 상의 산화막(4)도 제거한다. 다라서, 제1도(f)와 같이 트렌치(3)가 형성된 영역을 제외한 나머지 영역에 소자(6)가 형성된다.Next, as shown in FIG. 1D, the mask 2 is removed and an oxide film 4 is formed on the silicon wafer 1 including the inner surface of the trench 3. Then, as shown in FIG. 1 (e), the polysilicon 5 is deposited to fill the trench 3 on the silicon wafer 1, and then removed to remain only in the trench 3, thereby removing the trench. Ends. At this time, the oxide film 4 on the silicon wafer 1 is also removed. Therefore, the element 6 is formed in the remaining region except for the region in which the trench 3 is formed as shown in FIG.
그러나, 상술한 종래의 트렌치 방법을 이용한 소자 분리방법은 트렌치영역 내에 매립시키는 다결정실리콘을 빈 공간을 채우기 위한 것으로 소자 형성영역으로 사용할 수 없기 때문에 소자 분리시에 넓은 면적을 잠식하는 단점이 있었다.However, the above-described device isolation method using the trench method fills an empty space of the polysilicon embedded in the trench region, and has a disadvantage of encroaching a large area upon device isolation because it cannot be used as an element formation region.
따라서, 본 발명의 목적은 소자 분리 영역을 감소하여 소자의 집적도를 향상시킬 수 있는 반도체소자의 소자분리방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device that can reduce the device isolation region to improve the degree of integration of the device.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리방법은 실리콘기판에 트렌치를 형성하는 공정과, 상기 트렌치를 포함하는 상기 실리콘기판의 전표면에 산화막을 형성하고 에치 백하여 상기 트렌치의 측면에 산화격리막을 형성하는 공정과, 상기 트렌치 내에 다결정실리콘을 채우는 공정과, 상기 트렌치 내의 상기 다결정실리콘을 소자의 활성영역으로 이용할 수 있도록 열처리하여 재결정화하는 공정을 구비한다.A device isolation method of a semiconductor device according to the present invention for achieving the above object is a step of forming a trench in a silicon substrate, and forming an oxide film on the entire surface of the silicon substrate including the trench and etching back to the side of the trench Forming an oxide isolation layer in the trench, filling polycrystalline silicon in the trench, and heat-treating and recrystallizing the polycrystalline silicon in the trench to serve as an active region of the device.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도(a)~(i)는 본 발명에 따른 반도체소자 분리방법을 도시하는 공정도이다.2 (a) to (i) are process charts showing the semiconductor device isolation method according to the present invention.
제2도(a)와 같은 실리콘기판(1)에 상에 제2도(b)와 같이 포토 공정에 의해 트렌치 형성을 위한 마스크(2)를 형성한다. 그리고, 제2도(c)에 도시된 바와 같이 마스크(2)를 이용하여 실리콘웨이퍼(1)의 노출된 부분을 식각하여 트렌치(3)를 형성한다.On the silicon substrate 1 as shown in FIG. 2A, a mask 2 for forming trenches is formed by a photo process as shown in FIG. 2B. As illustrated in FIG. 2C, the exposed portion of the silicon wafer 1 is etched using the mask 2 to form the trench 3.
그 다음, 제2도(d)와 같이 마스크(2)를 제거하고 트렌치(3) 내부 표면을 포함하는 실리콘웨이퍼(1) 상에 산화막(4)을 증착하여 형성하고, 제2도(e)와 같이 트렌치(3) 바닥면을 포함하는 실리콘웨이퍼(1)의 표면이 노출되도록 산화막(4)을 측면에만 남도록 에치 백한다.Next, the mask 2 is removed as shown in FIG. As described above, the oxide film 4 is etched back so that only the side surface of the silicon wafer 1 including the bottom surface of the trench 3 is exposed.
그리고, 제2도(f)와 같이 실리콘웨이퍼(1) 사에 트렌치(3)를 채우도록 다결정실리콘(5)을 증착한 후, 제2도(g)와 같이 다결정실리콘(5)을 트렌치(3) 내에만 잔류하도록 에치 백한다.After depositing the polysilicon 5 to fill the trench 3 in the silicon wafer 1 as shown in FIG. 2 (f), the polysilicon 5 is formed in the trench (as shown in FIG. 2g). 3) Etch back so that it remains only inside.
그 다음, 제2도(h)와 같이 트렌치(3) 내의 다결정실리콘(5)을 열처리하여 재결정화된 다결정실리콘(5')을 형성한다.Next, as shown in FIG. 2H, the polycrystalline silicon 5 in the trench 3 is heat-treated to form recrystallized polysilicon 5 '.
제2도(i)와 같이 실리콘웨이퍼(1)의 트렌치(3)가 형성되지 않은 부분 뿐만 아니라 트렌치(3) 내늬 재결정화된 다결정실리콘(5')은 소자(6)가 형성되는 액티브영역이 되며, 이 액티브영역 사이의 산화막(4)은 소자를 격리하는 소자격리막이 된다.As shown in FIG. 2 (i), not only the portion where the trench 3 of the silicon wafer 1 is not formed, but also the recrystallized polysilicon 5 'formed in the trench 3 includes an active region in which the element 6 is formed. The oxide film 4 between the active regions becomes an element isolation film that isolates the element.
따라서, 본 발명은 소자격리막을 깊고 좁게 형성하므로 소자분리영역을 감소하여 소자의 집적도를 향상시킬 수 있는 효과가 있다.Therefore, since the device isolation layer is formed deep and narrow, the device isolation region can be reduced to improve the degree of integration of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900018350A KR0183971B1 (en) | 1990-11-13 | 1990-11-13 | Semiconductor element isolation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900018350A KR0183971B1 (en) | 1990-11-13 | 1990-11-13 | Semiconductor element isolation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920010832A KR920010832A (en) | 1992-06-27 |
| KR0183971B1 true KR0183971B1 (en) | 1999-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900018350A KR0183971B1 (en) | 1990-11-13 | 1990-11-13 | Semiconductor element isolation method |
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| KR (1) | KR0183971B1 (en) |
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- 1990-11-13 KR KR1019900018350A patent/KR0183971B1/en not_active IP Right Cessation
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| KR920010832A (en) | 1992-06-27 |
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