JPS5950540A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To attain high integration without generating the difference of conversion by a method wherein a groove serving as an element isolation region is provided in a substrate, a chemical vapor deposition film is formed therein and flatted by heat treatment, and the deposition film is left only in above-mentioned groove by etching. CONSTITUTION:A thermal oxide film 31 is formed on an Si substrate 30, and photo resists 32 and 33 are so patterned that the element isolation region 34 is bored. Next, etching is performed, with oxide films 36 and 37 as the mask, by removing the film 31, resulting in the formation of the groove 38. Then, a channel stopping layer 40 is formed by ion implantation, and the chemical vapor deposition film 41 is formed. Channel stopping layers 42, 43 and 44 are formed by heat treatment. An oxide film 50 is formed by removing the films 36, 37 and 41. A phosphorus glass film 52 is deposited and made to flow, resulting in flatness, and a resin material 58 is spin-coated thereon. It is flatted by etching down to the substrate 30.

Description

DETAILED DESCRIPTION OF THE INVENTION In the present invention, after forming a trench to serve as an isolation region in a silicon substrate, a channel top layer is formed on the side and bottom surfaces of the trench, and densification is applied to the trench.
The present invention relates to a method of manufacturing a semiconductor device in which isolation characteristics are improved and planarization is achieved by leaving a chemical vapor deposition film containing ionized phosphorus.

Conventionally, in semiconductor integrated circuits, the so-called LOCO8 method (Local Oxidat
ipnof5ilicon (selective oxidation) was the main method. However, in this LOCO8 method, due to the lateral diffusion of the birthbeak and the channel stop layer, a conversion difference between -G and (Sin formed in the silicon substrate when silicon is oxidized and converted to -C8iO2, and the surface For example, the difference in thickness of 5in2 formed on the top is large, etc.
High integration was difficult and rare.

Figure 1 shows the conventional LOCO8 method. Next, as shown in FIG. 1(a), a nitride film 3 and an oxide film 2 are formed on the silicon substrate 1 in a portion that will become an active region.

Thereafter, as shown in FIG. 1(b), the silicon substrate 1 is
Conductive type channel stop layers 4 and 5 are formed.

Furthermore, as shown in FIG. 1C, by performing oxidation treatment using the nitride film 3 as a mask, an isolated head formed of thick field oxide films 6 and 7 can be obtained.

At this time, as shown by symbols 8 and 9, υ
, the edge of the nitride film 3 is pushed up, a biting region of the field oxide film is generated, and the channel stop layer 4.5 is also diffused in the lateral direction due to the heat treatment during the oxidation process. Next, as shown in FIG. 1(d), the nitride film 3 is removed to obtain active regions 4 and 5 having a width of 21.

According to the above LOCO8 method, as shown in Figure 1,
A large conversion difference occurs in the width of the ultimately obtained active region due to the digging of the oxide film, making it difficult to miniaturize it.In addition, the narrow channel effect due to the lateral diffusion of the Nayant stop layers 4 and 5 also occurs. However, the density was still 4fJL.

This invention was made in order to eliminate the drawbacks of the LOCO8 method mentioned above, and the conversion difference hardly occurs, daytime integration is achieved, and normalization can be done in January. Another object of the present invention is to provide a method for manufacturing a semiconductor device (7) that produces less distortion and provides good isolation characteristics.

Embodiments of the semiconductor device manufacturing method of the present invention will be described below with reference to the drawings. Figure 2(a) to Figure 2(
j) is a diagram showing the i-ho manufacturing process of one embodiment.

First, as shown in FIG. 2(a), silico y J, i
& 3() to form a thin thermal oxide [31]. after that,
The element isolation region 34 is formed using known photolithography technology.
The photoresists 32 and 33 are turned so that the holes are opened.

Next, the thermal oxide film 31 is etched and removed using the photoresist 32,33+c mask as shown in FIG.
As shown in ), the silicon substrate 30 is etched using a reactive in/etch method using an oxidized mask. Form fIf38.

Next, as shown in FIG. 2(c), a channel stop layer 4 is formed on the silicon substrate 30 by an ion implantation method.
is formed at the bottom of the groove 38.

After that, as shown in Figure 2 (Yu), by chemical vapor vapor method,
A chemical vapor film 41 doped with the same impurity as that which forms the conductivity of this silicon substrate 30 is formed.

Next, a heat treatment is performed to form channel stop layers 42, 43, and 44 on the side walls and bottom of the trench 38 in the silicon substrate 30 by an in-phase diffusion method.

After that, the oxide films 36 and 37 and the chemical vapor deposition film 41 are removed by etching the entire surface to form a structure as shown in Figure 2(e).
do .

Furthermore, as shown in FIG. 2(f), the silicon substrate 30 is oxidized to form a thin oxide film 50.

Next, as shown in FIG. 2(g), a phosphorus glass film (SiO,/P, O,) 52 is deposited by chemical vapor deposition. At this time, the phosphor glass film 5 is placed in the center of the groove 38.
2 four parts 53 are formed.

Further, by utilizing the fact that the phosphorus glass film 52 contains phosphorus as an impurity, flow is caused in the high temperature surrounding atmosphere. At the same time, the phosphorus glass film 52 becomes an insulating film with excellent heat treatment, simplification, and R density, and is also expected to have a gettering effect on ionic impurities due to the inclusion of phosphorus. be done.

Also, due to this flow, the phosphor glass film 52 is flattened, and as shown in FIG. 2(h), a resin-based material 58 is spin-coated on the phosphor glass film 52, and as shown in FIG. 2(i). The surface is completely flattened.

Thereafter, the entire surface of the resin material 58 and the saw/glass film 52 is etched up to the upper surface of the silicon substrate 3o using an etching material that has uniform etching characteristics. A planarized element isolation structure is formed so that it is exposed.

The first embodiment described above has the advantages listed in -F.

(1) Since a selective oxidation method such as the LOCO8 method is not used, NJ+t can be achieved for elements with a small conversion difference, making it possible to integrate high strength internally when manufacturing semiconductor devices.

(2) Since the in-phase diffusion of a chemical vapor deposition film containing impurities that can form a channel stop layer is used, the channel stop layer can be formed on the sidewalls of the trench in the silicon substrate, improving isolation characteristics. .

(3) The method of filling the grooves 38 of the silicon substrate 30 utilizes the flow of the phosphor glass film 52 formed by chemical vapor deposition, so a film with excellent passivation effect and good density is filled. The element isolation characteristics are greatly improved.

(4) Since planarization is performed using a constant-speed etching method of a tung resin material and a phosphorus glass film, the element isolation region and the active region surface are almost on the same plane, and the degree of integration is greatly improved.

In addition, in the first embodiment, after depositing a chemical vapor deposition film containing impurities to serve as a channel stop layer, in-phase diffusion was performed, and then the chemical vapor deposition was completely removed.
By forming a chemical vapor deposition film, successively depositing a phosphorus glass film and performing high-temperature heat treatment, the same effect can be achieved even when the in-phase diffusion for forming a channel stop layer is performed at the same time. That's what you get.

As described above, the semiconductor of the present invention 46) Id (1)
! According to the 1 manufacturing method, a trench is formed in a silicon substrate to serve as an element isolation region, a channel stop layer is formed on the sides and bottom of this trench, and then a chemical vapor deposition film containing phosphorus is formed. Since the chemical vapor deposition film is left only in the grooves of the silicon substrate on the flattened substrate, not only is it possible to achieve capacitance with almost no conversion difference, but also to reduce the occurrence of distortion. The separation characteristics are small and good separation characteristics can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) each show a conventional half-two
Figure 2 is a diagram explaining the manufacturing method of the J-6 body device (
a) to FIG. 2(j) respectively show semiconductors of the present invention;
4. , 6z is a diagram for explaining an embodiment of the manufacturing method. 30...Silicon substrate, 38...r/ri, 40.4
2 to 44... Channel stop layer, 50... Oxide film, 52... Phosphorus glass film. Figure 1 Figure 2 4°4

Claims (1)

[Claims] A first step of forming a trench to serve as an element isolation region in the +IJ silicon substrate, a second step of forming a channel stop layer on the bottom and side surfaces of the trench of the silicon substrate, and a second step of forming a channel stop layer on the bottom and side surfaces of the trench of the silicon substrate; After forming the stop layer, a third step of forming a chemical vapor deposition film containing phosphorus on the silicon substrate and flattening it by heat treatment, and further flattening the chemical vapor deposition film. Therefore, the method for manufacturing a semiconductor device is different from the fourth step in which the chemical vapor deposition film is left only in the groove of the silicon substrate. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the second step of forming the channel stop layer is by depositing a chemical vapor deposition film and in-phase diffusion.