JP2883242B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art FIG. 3 is a schematic sectional view showing a procedure of a conventional manufacturing method. First, an isolation oxide film 12 is formed on a silicon substrate 10 in a self-aligned manner to expose silicon on an active region, and polysilicon 13 is deposited on the exposed silicon substrate 10 and the isolation oxide film 12. Then P ⁺
Ions are implanted into the entire surface (FIG. 3A). Next, after the NSG 14 is deposited on the polysilicon 13, the NSG 14 and the polysilicon 13 on the internal base region 15 are removed by a photolithography process. Thereafter, an external base region 16 which is a P ⁺ diffusion layer is formed by performing a heat treatment (FIG. 3B).

[0003] Then, P ^- by implanting ions into the entire surface, the internal base over source region 15 is formed [FIG. 3
(C)]. Next, a sidewall 17 is formed on the internal base region 15 by a known method (FIG. 3D).

[0004] and, deposited on the entire surface of polysilicon, ⁷⁵
After N ⁺ ions such as As ⁺ are implanted, an emitter polysilicon 18 for forming an emitter region 19 is formed by a photo-etching step. Thereafter, the emitter region 19 is formed by thermal diffusion [FIG. 3 (e)].

As described above, conventionally, when a bipolar transistor is manufactured by base-emitter self-alignment, the outer base region is formed by thermal diffusion from silicon, and the inner base region is formed. This has been done by directly implanting N ⁺ ions into polysilicon.

[0006]

By the way, in the above-mentioned conventional method, ion implantation is required in each step to form the inner base region and the outer base region. However, there is a problem that the depth of diffusion becomes deep due to direct ion implantation into silicon, and it is not possible to increase the speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a structure of an emitter-base self-alignment and a shallow bipolar transistor by forming an internal base region and an emitter region shallow. It is an object of the present invention to provide a method for manufacturing a semiconductor device which realizes a high speed operation.

[0008]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises an internal base region and an external base around the active region in a predetermined active region of a substrate surface layer. In a method of manufacturing a semiconductor device having a structure in which a source region is formed, an isolation oxide film is formed in a self-aligned manner on a substrate, silicon on the active region is exposed, and then polysilicon is deposited on the entire surface of the substrate. Then, the polysilicon surface is oxidized, and then the polysilicon excluding the region where the internal base region is to be formed is removed from the substrate surface by the total of the isolation oxide film and the polysilicon on the isolation oxide film. After removal so that the thickness is smaller than the total thickness of the polysilicon on the region where the internal base region is to be formed and the oxide film on the polysilicon surface, ion implantation and annealing are sequentially performed. Thereby, an outer base region and an inner base region having a predetermined concentration and depth are formed, and thereafter, an insulating film for planarization is deposited on the entire surface, and the insulating film is formed on the inner base region. After etching back until the upper polysilicon is exposed, a trench is formed by removing the polysilicon on the internal base region, and then, after forming a sidewall on the sidewall in the trench, It is characterized by forming an emitter region in the inner base region.

[0009]

The internal base and the external base of the self-aligned structure are formed by performing ion implantation in a state where the polysilicon is selectively thickly left on the region where the internal base region is to be formed. Is done. The internal base is formed by shallow diffusion from polysilicon.

[0010]

1 and 2 show the procedure of an embodiment of the present invention. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, an isolation oxide film is formed on the silicon substrate 1 in a self-aligned manner by a known technique to expose silicon on the active region. Here, an oxide film separation is taken as an example, but another method such as a trench separation may be used. Thereafter, polysilicon 3 is deposited on exposed silicon substrate 1 and isolation oxide film 2. Thereafter, an oxide film 4 is formed by oxidizing the surface of the polysilicon 3. The thickness of the oxide film 4 is appropriately determined according to the P ⁺ ion implantation conditions in a later step (FIG. 1A).

Next, the oxide film 4 and the polysilicon 3 excluding the internal base region 8 are etched away by a photolithography process so that the polysilicon 3 remains at a predetermined thickness. At this time, the thickness A of the polysilicon 3 on the internal base region is higher than the sum B of the thickness of the isolation oxide film 2 from the silicon substrate surface and the thickness of the remaining polysilicon 3. The thickness of the isolation oxide film 2, the thickness of the polysilicon 3 and the remaining thickness after etching are adjusted as described above [FIG.
(B)].

Next, P ⁺ ions such as ¹¹ B ⁺ are implanted,
Annealing is performed. In this step, the difference in the thickness of the polysilicon between the outer base region 9 and the inner base region 8, that is, the thickness of the polysilicon 3 on the outer base region 9 This is performed by utilizing the fact that the thickness is smaller than the film thickness of the polysilicon 3 of FIG. on the other hand,
The internal base region 8 is formed by diffusion from the polysilicon 3.
The implantation condition and the annealing condition are adjusted so as to form the internal base region 8 of the shallow base diffusion layer as necessary. The concentration and depth of the internal base region 8 can also be controlled by adjusting the thickness of the oxide film 4 on the surface of the polysilicon 3 (FIG. 1C).

Next, an insulating film 5 such as SOG, which is excellent in flattening, is deposited on the entire surface, and then etched back until the polysilicon 3 on the internal base region 8 is exposed [FIG.
(A)].

After that, the polysilicon 3 on the internal base region 8 is removed by etching under a condition that the selectivity with the insulating film 5 is sufficient [FIG. 2 (b)]. Next, after depositing an insulating film such as HTO, the side wall 6 is formed by etching back. Thereafter, it deposited on the entire surface of polysilicon, ⁷⁵ A
After the implantation of N ⁺ ions such as s ^+, the emitter polysilicon 7 for forming the emitter region 81 is deposited in a photo-etching step. Thereafter, an emitter region 81 is formed by thermal diffusion from the emitter polysilicon 7 (FIG. 2C).

[0016]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the polysilicon is selectively and thickly left on the region where the internal base region is to be formed.
By performing a single ion implantation, an external base region having a concentration sufficient for obtaining a sufficient ohmic contact is formed.
On the other hand, the internal base region is configured to form a shallow base / emitter region by thermal diffusion from polysilicon, so that the speed of the obtained semiconductor device can be increased and a device having excellent characteristics can be realized. In addition, since a self-aligned structure can be formed by one ion implantation process, the process can be simplified and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a process of an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view illustrating a process of an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view illustrating a process of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Separation oxide film 3, 7 ... Polysilicon 4 ... Oxide film 5 ... Insulation film 6 ... Side wall 8 ... Inside Base region 81 Emitter region 9 External base region

Claims (1)

(57) [Claims] In a method for manufacturing a semiconductor device having a structure in which an internal base region and an external base region around the internal base region are formed in a predetermined active region of a substrate surface layer, a self-aligned structure is formed on the substrate. An isolation oxide film is formed to expose silicon on the active region. Thereafter, polysilicon is deposited on the entire surface of the substrate, and then the polysilicon surface is oxidized. Thereafter, the internal base region is formed. The total thickness of the isolation oxide film and the polysilicon on the isolation oxide film from the substrate surface, except for the region above the polysilicon, is the polysilicon on the region where the internal base region is to be formed and the polysilicon surface. After removing the oxide film to a thickness smaller than the total thickness, ion implantation and annealing are sequentially performed to form an outer base region and an inner base region having a predetermined concentration and depth. After that, an insulating film for planarization is deposited on the entire surface, and the insulating film is etched back until polysilicon on the internal base region is exposed,
Forming a groove by removing polysilicon on the internal base region, forming a sidewall on a side wall in the groove, and then forming an emitter region in the internal base region; A method for manufacturing a semiconductor device.