JP3316411B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device in which variations in hFE are suppressed.

[0002]

2. Description of the Related Art As a technique for obtaining an extremely fine base-emitter junction, for example, a method described in JP-A-7-235547 is known. First, this method will be described. An N-type semiconductor layer 11 serving as a collector is formed on a P-type semiconductor substrate by an epitaxial growth method, and the surface of the semiconductor layer 11 is selectively oxidized to form a LOCOS oxide film 12 for element isolation. Form. Reference numeral 13 denotes an N + type buried layer. Further, a P + type isolation region for isolating the N type epitaxial layer from the PN junction is formed below the LOCOS oxide film 12.

Subsequently, a CVD oxide film is deposited on the entire surface, and the semiconductor layer 11 to be subjected to emitter diffusion by photoetching.
The insulating film 15 is left on the surface. (Refer to FIG. 6 above.) Subsequently, on the surface of the semiconductor layer 11 not covered with the insulating film 15, a polysilicon layer is formed by a selective epitaxial growth method to form a first silicon layer 16, and thereafter, boron is ion-implanted. As a result, an impurity for external base diffusion is doped into the first silicon layer 16. L on the whole surface
A second silicon layer 17 is formed by depositing a silicon layer by the PCVD method. (See FIG. 7 above.) Subsequently, boron for imparting conductivity to the second silicon layer 17 is ion-implanted, and the second silicon layer 17 is photo-etched to form the first and second silicon layers 16 and 17. To form a base lead electrode 18. At the same time, an opening is formed on the insulating film 15 to expose the head of the insulating film 15. (Refer to FIG. 8 above.) Subsequently, as shown in FIG.
Is formed, and the surface of the semiconductor layer 11 is exposed. Thereafter, the whole is thermally oxidized to form a thermal oxide film 20 on the surface of the semiconductor layer 11 and the surfaces of the first and second silicon layers 16 and 17. At the same time, boron is diffused from the first silicon layer 16 to form an external base region 21, and boron for forming an active base is ion-implanted without a mask. (Refer to FIG. 10 above.) Subsequently, a polysilicon layer is deposited on the entire surface, and is dry-etched anisotropically to form a sidewall 22 on the side wall of the opening 19, and the entire surface is HTO (High).
(Temperature oxide) 23 is formed. Further, the HTO 23 is etched back to open the opening 19.
The surface of the semiconductor layer 11 is exposed again. (See FIG. 11 above.) Finally, a polysilicon layer is deposited by the CVD method, an impurity for emitter diffusion is doped, and this is photoetched to form an emitter lead-out electrode 24 in the opening 19. Then, by thermally treating the entire substrate, the previously implanted ions are diffused to form the active base region 25, and at the same time, the emitter region 26 is formed by solid-phase diffusion from the emitter extraction electrode 24. (See FIG. 12 above.) Further, an insulating film is deposited on the entire surface, an emitter contact and a base contact are formed, and an emitter electrode and a base electrode are formed through a contact hole.

A fine high-frequency transistor can be manufactured by the above manufacturing method. In FIGS. 7 to 9, the first silicon layer 16 made of polysilicon and the base lead electrode 18 are integrally formed of polysilicon.
FIG. 13 shows a semiconductor integrated circuit device formed using the above-described steps. In this semiconductor integrated circuit device, after the step of forming an emitter lead-out electrode 24 (FIG. 12), an insulating film 27 is deposited on the entire surface in the same manner as in the above-described conventional example, and an emitter contact 28, a base contact 29, and a collector contact 32, an emitter electrode 30, a base electrode 31, and a collector electrode 33 are formed.

[0005]

However, FIG.
As shown in FIG. 12, the extraction electrode 24 on the emitter region 26 is etched to form a recess 34, and the impurity is hardly diffused by the removal of the diffusion source.
A problem that the diffusion depth of the metal is different. This problem occurs in the conventional example described up to FIG. 12 and the conventional example in FIG. 13, and will be described here with reference to FIG.

That is, this is due to the difference in the thickness of the insulating film extending in the region where the emitter contact 28, the base contact 29 and the collector contact 32 are formed. That is, the emitter contact 28 is covered with the insulating film 27, but the base contact 29 is provided with the HTO film in addition to the insulating film 27, and the collector contact 3
In the portion 2, the thermal oxide film 20 is placed in addition to the insulating film 27. Therefore, the emitter contact 28 having a small thickness is used.
Is opened first, so that when the collector contact 32 and the base contact 29 are completely opened,
The emitter extraction electrode 24 is etched, and the recess 3
4 are formed.

Therefore, when the recess 34 is formed on a part of the emitter region 26, the impurity of the emitter is removed by this etching, so that the emitter diffusion region 26 is formed.
However, there is a problem that the desired hFE cannot be obtained or varies.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. When the extraction electrode of the region is extended and an emitter contact is formed around this opening, the insulating film located at the base contact is thick, and the extraction electrode of the emitter is etched until the contact hole is completely opened. Since the contact (concave portion) is formed shifted, it can be formed without causing a difference in the diffusion depth of the emitter region.

Further, even if the insulating film located at the collector contact is thick and the extraction electrode of the emitter is etched before the contact hole is completely opened, the emitter contact (concave portion) is formed so as to be shifted. It can be formed without a difference in diffusion depth.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIGS. First, the structure will be briefly described with reference to FIG. The LOCOS oxide film 52 includes a collector contact region 55 and a base region (an active base region 61).
And the external base region 59). The external base region 59 is formed by diffusing impurities of the extraction electrode 57 made of a silicon material. An insulating film 56 is provided around the extraction electrode 57 to expose the active base region 61. A sidewall 62 is formed on a side surface of the opening exposing the active base region 61.
Is an opening through which impurities of the emitter pass. The sidewall 62 is an injection hole for ion-implanting the impurity of the emitter. In the case of diffusion by a solid diffusion source, the sidewall 62 serves as a mask in etching for forming an introduction hole.

Insulating films 56 and 66 are formed in a portion located at base contact hole 65 ', and a thermal oxide film 58 and an insulating film 66 are formed in a portion located at collector contact hole 67. In addition, an insulating film 66 is formed in a portion of the emitter region located at the contact hole 68 of the extraction electrode 64. The feature of the present invention is that the contact hole 68 of the emitter electrode 71 is not placed directly above the opening surrounded by the sidewall 62, and the periphery of the opening, for example, L
It is to be placed on the OCOS oxide film 52.

That is, by shifting the contact hole 68,
Since the concave portion of the extraction electrode 64 is not formed directly above the emitter region, impurities can be sufficiently secured by the extraction electrode 64, and the formation of the concave portion can be suppressed. Hereinafter, the manufacturing method will be described with reference to the drawings. First, reference is made to FIG. An N-type semiconductor layer 51 serving as a collector is formed on a P-type semiconductor substrate 50 by an epitaxial growth method, and the surface of the semiconductor layer 51 is selectively oxidized to form a LOCOS oxide film 52 for element isolation. Where LO
The COS oxide film 52 can be replaced with a thick insulating film. 53 is an N + type buried layer. Also,
A trench 54 for electrically isolating the N-type epitaxial layer is formed below the LOCOS oxide film 52.
A P + type isolation region may be formed.

The LOCOS oxide film 52 surrounds a region where a transistor is to be formed, and has a collector contact region 5.
The semiconductor layer 51 which will be 5 and the base regions 59 and 61 to be planned is exposed. Also, a-Si is formed on the entire surface to a thickness of about 2000 ° by CVD, and BF 2 is ion-implanted. An impurity may be previously added to the a-Si forming gas (a gas composed of H2 and silicon, for example, silane), or the impurity may be deposited. Here, this a-
In order to use Si as a diffusion source and to use it as an extraction electrode, ion implantation that can accurately control resistance value control and concentration control of an external base is preferable.

What is important here is that a-Si is deposited by lowering the film forming temperature by using LPCVD or plasma CVD with a gas composed of H 2 and silicon instead of depositing polysilicon at the time of deposition. To wear. At the stage of the final process, this film may be a-Si as it is, or may be a film subjected to heat treatment. (See FIG. 2 above.) Subsequently, an insulating film 56 is formed on the entire surface. This insulating film 56
Is a silicon oxide film formed by CVD and is about 2000
Å. After that, both films are etched, and the extraction electrode 57 is extended on a portion corresponding to the planned external base region 59 and on the LOCOS oxide film 52 adjacent to this region. Further, the extended a-Si is utilized as an electrode 57 taken out from an external base and a diffusion source by introducing impurities later. At the time of this etching, the surface of the semiconductor layer corresponding to the predetermined active base region is lightly etched.

Here, since the a-Si film and the film obtained by heat-treating a-Si are formed, the surface of the extraction electrode 57 and the predetermined active base region are formed on a gentle surface. If the film 52 is made of polysilicon, the surface of the extraction electrode 57 becomes uneven due to differences in grain boundary and grain etching speed. Further, the film corresponding to the active base region 61 is etched. As the etching approaches the semiconductor surface, the grain boundary disappears but the grain remains. As a result, the semiconductor layer located around the grain is etched first,
The exposed surface of the semiconductor layer 51 has an uneven surface. This increases the shape and contact resistance in the following diffusion region forming process.

However, since an a-Si film or a film obtained by heat-treating a-Si is used, this unevenness is suppressed. Subsequently, the entire surface is thermally oxidized, and 10 Å is deposited on the a-Si surface and the semiconductor layer 51 surface.
A thermal oxide film 58 of about 0 to 200 ° is formed. At this point, the impurities in the a-Si are slightly diffused, and the external base region 59 is slightly formed. Further, using a resist 60 as a mask for ion implantation, BF2 as a base impurity is ion-implanted through the thermal oxide film 58. As a result, an active base region 61 is formed in a later heat treatment step. (Refer to FIG. 3 above.) As described above, the unevenness is suppressed on the surface of the planned active base region 61, so that the diffusion speed here is substantially uniform on all surfaces.

Subsequently, in consideration of insulation between a predetermined extraction electrode 64 of the emitter electrode and a base extraction electrode 57, the entire surface is HTO (High temperature ox).
ide) is deposited by LPCVD or plasma CVD, and sidewalls 62 are formed on sidewalls corresponding to the predetermined active base region. This sidewall 62 is also aS
i is formed by etching back a-Si formed on the entire surface by anisotropic etching.

Here, the impurity of the emitter may be ion-implanted through the side wall. However, since solid diffusion (diffusion using the extraction electrode 64) is used here, the thermal oxide film 58 on the surface of the active base region 61 is used. Is removed by wet etching. In this step, as described above, since the sidewall 62 is composed of the a-Si film and the film obtained by heat-treating the a-Si, the sidewall 62 can be formed on the sidewall having a gentle surface. Here, in the former ion implantation, ions are implanted using the sidewalls as a mask. In the latter solid-state diffusion, the insulating film 58 is etched to form an impurity introduction hole. In any case, these introduction holes are affected by the shape of the side wall 62, but in the present invention, since they are gentle, unevenness can be suppressed. Therefore, variations in the emitter area, diffusion depth, and the like are suppressed.

Subsequently, after a silicon film made of polysilicon or a-Si is applied, a predetermined extraction electrode 64 of the emitter electrode 71 is formed by etching via a resist 63. Here, as shown in FIG. 4, after the silicon film is deposited, the extraction electrode 64 of the emitter electrode, which also serves as a diffusion source, takes into account the resistance value of the emitter electrode and the impurity concentration of the emitter region. As is ion-implanted on the entire surface. In addition, a predetermined emitter contact hole 68 is shifted from a position immediately above an opening formed by the sidewall 62 and is disposed around the opening. Here, the extraction electrode 64 extends over the LOCOS oxide film 52.

Subsequently, in order to form a contact 65 for the extraction electrode 57 of the base electrode, a part of the insulating film 56 is etched, and further, an insulating film 66 is formed on the entire surface.
This insulating film 66 may be a silicon oxide film, a silicon glass film, or a silicon nitride film. Further, the contact 6
Etching is performed to form 5 ', collector contact 67 and contact 68 for the emitter electrode. Thereafter, using a mask 69 for ion implantation, BF2 is ion-implanted into the exposed contact holes 65. This is performed to reduce the contact resistance between the base electrode and the extraction electrode 57. Here, the insulating film 66 and the insulating film 56 may be etched at once without forming the contact hole 65 in advance. The insulating films 56 and 66 located in the base contact hole 65 'are formed thicker than the other contact portions by the overlap. However, if the collector contact 67 is LOC
When exposed through the OS oxide film, the collector contact 67 has a thicker insulating film. In any case, by the time the collector contact 67 and the base contacts 65 and 65 'are completely opened, the extraction electrode 64 corresponding to the emitter contact 68 is etched to form a recess. However, the contact hole 68 is formed around the emitter region (opening surrounded by the side wall), here LOC.
Since it is formed on the OS oxide film, the impurities in the emitter region can be sufficiently secured, and the uneven emitter region as shown in FIG. 14 can be suppressed.

Subsequently, the resist 69 is removed, and the entire substrate is heat-treated. As a result, the previously implanted ions are diffused to form the active base region 59, and at the same time, the emitter region E is formed by solid-phase diffusion from the emitter extraction electrode 64. The diffusion depth of the emitter region E is about 0.5 μ, and the emitter region E is formed further outside by the sidewall 62.

Thereafter, a base electrode 70, an emitter electrode 71 and a collector electrode 72 are formed through light etching of the contact hole. Thus, a microfabricated high-frequency transistor can be manufactured. As described above, in the embodiment of the present invention, the extraction electrode 57 of the base electrode and the side wall 62 are formed of the a-Si film or the film obtained by heat-treating the a-Si. However, if only the removal of the emitter contact from the emitter region is considered. If so, at least one may be made of polysilicon.

[0023]

As described above, the extraction electrode of the emitter region, which serves as a diffusion source, extends to the periphery (preferably above the LOCOS oxide film) of the opening formed by the sidewall exposing the emitter region. If an emitter contact is formed around the opening, the insulating film located at the base contact is thick, and the extraction electrode of the emitter is etched until the base contact hole is completely opened. However, since the emitter contact is formed shifted from immediately above the emitter region, the emitter contact can be formed without causing a difference in the diffusion depth of the emitter region.

The insulating film located at the collector contact is thicker than the insulating film located at the base contact. Even if the extraction electrode of the emitter is etched before the collector contact hole is completely opened, the emitter contact is located directly above the emitter region. Therefore, the emitter region can be formed without causing a difference in the diffusion depth of the emitter region.

Accordingly, since the emitter region can be formed without causing a difference in the diffusion depth, the transistor characteristics such as hFE can be realized with the initial values, and the variation can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor integrated circuit device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 6 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 7 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 8 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 9 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 10 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 11 is a cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 12 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 13 is a cross-sectional view illustrating a conventional semiconductor integrated circuit device.

FIG. 14 is a schematic diagram illustrating the shape of the emitter region of FIG.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-120237 (JP, A) JP-A-10-256267 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/732 H01L 21/331

Claims (2)

(57) [Claims] A base region exposed by a first insulating film on a semiconductor layer; an active base region which forms the base region and is formed at the center thereof; and an external base region which surrounds the active base region. An emitter region formed in the active base region; an extraction electrode of the external base region extending on the first insulating film exposing the active base region; and an extraction electrode of the external base region Cover the surface,
A second insulating film exposing the emitter region; and an amorphous silicon provided on a side surface of the second insulating film.
The emitter region.
An exposed opening , contacting the emitter region through the opening,
An extraction electrode of the emitter region serving as a diffusion source extending to the periphery of the opening, and a third insulating material coated on the extraction electrode of the emitter
A film, a base contact that exposes an extraction electrode of the external base region, and the emitter that is separated from the sidewall of the opening.
Emitter contact exposing the extraction electrode in the data area
And a base electrode and an emitter electrode provided on the base contact and the emitter contact, respectively. 2. A base region and a collector contact region exposed by a first insulating film on a semiconductor layer; a thin insulating film covering the collector contact region; and an active layer formed at the center of the base region. An external base region surrounding the base region and the active base region; and an external base region extending over the first insulating film.
Covering the extraction electrode and the extraction electrode surface of the external base region;
A second insulating film exposing the emitter region; and an amorphous silicon provided on a side surface of the second insulating film.
The emitter region.
An exposed opening , contacting the emitter region through the opening,
An extraction electrode of the emitter region serving as a diffusion source extending to the periphery of the opening, a third insulation film coated on the extraction electrode of the emitter and the thin insulation film, and exposing the collector contact region Separated from the collector contact and the sidewall of the opening.
Emitter contact exposing the extraction electrode in the data area
And a collector electrode and an emitter electrode provided on the collector contact and the emitter contact, respectively.