JP3342339B2 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which variations in hFE are suppressed and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a technique for obtaining an extremely fine base-emitter junction, for example, a method described in JP-A-7-235547 is known. First, this method will be described. An N-type semiconductor layer 11 serving as a collector is formed on a P-type semiconductor substrate by an epitaxial growth method, and the surface of the semiconductor layer 11 is selectively oxidized to form a LOCOS oxide film 12 for element isolation. Form. Reference numeral 13 denotes an N + type buried layer. Further, a P + type isolation region for isolating the N type epitaxial layer from the PN junction is formed below the LOCOS oxide film 12.

Subsequently, a CVD oxide film is deposited on the entire surface, and the semiconductor layer 11 to be subjected to emitter diffusion by photoetching.
The insulating film 15 is left on the surface. (Refer to FIG. 6 above.) Subsequently, on the surface of the semiconductor layer 11 not covered with the insulating film 15, a polysilicon layer is formed by a selective epitaxial growth method to form a first silicon layer 16, and thereafter, boron is ion-implanted. As a result, an impurity for external base diffusion is doped into the first silicon layer 16. L on the whole surface
A second silicon layer 17 is formed by depositing a silicon layer by the PCVD method. (See FIG. 7 above.) Subsequently, boron for imparting conductivity to the second silicon layer 17 is ion-implanted, and the second silicon layer 17 is photo-etched to form the first and second silicon layers 16 and 17. To form a base lead electrode 18. At the same time, an opening is formed on the insulating film 15 to expose the head of the insulating film 15. (Refer to FIG. 8 above.) Subsequently, as shown in FIG.
Is formed, and the surface of the semiconductor layer 11 is exposed. Thereafter, the whole is thermally oxidized to form a thermal oxide film 20 on the surface of the semiconductor layer 11 and the surfaces of the first and second silicon layers 16 and 17. At the same time, boron is diffused from the first silicon layer 16 to form an external base region 21, and boron for forming an active base is ion-implanted without a mask. (Refer to FIG. 10 above.) Subsequently, a polysilicon layer is deposited on the entire surface, and is dry-etched anisotropically to form a sidewall 22 on the side wall of the opening 19, and the entire surface is HTO (High).
(Temperature oxide) 23 is formed. Further, the HTO 23 is etched back to open the opening 19.
The surface of the semiconductor layer 11 is exposed again. (See FIG. 11 above.) Finally, a polysilicon layer is deposited by the CVD method, an impurity for emitter diffusion is doped, and this is photoetched to form an emitter lead-out electrode 24 in the opening 19. Then, by thermally treating the entire substrate, the previously implanted ions are diffused to form the active base region 25, and at the same time, the emitter region 26 is formed by solid-phase diffusion from the emitter extraction electrode 24. (Refer to FIG. 12 above.) A fine high-frequency transistor can be manufactured by the above manufacturing method.

[0004]

However, in the steps shown in FIGS. 8 to 9, the insulating film 15 is a CVD oxide film, and the first silicon layer 16 is a polysilicon film. Here, only the insulating film 15 is removed.
The polysilicon 16 is also removed from the dry etching material. In addition, polysilicon is a collection of grains and grain boundaries, and the grain boundary has a higher etching rate.
The surface of is uneven.

As a result, the side surface of the first silicon layer 16 extending vertically from the semiconductor layer 11 also becomes uneven. In addition, since the boundary line L between the semiconductor layer 11 and the silicon film 16 shown in FIG. 9 naturally becomes uneven, the external base region diffused by the impurities of the first silicon film 16, particularly the external base region 2
The boundary between 1 and the semiconductor layer 11 becomes uneven as shown by the line M in FIG.

Further, even if a thermal oxide film 20 is formed as shown in FIG. 10, since the surface of the polysilicon is uneven, the active base region is formed by ion implantation.
Is formed unevenly like the line N of FIG. Since the unevenness has no reproducibility, the active base region and the external base have different areas.

When the first silicon layer 16 and the insulating film 15 are formed of a polysilicon film and the active base region is opened as shown in FIG. 9, the exposed surface of the semiconductor layer 11 is also reduced due to the difference in etching rate described above. Line O shown in FIG.
Are formed unevenly. In other words, in the state where the polysilicon film on the active base region being etched remains thin in the semiconductor layer, the portion with the grain boundary is
Since the etching speed is high, the semiconductor layer reaches the semiconductor layer quickly and is etched toward the semiconductor layer. Therefore, irregularities are formed on the surface of the semiconductor layer. Since this portion finally becomes a contact portion of the extraction electrode 24, the contact resistance increases.

In addition, the unevenness of the surface of the semiconductor layer exposes various crystal faces. For example, the surface is [1,0,
[0] plane, but the [1,1,1] plane appears on the uneven surface.
In this [1,1,1] plane, since the diffusion speed is high, the shape of the active base region becomes uneven, which affects the transistor characteristics. Further, there is a problem with the sidewall 22 as well. In the process of FIG.
2 is made of polysilicon. Since the grain boundary has a higher etching rate, the sidewall 2
The surface of No. 2 has irregularities from which polysilicon has protruded.
Further, an HTO film is formed on the surface of the side wall 22. Since the HTO film is generated in accordance with the unevenness of the side wall 22, the HTO film also has an uneven surface. Also, the introduction hole of the emitter impurity forms irregularities.

Therefore, as shown in FIG.
The boundary P between the layer 5 and the emitter region 26 and the surface of the emitter region become uneven. For this reason, the diffusion depth of the emitter region is uneven as shown by the line P, and there is no reproducibility. Therefore, there is a problem that the characteristics (hFE) of the transistor vary.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and firstly, in an opening surrounded by a sidewall on the side surface of an insulating layer which is substantially located at a portion where an external base and an active base region overlap. The problem is solved by using the opening as an introduction hole for the emitter region and forming the sidewall with amorphous silicon or a film obtained by heat-treating amorphous silicon.

A film formed by heat-treating amorphous silicon (hereinafter referred to as a-Si) or a-Si can form a smooth surface even when etched without distinction between grains and grain boundaries. Even if an impurity is ion-implanted, the shape of the emitter does not become uneven. Second, since the exposed portion of the insulating film between the sidewall and the surface of the semiconductor layer is self-aligned with the sidewall, the shape of the emitter is uneven even if impurities are introduced through the exposed portion. It does not become.

Third, in order to suppress variations in hFE of the transistor, a sidewall made of polysilicon is made of amorphous silicon (hereinafter referred to as a-Si) or a-Si.
The problem is solved by replacing the film with a heat-treated film after attaching -Si and introducing impurities through the sidewall. As a fourth means, in addition to the third means, an a-Si film or an a-Si film is first applied instead of a diffusion source made of polysilicon, and then a heat-treated film is used as a diffusion source. is there.

As described above, since the former a-Si has no grains and no grain boundary, it is possible to realize a surface in which unevenness is suppressed even by etching. As will be described in detail later, a film with a-Si applied thereto and then heat-treated can also realize a surface with suppressed irregularities. Therefore, the uneven diffusion region and the uneven semiconductor surface shown in FIG. 13 can be suppressed.

Further, as shown in FIG. 17, the heat-treated a-Si film can have a small sheet resistance.
By leaving the diffusion source made of the -Si film as the extraction electrode of the base region, a low extraction resistance can be realized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIGS. First, the structure will be briefly described. The LOCOS oxide film is formed in the collector contact region 5
5 and the base region (consisting of the active base region 61 and the external base region 59). The external base region 59 is provided with the extraction electrode 5 made of a silicon material.
7 is formed by diffusing the impurities. An insulating film is provided around the extraction electrode 57 to expose the active base region 61. A side wall 62 is formed on the side surface of the opening exposing the active base region 61, and the opening formed by the side wall 62 serves as a passage for impurities of the emitter. This sidewall 62
Is an injection hole for ion-implanting the impurity of the emitter. In the case of diffusion by a solid diffusion source, it serves as a mask in etching for forming an introduction hole.

The present invention focuses on the fact that the shape of the side wall 62 determines the shape of the emitter region 65 '. That is, a-
The side wall 62 is made of a Si film or a film obtained by heat-treating a-Si.
With this configuration, the surface shape of the sidewall 62 can be made smooth, and as a result, the shape of the emitter region 65 'is made smooth, and variation in hFE is suppressed.

Hereinafter, the manufacturing method will be described with reference to the drawings. First, reference is made to FIG. P-type semiconductor substrate 50
To be a collector by epitaxial growth on
A semiconductor layer 51 of a mold type is formed, and the surface of the semiconductor layer 51 is selectively oxidized to form a LOCOS oxide film 52 for element isolation. Here, the LOCOS oxide film can be replaced with a thick insulating film. 53 is an N + type buried layer. Although a trench 54 for electrically isolating the N-type epitaxial layer is formed below the LOCOS oxide film 52, a P + -type isolation region may be formed.

This LOCOS oxide film 52 surrounds a region where a predetermined transistor is to be formed, and has a collector contact region 5.
The semiconductor layer 51 which will be 5 and the base regions 59 and 61 to be planned is exposed. Also, a-Si is formed on the entire surface to a thickness of about 2000 ° by CVD, and BF 2 is ion-implanted. An impurity may be previously added to the a-Si forming gas (a gas composed of H2 and silicon, for example, silane), or the impurity may be deposited. Here, this a-
In order to use Si as a diffusion source and to use it as an extraction electrode, ion implantation that can accurately control resistance value control and concentration control of an external base is preferable. What is important here is that a-Si is deposited by lowering the film forming temperature by using LPCVD or plasma CVD with a gas composed of H2 and silicon instead of depositing polysilicon at the time of deposition. It is in. At the stage of the final process, this film is a-
Si may be used as it is, or a film subjected to heat treatment may be used. This will be described in detail later. (See FIG. 2 above.) Subsequently, an insulating film 56 is formed on the entire surface. This insulating film 56
Is about 2000 ° for a silicon oxide film. After that, the two films 52 and 56 are etched to form a predetermined external base region 59.
And on the LOCOS oxide film 52 adjacent to this region and this region. The extended a-Si is
Extraction electrode 5 from external base by later impurity introduction
7 and used as a diffusion source. At the time of this etching, the surface of the semiconductor layer corresponding to the predetermined active base region is lightly etched.

This step is a feature of the present invention.
Since it is composed of an a-Si film and a film obtained by heat-treating a-Si,
The extraction electrode 57 and the intended active base region surface
Formed on a gentle surface. If the film 52 is made of polysilicon, the surface of the extraction electrode 57 becomes uneven due to differences in grain boundary and grain etching speed. Further, the film corresponding to the active base region 61 is etched. As the etching approaches the semiconductor surface, the grain boundary disappears but the grain remains. As a result, the semiconductor layer located around the grain is etched first, and the exposed surface of the semiconductor layer 51 becomes an uneven surface. This increases the shape and contact resistance in the following diffusion region forming process.

However, in the present invention, since an a-Si film or a film obtained by heat-treating a-Si is used, this unevenness is suppressed.
Subsequently, the entire surface is thermally oxidized to form a thermal oxide film 58 of about 100 to 200 ° on the a-Si surface and the surface of the semiconductor layer 51.
At this point, the impurities in the a-Si are slightly diffused, and the external base region 59 is slightly formed. Further, using a resist 60 as a mask for ion implantation, BF2 as a base impurity is ion-implanted through the thermal oxide film 58. As a result, an active base region 61 is formed in a later heat treatment step. (Refer to FIG. 3 above.) As described above, the unevenness is suppressed on the surface of the planned active base region 61, so that the diffusion speed here is substantially uniform on all surfaces.

Subsequently, in consideration of insulation between the predetermined emitter electrode extraction electrode 64 and the base extraction electrode 57, the entire surface is HTO (High temperature oxi).
de) is deposited, and a sidewall 62 is formed on the side wall corresponding to the intended active base region. The side wall 62 is also made of a-Si, and the a-
Si is formed by being etched back by anisotropic etching.

Here, the impurity of the emitter may be ion-implanted through the side wall. However, since solid diffusion (diffusion using the extraction electrode 64) is used here, the thermal oxide film 58 on the surface of the active base region 61 is used. Is removed by wet etching. This step is a feature of the present invention. As described above, since the sidewall 62 is composed of the a-Si film and the film obtained by heat-treating the a-Si, it can be formed on a gentle surface. Here, in the former ion implantation, ions are implanted using the sidewalls as a mask. In the latter solid-state diffusion, the insulating film 58 is etched to form an impurity introduction hole. In any case, these introduction holes are affected by the shape of the side wall 62, but in the present invention, since they are gentle, unevenness as shown in FIG. 13 can be suppressed.
Therefore, variations in the emitter area, diffusion depth, and the like are suppressed.

Subsequently, a silicon film made of polysilicon or a-Si is deposited to form a predetermined extraction electrode of the emitter electrode 71. In addition, As is ion-implanted on the entire surface in consideration of the resistance value of the emitter electrode and the impurity concentration of the emitter region, and etched through the resist 63. Subsequently, in order to form the contact 65 of the extraction electrode 57, the insulating film 56 is partially etched, and further the insulating film 66 is formed on the entire surface. This insulating film 66 may be a silicon oxide film, a silicon glass film, or a silicon nitride film.
Further, etching is performed to form the contact 65, the collector contact 67, and the contact 68 for the emitter electrode. Thereafter, a mask 69 for ion implantation is used.
Then, BF2 is ion-implanted into the exposed contact holes 65. This is performed to reduce the contact resistance with the extraction electrode 57. (Refer to FIG. 5 above.) Subsequently, the resist 69 is removed, and the entire substrate is heat-treated. As a result, the previously implanted ions are diffused to form the active base region 59, and at the same time, the emitter region 65 'is formed by solid phase diffusion from the emitter extraction electrode 64. The diffusion depth of the emitter region 65 'is about 0.5μ,
The emitter region 65 'is formed further outside by the sidewall 62.

Thereafter, a base electrode 70, an emitter electrode 71 and a collector electrode 72 are formed through light etching of the contact hole. Thus, a microfabricated high-frequency transistor can be manufactured. As described above, in the embodiment of the present invention, the extraction electrode 57 of the base electrode and the side wall 62 are formed of the a-Si film or the film obtained by heat-treating the a-Si. The extraction electrode 57 may be made of polysilicon.

Now, why the a-Si film is deposited first,
The reason will be described below. Unlike the polysilicon film, the a-Si film has no grain or grain boundary, and thus has a feature that the etched surface becomes gentle. As shown in FIG. 13, when the polysilicon is etched, the grain boundary has a higher etching speed, so that the surface becomes uneven, and the surface and interface corresponding to the emitter region and the active base region are eventually made uneven. , A-Si have a smooth shape after etching, and thus can eliminate this unevenness.

This phenomenon can be applied to a film to which a-Si is applied first and then heat-treated. The results of the experiment will be described below with reference to FIGS. FIGS. 14 to 16 show the conversion state of the film. The left side shows the conventional method, which is directly grown from polysilicon, and the right side shows amorphous silicon (hereinafter a).
−Si) to after the heat treatment.

The experimental flow at this time is as follows. A: A silicon oxide film of about 1000 ° is grown on a silicon substrate. B: 540 degree, 580 degree, 6 mounted on LPCVD equipment
At 100 degrees and 620 degrees, 100% silane gas (S
iH4). The film thickness at this time is 2
000, 3000, and 4000.

In the experiment, LPCVD was used, but plasma CV
D is fine. C: BF2 is ion-implanted over the entire surface. 60 eV, 3 × 1
015 D: Anneal for 1 hour in a nitrogen atmosphere at 900 ° C. E: Measurement of sheet resistance RS. FIG. 14 shows the steps up to B, FIG. 15 shows the state after the step C, FIG. 16 shows the state after the step D, and FIG. 17 (sheet resistance Rs) and FIG. (Variation in sheet resistance). 17 and FIG.
The horizontal axis of 8 indicates the film forming temperature in the step B.

Looking at the measurement results, the lower the film formation temperature is,
It was found that the sheet resistance was low and the variation was small.
Further, it was also found that at the time of film formation in the step B, amorphous silicon was formed at about 520 to 580 degrees (hereinafter referred to as a low temperature region). Further, a region exceeding 590 degrees to 610 degrees (hereinafter referred to as a high-temperature region) has a greatly changed surface state and is made of polysilicon. About 580
It is considered that a region between about degrees and 600 degrees (hereinafter referred to as an intermediate region) is a transition region between polysilicon and amorphous silicon.

The surface condition of the silicon film is as follows in a low temperature region.
As seen from the electron microscope (magnification: 50,000), as shown on the right side of FIG. 14, unevenness on the surface is hardly observed, and a-Si 81 is formed. On the other hand, in the high temperature region, as shown in the left side of FIG.
Of the polysilicon film 83 can be observed. Also grain 82
A grain boundary 84 exists between them.

Next, in the ion implantation in the step C, boron fluoride (BF 2 +) 85 is ion-implanted as indicated by the mark X, and the impurity dispersion state of the right a-Si film and the left polysilicon film is Are considered to be substantially the same. Here, if boron is ion-implanted, it penetrates the a-Si film or the polysilicon film. Therefore, boron fluoride having a large size to enter near the surface is employed. In addition, As ion,
Like boron fluoride, it can be adopted because it does not enter deeply.

Further, the annealing step in the step D is about 800 to 1000 degrees, preferably about 900 degrees.
The result here was a different phenomenon than expected. In the polysilicon film 83 on the left side of FIG. 16, the grains grow slightly larger due to the heat treatment, but the grains were observed with an electron microscope (magnification of 50,000 times). However, a-Si on the right side of FIG. 16 is an electron microscope (magnification of 50,000 times).
Observed at, it was not possible to determine whether there was any grain. Since the heat treatment has been applied, it is difficult to imagine that the polysilicon film remains as a-Si. That is, the polysilicon film is generated in the order of two digits or one digit, and the part that is substantially observed is a single crystal. It can be determined that the film is from a large grain film. Also, no grain boundary can be observed. In the former case, it is considered that the grain boundary is very small and small ones are finely dispersed. It can be determined that there is no substantial grain boundary.

In general, the film after annealing is 5 ° C in a high temperature region.
Grains of about 00 ° exist and the surface is rough, but the surface is much flatter in the low temperature region than in the high temperature region. Therefore, when the polysilicon film in the high temperature region is etched, the grain boundary has a higher etching speed, and the surface is uneven when observed with an electron microscope. Further, the surface of the a-Si film in the low temperature region is almost flat. If this is a very fine polycrystalline state, it will be substantially flat even if the grains are selectively etched, and if one or two of the large grains is a resistor, the grain boundary will be polysilicon. This is considered to be due to the fact that it is almost non-existent, so that even when etched, it is possible to form a flat, well-shaped and beautiful pattern.

The feature of the present invention is that the plasma CVD or LPC
A gas (e.g., silane gas) containing H2 and silicon flows in a wafer provided in the VD apparatus in a low temperature region, and a-
The purpose is to form a Si film and heat-treat it to utilize it as a sidewall, and to diffuse impurities and use this film as an extraction electrode and a diffusion source for the external base region 59.

As described above, this film has a small variation in sheet resistance and is a flat film whose surface state cannot be substantially distinguished from a-Si. High-precision etching without defects. Therefore, since the etching can be performed with a gentle surface, it is suitable as a sidewall. In addition, since the sheet resistance variation is small and the surface is smooth and can be etched accurately, it can be used as an extraction electrode for the base electrode, and the uneven semiconductor surface as shown in FIG. 13 and the uneven diffusion surface are significantly reduced. Can be done.

Accordingly, the variation in the diffusion depth of the emitter region can be suppressed, and the unevenness of the interface between the emitter region and the active base region can be suppressed, so that the variation in hFE of the transistor can be suppressed. Also, the area of the external base region,
The variation in the area of the active base region is reduced, and the surface of the active base region is flattened, so that the contact resistance between the extraction electrode of the emitter electrode and the emitter region can be reduced. Further, the film obtained by heat-treating a-Si, that is, the film in FIG. 16 can lower the sheet resistance as compared with polysilicon, and can lower the resistance of the extraction electrode.

[0037]

As described above, in the opening surrounded by the sidewall on the side surface of the insulating layer substantially located at the overlapping portion of the external base and the active base region, this opening is used as the introduction hole of the emitter region. By forming the sidewalls with amorphous silicon or a film obtained by heat-treating amorphous silicon, variations in the diffusion depth of the emitter region can be suppressed. Further, unevenness at the interface between the active base region and the emitter region can be suppressed. Therefore, variation in transistor characteristics, particularly variation in hFE, can be suppressed.

Second, the exposed portion of the insulating film between the side wall and the semiconductor layer surface is self-aligned with the side wall, so that the exposed portion does not become uneven, and impurities are removed from the exposed electrode of the emitter through the exposed portion. Even if it is introduced through, the shape of the emitter does not become a conventional uneven structure. Therefore, variation in transistor characteristics can be suppressed as described above.

Third, when amorphous silicon or amorphous silicon is first applied instead of the polysilicon diffusion source, and then a film that has been heat-treated is used as a diffusion source,
Even if the etching is performed, it is possible to realize a surface having no unevenness and a suppressed unevenness. Therefore, variations in the planar area, diffusion depth, and the like of the emitter region can be suppressed. In addition, variations in the planar area of the external base and the active base region, and the contact resistance between the active base region and the emitter extraction electrode can be reduced.

Fourth, the heat-treated a-Si film can reduce the sheet resistance of the silicon film as shown in FIG. 17 and has a small extraction resistance even if the diffusion source remains as the extraction electrode in the base region. Things can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor integrated circuit of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 6 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 7 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 8 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 9 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 10 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 11 is a cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 12 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 13 is a diagram illustrating a problem of a conventional example.

FIG. 14 is a diagram illustrating a state where a-Si of the present invention and a conventional poly-Si film are attached.

FIG. 15 is a diagram illustrating a state when ions are implanted into the two types of films in FIG. 14;

16 is a diagram illustrating a state when the two types of films in FIG. 15 are annealed.

FIG. 17 is a view for explaining the sheet resistance of the present invention and the conventional silicon film.

FIG. 18 is a diagram illustrating a variation in sheet resistance in FIG. 17;

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-22431 (JP, A) JP-A-63-254768 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 29/732

Claims (4)

(57) [Claims] 1. A base region exposed by an insulating film on a semiconductor layer, an active base region constituting the base region and formed at the center thereof, and a base region constituting the base region and surrounding the active base region. An external base region, an emitter region formed in the active base region, and an inner base region located substantially inside an overlapping portion of the external base region and the active base region, and formed on a side wall of an extraction electrode of the external base region. A semiconductor integrated circuit having an opening formed by a sidewall provided on a side surface of the insulating layer and an emitter extraction electrode formed in the opening, wherein the opening serves as an impurity introduction hole for the emitter region, Removal of sidewalls and the external base area
The extraction electrode has a film formation temperature of 520 to 580 degrees during film formation.
Amorphous silicon film deposited at a temperature of 5 degrees
Polycrystalline silicon deposited at a deposition temperature of 80 to 600 degrees
And a film that is a transition region of amorphous silicon . 2. The semiconductor integrated circuit according to claim 1, wherein the insulating layer between the sidewall and the surface of the semiconductor layer is self-aligned with the sidewall to expose the emitter region. Forming a first insulating film on the semiconductor layer so that a predetermined base region in the collector region is exposed; and a first silicon film doped with an impurity on the exposed semiconductor layer. And forming a second layer on the first silicon film.
Forming said insulating film and removing said first silicon film and said second insulating film such that an active base region that is to form a predetermined base region is exposed; Forming a third insulating film on the semiconductor layer surface corresponding to the base region and on the side wall of the first silicon film; and forming the third insulating film on the semiconductor layer surface corresponding to the exposed active base region. And forming a sidewall on the side surface of the first silicon film on the side of the planned active base region, and formed on the surface of the planned emitter region via the side wall. the third insulating film is etched, forming an impurity introduction hole, said forming a second silicon film to which an impurity in the impurity introducing hole of the emitter region of the appointment has been introduced Second silicon
Heat-treating the film to form the emitter region by thermal diffusion;
The sidewall is formed at 520 to 580 degrees at the time of film formation.
Amorphous silicon film or
Deposited at a film formation temperature of 580 degrees to 600 degrees during film formation and polycrystalline
A film that is the transition region between silicon and amorphous silicon
And the side wall is adjacent to the emitter region.
A method for manufacturing a semiconductor integrated circuit, comprising performing directional diffusion . 4. The method according to claim 1, wherein said first silicon film is 520 at the time of film formation.
Amorphous silicon deposited at a deposition temperature of
Deposition temperature of 580 to 600 degrees at the time of film formation or film formation
Transition between polycrystalline silicon and amorphous silicon
4. The method for manufacturing a semiconductor integrated circuit according to claim 3, wherein the film is a region .