JP2812298B2 - Manufacturing method of bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to a method for manufacturing a bipolar transistor including a simple self-alignment method for a base region and an emitter region.

[0002]

2. Description of the Related Art Generally, in order to improve the operation speed of a bipolar transistor, the resistance (Rb) of a base region must be reduced. In a normal bipolar transistor, the resistance of the intrinsic base region is reduced by adopting a graft base structure, reducing the resistance of the bulk base region, and reducing the width of the emitter region.

FIGS. 5 (a) to 5 (c) to 6 (d),
5E is a sectional view showing a step of a manufacturing step of a conventional self-alignment type bipolar transistor described in Japanese Patent Application Laid-Open No. 1-108772. n-type silicon substrate 20
1 to selectively introduce impurities into the channel stopper 20.
4. After forming the collector lead portion 213, the n-type epitaxial layer 202 is grown. Next, an element isolation oxide film 203 is formed on the substrate surface, and the photoresist film 2 is formed.
Boron ions are implanted using 20 as a mask to form a base region 208 (FIG. 5A). Next, a silicon nitride film 207 and a silicon oxide film 205 are grown on the substrate,
The masking layer is formed by etching away the silicon nitride film 207 and the silicon oxide film 205 in the remaining region except for the region where the emitter and collector lead portions are formed [FIG. 5B].

After forming the graft base region 206 by ion implantation using this masking layer, the side surfaces of the silicon nitride film 207 are etched with hot phosphoric acid or the like to form the emitter region (FIG. 5C). . Then, after removing the silicon oxide film 205 for masking, oxidation is performed using the silicon nitride film 207 as a mask to form a silicon oxide film 212 with a predetermined film thickness (FIG. 6D). Then, the silicon nitride film 207 is removed,
After forming an n ⁺ -type polycrystalline silicon layer 209 over the entire surface of the substrate and forming an emitter region 210 by heat treatment, the polycrystalline silicon layer 209 is patterned to obtain a bipolar transistor having a structure shown in FIG.

[0005]

In the above-described conventional manufacturing method, the size of the emitter region depends on the amount of side etching of the silicon nitride film and the size of bird's beak generated during thermal oxidation using the silicon nitride film as a mask. However, since it is difficult to control these with high accuracy, the emitter region greatly varies within the wafer surface and between lots, and the characteristics become unstable.

In the prior art, oxidation is performed using a silicon nitride film as a mask to define an emitter region. However, the graft base is eroded by the oxide film and becomes thinner, and at the same time, boron is deposited on the oxide film side. To segregate,
The resistance value of the graft base increases, and the resistance value greatly varies within the wafer surface and between lots. Therefore, a problem to be solved by the present invention is to firstly make it possible to accurately form an emitter region in a method of manufacturing a bipolar transistor formed by a self-alignment method. The reason is that it can be formed without variation and with low resistance.

[0007]

SUMMARY OF THE INVENTION The above object is achieved by providing a silicon substrate having a collector region,
Forming a graft base region selectively, forming a silicon oxide film having an emitter opening thereon, compensating for impurities in the graft base region or out-diffusion thereof through the emitter opening to form the graft base region; Forming a base region, forming a polycrystalline silicon film having a high impurity concentration on the emitter opening, and forming an emitter region by heat treatment.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of manufacturing a bipolar transistor according to the present invention comprises the steps of (1) forming an n-type epitaxial layer on an n-type silicon substrate, and (2) selecting an n-type epitaxial layer within a surface region of the n-type epitaxial layer. Forming a high impurity concentration p-type diffusion layer by selectively introducing a p-type impurity; (3)
Forming a silicon oxide film on the substrate, and selectively removing the silicon oxide film by etching to form an emitter opening on the high impurity concentration p-type diffusion layer; and (4) forming the emitter opening through the emitter opening. Forming a low impurity concentration p-type region in the high impurity concentration p-type diffusion layer by compensating or out-diffusing the p-type impurity in the high impurity concentration p-type diffusion layer;
(5) forming a polycrystalline silicon layer containing an n-type impurity on the emitter opening and performing a heat treatment to form an n-type diffusion layer in a surface region of the low impurity concentration p-type region. In. Then, in the above-mentioned (4) step, by performing a treatment with hot phosphoric acid,
Alternatively, a high impurity concentration p is obtained by ion-implanting an impurity of the opposite conductivity type or by performing thermal oxidation.
A low impurity concentration p-type region can be formed in the type diffusion layer.

According to the above-described manufacturing method of the present invention, a base region is formed by treating silicon with hot phosphoric acid using an emitter opening formed in a silicon oxide film provided on a graft base region. Since the emitter region is formed using the emitter opening used to form the base region, a margin between the base region and the emitter region is not required, and the emitter region can be formed with high accuracy. it can. In addition, since the region of the graft base body is not narrowed or the impurity concentration is not reduced, the base resistance can be kept low. Therefore, according to the present invention, it is possible to provide a bipolar transistor having good characteristics and small variations in characteristics.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 1 (a) to 1 (c) to 2 (d)
FIGS. 4A to 4F are cross-sectional views in the order of steps for explaining the first embodiment of the present invention. First, as shown in FIG.
Impurities are introduced for forming a channel stopper 104 and a collector buried layer (not shown) on an n-type silicon substrate 101 using a single crystal silicon wafer having a resistivity of 20 to 40 Ωcm having a (100) plane as a main surface. Thereafter, an n-type epitaxial layer 102 is grown to a thickness of 30,000.degree., An element isolation oxide film 103 having a thickness of 10,000.degree. Is formed by a selective oxidation method, and a silicon oxide film 105 is formed on the entire surface.

Next, as shown in FIG. 1B, a photoresist film 120 is formed on the silicon oxide film 105, and a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ ions is applied to the mask.
The graft base region 106 is formed by ion-implanting a p-type impurity (for example, boron) at / cm ² . Then, FIG.
As shown in (c), a silicon nitride film is grown to a thickness of 6000 to 8000 ° by a CVD method, a photoresist film 121 is formed thereon, and using this as a mask, a dry etch method and a wet etch method are used. The silicon nitride film 107 and the silicon oxide film 105 are selectively removed by etching to form an emitter opening.

When the photoresist film 121 is stripped and removed and then treated with hot phosphoric acid, a high-resistance base region 108 is formed on the surface of the graft base region 106 exposed at the emitter opening. Although the mechanism of the formation of the base region has not been elucidated yet, it is assumed that a phenomenon in which boron in the graft base region is sucked out due to attack by hot phosphoric acid has occurred. Expressing the result of this processing as a ρ _s value, a part of the 300 Ω / □ graft base region 106 has been converted to a 1500 Ω / □ base region 108. During this hot phosphoric acid treatment, the silicon nitride film 1
07 is isotropically etched, and its side wall recedes from the emitter opening [FIG. 2 (d)].

Next, as shown in FIG.
Polycrystalline silicon is deposited by VD (low pressure CVD)
The film is grown to a thickness of from 00 to 2000, with appropriate energy and a dose of 1 to 3 × 10 ¹⁶ ions / cm ^2.
Arsenic ions are implanted to the extent that n ⁺ -type polycrystalline silicon layer 1
After forming 09, annealing is performed in a nitrogen atmosphere at 900 ° C. to 1000 ° C. Thereby, arsenic ions in n ⁺ -type polycrystalline silicon layer 109 diffuse into base region 108 to form emitter region 110.

Next, as shown in FIG. 2F, the n ⁺ -type polycrystalline silicon layer 109 is patterned by photolithography and dry etching so as to remain only in the emitter opening. At this time, since the side wall of the silicon nitride film is etched, the emitter electrode formation portion is formed flat, and the subsequent metal process is facilitated. Further, the base contact portion 111 is formed using a photolithography method, a dry etching method, and a wet etching method. As described above, the production method of the present invention is a combination of easy steps, and enables production with high productivity. Since the size of the emitter region is directly determined by the emitter aperture, it can be formed accurately and without variation. Further, since the base resistance can be kept low, a transistor with an excellent operation speed can be provided.

[Second Embodiment] FIGS. 3A and 3B show
FIG. 9 is a sectional view in the order of steps for explaining a second embodiment of the present invention. In FIG. 3, parts that are the same as the parts shown in FIGS. 1 and 2 are given the same reference numerals. As in the first embodiment, a silicon oxide film 105 is formed on the substrate.
After the silicon nitride film 107 is grown, an emitter opening is formed by using a photolithography method, a dry etching method, and a wet etching method. Thereafter, when the silicon oxide film 112 is formed at the emitter opening by the thermal oxidation method, boron in the graft base region 106 segregates to the oxide film side, so that the p ⁻ -type base region 108 is formed in the graft base region. [FIG. 3 (a)].

Next, a silicon nitride film is grown by the CVD method and etched back to form a nitride film sidewall at the emitter opening. Subsequently, polycrystalline silicon is grown, arsenic ions are implanted to form an n ⁺ -type polycrystalline silicon layer 109, and then heat treatment is performed to form an emitter region 110 in the base region. After that, the polycrystalline silicon layer 109 is patterned,
The silicon nitride film 107 and the silicon oxide film 105 are selectively removed to form a base contact portion 111 [FIG.
(B)].

[Third Embodiment] FIGS. 4 (a) to 4 (c)
It is sectional drawing of a process order for demonstrating the 3rd Example of this invention. As shown in FIG. 4A, as in the first embodiment, after forming ap ⁺ -type graft base region 106 in the surface region of the n-type epitaxial layer 102, a silicon oxide film 105 is formed on the substrate. Grown, photoresist film 12
Etching is performed using this as a mask to form an emitter opening in the silicon oxide film 105. Thereafter, phosphorus is ion-implanted using the silicon oxide film 105 as a mask to form p.
^- -type base region 108. At this time, in this embodiment, since the graft base region 106 is formed shallow, the base region 108 is formed over the entire thickness of the graft base region 106 (FIG. 4B).

Next, the silicon nitride film 10 is formed by CVD.
7 is grown and etched back to form a sidewall of the silicon nitride film 107 in the emitter opening.
Subsequently, after growing polycrystalline silicon and performing arsenic ion implantation to form an n ⁺ -type polycrystalline silicon layer 109,
By performing heat treatment, the emitter region 11 is formed in the base region 108.
0 is formed. Thereafter, the polycrystalline silicon layer 109 is patterned, and the silicon nitride film 107 and the silicon oxide film 105 are selectively removed to form the base contact portion 11.
1 [FIG. 4 (c)].

[0019]

As described above, according to the present invention,
Since the emitter region is formed so as to be aligned with the emitter opening or the side wall formed in the emitter opening, the accuracy of the emitter region is improved, and the shape thereof does not vary within a plane and between lots, and is therefore stable. A transistor having the following characteristics can be obtained. Further, since the graft base region is not eroded by the oxide film or its impurities are not segregated to the oxide film side, the base resistance can be reduced and a transistor which can operate at high speed can be provided. .

[Brief description of the drawings]

FIG. 1 is a part of a process order sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a first embodiment of the present invention;
Sectional sectional view in a step following the step.

FIG. 3 is a sectional view illustrating a second embodiment of the present invention in order of process.

FIG. 4 is a process order sectional view for explaining a third embodiment of the present invention.

FIG. 5 is a part of a process order sectional view for explaining a conventional example.

FIG. 6 is a part of a process order cross-sectional view in a step that follows the step of FIG. 5 for describing a conventional example.

[Explanation of symbols]

101, 201 n-type silicon substrate 102, 202 n-type epitaxial layer 103, 203 element isolation oxide film 104, 204 channel stopper 105, 112, 205, 212 silicon oxide film 106, 206 graft base region 107, 207 silicon nitride film 108, 208 Base region 109, 209 n ⁺ -type polycrystalline silicon layer 110, 210 Emitter region 111 Base contact portion 213 Collector lead-out portion 120, 121, 220 Photoresist film

Claims (6)

(57) [Claims] (1) a step of forming an n-type epitaxial layer on an n-type silicon substrate; and (2) a high impurity concentration by selectively introducing a p-type impurity into a surface region of the n-type epitaxial layer. forming a p-type diffusion layer; and (3) forming a silicon oxide film on the substrate and selectively removing the silicon oxide film by etching to remove the high impurity concentration p.
Forming an emitter opening on the p-type diffusion layer; and (4) compensating or out-diffusing a p-type impurity in the high impurity concentration p-type diffusion layer through the emitter opening. Forming a low-impurity-concentration p-type region in the high-impurity-concentration p-type diffusion layer; and (5) forming a polycrystalline silicon layer containing an n-type impurity on the emitter opening and performing heat treatment. Forming a n-type diffusion layer in the surface region of the concentration p-type region. 2. The method according to claim 1, wherein, in the step (3), a silicon nitride film is formed on the silicon oxide film, and the two-layer film is etched to form the emitter opening. A method for manufacturing a bipolar transistor. 3. The method according to claim 1, wherein in the step (4), the substrate is treated with hot phosphoric acid to reduce the p-type impurity concentration in the high impurity concentration p-type diffusion layer. A manufacturing method of the bipolar transistor according to the above. 4. The method according to claim 4, wherein in the step (4), the substrate in the high impurity concentration p-type diffusion layer is thermally oxidized.
2. The method for manufacturing a bipolar transistor according to claim 1, wherein the type impurities are out-diffused. 5. The bipolar transistor according to claim 1, wherein in the step (4), a p-type impurity in the high impurity concentration p-type diffusion layer is compensated by ion implantation of an n-type impurity. Manufacturing method. 6. After the (4) th step, the (5) th step
2. The method for manufacturing a bipolar transistor according to claim 1, wherein a step of forming a sidewall insulating film on the side surface of said emitter opening is inserted by depositing an insulating film and etching back said insulating film before said step.