JPH11289082A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a low source resistance and a high degree of integration. SOLUTION: In the surface layer of an N<+> -type epitaxial layer 2, N<+> -type impurity diffusion areas 8 are formed at the spots which become contact sections and, under the areas 8, first P-type impurity diffusion areas 7 are formed. In addition, second P<+> -type impurity diffusion areas 9 containing a P<+> -type impurity at a higher concentration than that in the areas 7 are formed in the areas 7. Side walls 10 prevent the side sections of gate electrodes 4 from coming into contact with wiring 12. In the partial central area of the surface of the n<-> -type epitaxial layer 2 at the spots which become contact sections, groove sections 11 are formed to the second P<+> -type impurity diffusion areas 9 through the N<+> -type impurity areas 8. The wiring 12 is connected to the first P<+> type impurity areas 8 and, at the same time, to the second P<+> type impurity areas 9 through the groove sections 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power MOSFET.
T and insulated gate bipolar transistor (IGBT)
And a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional N ⁺ in a semiconductor device.
FIG. 14 is a cross-sectional view schematically showing a step of forming a / P ⁺ common contact portion. First, as shown in FIG.
-Type epitaxial substrate 50 to form the gate insulating film 51 and gate electrode 52 on the patterned this, as shown in FIG. (B), by implanting boron (B) to the N-type epitaxial substrate 50 P ^- -type An area 53 is formed. Next, as shown in FIG. 4C, a resist pattern 54 is formed, and a P ⁺ -type region 55 is formed substantially at the center of the P ^-- type region 53 using the resist pattern 54 as a mask. Then, the resist pattern 54 is removed to form a resist pattern 56 having a resist on the P ⁺ -type region 55, as shown in FIG. An N ⁺ type region (source region) 57 is formed in the portion. Next, the resist pattern 56 is removed,
An interlayer insulating film 58 covering the gate electrode 52 is formed, and a wiring 59 is formed.

As a conventional method of manufacturing a power MOSFET or the like, there is a method disclosed in Japanese Patent Application Laid-Open No. 5-121745. In this method, a gate insulating film, a polycrystalline silicon film, and an oxide film are formed on a semiconductor substrate, and a gate electrode is formed using a photoresist pattern as a mask. Then, a P ^- type region and a P ⁺ type region (body region) are formed, and thereafter, an N ⁺ type region (source region) is formed in the surface layer portion of the substrate. After that, the phosphor glass is reflowed and the entire surface of the substrate is etched, so that the phosphor glass is left on the side of the gate electrode and the substrate surface at a portion to be a contact region is exposed. Next, the etching gas is changed and the substrate surface is etched until it reaches the P ⁺ -type region, and then wiring is provided.

[0004]

In the conventional method shown in FIG. 8, two resist pattern forming steps are required to form the P ⁺ type region 55 and the N ⁺ type region 57. In addition, it is not easy to accurately leave the resist on the P ⁺ type region 55 to form the N ⁺ type region 57,
There is a disadvantage that the yield of the product is low because the resist is easily peeled. Further, in the interlayer insulating film 58 covering the gate electrode 52, the thickness between the upper surface of the gate electrode 52 and the wiring 59 needs to be approximately 0.8 μm, so that the thickness of 0. As a result of the existence of the interlayer insulating film 58 having a thickness of 8 μm, the interval between the gate electrodes 52 is increased, and there is a disadvantage that the integration degree of the semiconductor device cannot be increased.

In the technique disclosed in Japanese Patent Application Laid-Open No. 5-121745, since the wiring only contacts a small area at the end with respect to the N ⁺ type area, the source resistance is increased and V There is a disadvantage that _GS is difficult to apply.

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention can reduce the source resistance, increase the degree of integration, and manufacture a semiconductor device and a semiconductor device which are relatively easy to manufacture. Provide a way.

[0007]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film and a film serving as a gate electrode formed on the semiconductor substrate, and a gate upper surface insulating film. A stacked film body made of a film, a first conductivity type impurity diffusion region formed in a surface layer of the semiconductor substrate at a location where the stacked film body is removed in a predetermined pattern,
A first impurity diffusion region of the second conductivity type formed on the lower layer side to cover the impurity diffusion region of the first conductivity type;
The second impurity diffusion region of the second conductivity type formed in the first impurity diffusion region of the second conductivity type at a higher concentration than the second impurity diffusion region and the side portion of the gate electrode contact the wiring. A side insulating film to be prevented, and a second conductive film formed in a part of the removed portion where the side insulating film is not formed on the surface of the semiconductor substrate, penetrating the impurity diffusion region of the first conductivity type. A trench that reaches the second impurity diffusion region of the mold, and a portion where the side insulating film is not formed in the removed portion, is connected to the impurity diffusion region of the first conductivity type, and passes through the trench. A wiring connected to the second impurity diffusion region of the second conductivity type.

In the above structure, the groove penetrating the first conductivity type impurity diffusion region is formed in a part of the semiconductor substrate surface at a portion where the side insulating film is not formed at the removed portion. It is formed. Therefore, the wiring which enters the portion where the side insulating film is not formed in the removed portion is only the side portion of the first conductivity type impurity diffusion region by the trench with respect to the first conductivity type impurity diffusion region. In addition, since the contact is made also on the upper surface, the source resistance can be reduced. Further, since the step shown in FIG. 8D is unnecessary, there are no drawbacks such as difficulty in accurately leaving the resist, and easy peeling of the resist resulting in low product yield.

The side insulating film may be a side wall made of a silicon oxide film formed by etch back. The sidewalls can keep the insulation between the gate and the source constant without depending on the accuracy of the photolithography process, so that the distance between the gate electrodes can be narrowed and the degree of integration can be improved.

In the method of manufacturing a semiconductor device according to the present invention, a side insulating film for preventing a side portion of the gate electrode from contacting a wiring is formed at a removed portion serving as a contact portion on a side of the gate electrode. And a step of forming a groove in the impurity diffusion region of the surface layer of the semiconductor substrate at the removed portion in a part of the portion where the side insulating film is not formed at the removed portion. It is characterized by the following.

Further, according to a method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a gate insulating film, a film to be a gate electrode, and a gate upper surface insulating film on a semiconductor substrate; And forming a first conductivity type impurity diffusion region located on the surface layer portion of the semiconductor substrate at the removed portion and a second conductivity type first impurity diffusion region located thereunder. Performing a step of forming a side insulating film for preventing a side portion of the gate electrode from contacting a wiring; removing a gate insulating film on a substrate beside the side insulating film; Applying a resist to the resist, removing the resist in a partial region of the portion where the side insulating film is not formed in the removed portion to form a resist pattern; and Forming a groove through the impurity diffusion region of the first conductivity type to reach the first impurity diffusion region of the second conductivity type by using the turn as a mask; and forming a first groove of the second conductivity type through the groove. Forming a second conductivity type second impurity diffusion region having a concentration higher than that of the second conductivity type, and connecting the second conductivity type impurity diffusion region to the first conductivity type impurity diffusion region through the trench. Forming a wiring connected to the second impurity diffusion region.

Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film made of silicon oxide, a film serving as a gate electrode, a gate upper insulating film made of silicon oxide, and a silicon nitride film on a semiconductor substrate. Removing a film serving as a gate electrode, a gate upper surface insulating film, and a silicon nitride film in a predetermined pattern; and removing a first conductivity type impurity diffusion region located in a surface layer portion of the semiconductor substrate at a removed portion and a lower layer side thereof. Forming a first impurity diffusion region of a second conductivity type located on the side of the substrate; and depositing a silicon oxide film and performing etch back to prevent a side wall of the gate electrode from contacting a wiring. Forming and removing the gate insulating film on the substrate on the side of the side wall; applying a resist over the entire surface of the substrate; Forming a resist pattern by removing the resist in a partial region of the portion where the sidewall is not formed, and penetrating the impurity diffusion region of the first conductivity type using the resist pattern as a mask. Forming a groove portion reaching the first impurity diffusion region of the second conductivity type, and forming a second portion of the second conductivity type having a higher concentration than the first impurity diffusion region of the second conductivity type through the groove. Forming an impurity diffusion region, and forming a wiring connected to the first conductivity type impurity diffusion region and connected to the second conductivity type second impurity diffusion region via the groove. It is characterized by including.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a power MOSF of this embodiment.
It is sectional drawing which showed ET (semiconductor device). N⁺Type
On a substrate (for example, specific resistance 0.006Ω · cm) 1
Is N^-Type epitaxial layer (for example, specific resistance 0.2 to
0.3 Ω · cm) 2. N^-Epitaxy
Silicon oxide (SiO 2)_TwoConsisting of
A gate insulating film 3, a gate electrode 4 made of polysilicon,
Silicon oxide (SiO _Two) Gate top insulating film
5, a silicon nitride film 6 is formed in this order. Less than
Lower, gate insulating film 3, gate electrode 4, gate upper surface insulating film
5 and the whole of the silicon nitride film 6
U.

The laminated film body is removed in a predetermined pattern to expose the surface of the N ⁻ type epitaxial layer 2.
N ⁻ -type epitaxial layer 2 at this removed portion (exposed portion)
An N ⁺ -type impurity diffusion region 8 is formed in the surface layer. Moreover, its lower side so as to cover the impurity diffusion region 8 of the N ⁺ -type, P ^- with the first impurity diffusion region 7 of the mold is formed, the P ^- first impurity diffusion regions of the mold 7, the P ⁺ -type second concentration of a higher concentration
Impurity diffusion region 9 is formed.

The removed portion is a portion where the material of the wiring 12 is filled to form a contact portion, and the gate electrode 4 is removed so that the side of the gate electrode 4 does not contact the wiring 12.
A sidewall 10 made of silicon oxide (SiO ₂ ) is formed on the side. Then, a part of the removed portion where the sidewall 10 is not formed, in the central part of the surface of the N ⁻ -type epitaxial layer 2, penetrates through the N ⁺ -type impurity diffusion region 8 and has P ⁺ A groove (hole) 11 reaching the second impurity diffusion region 9 of the mold is formed.

The wiring 12 has a side wall at the removed portion.
Into the part where the nozzle 10 is not formed, and N⁺Improper type
Connected to the pure substance diffusion region 8 and through the groove 11
P ⁺It is also connected to the second impurity diffusion region 9 of the type. wiring
12, a passivation film 13 is formed.
You.

In the above configuration, the trench 11 penetrating the N ⁺ -type impurity diffusion region 8 is formed in the portion of the N ⁻ -type epitaxial layer 2 where the side wall 10 is not formed at the removed portion. It is formed in a central partial area.
Accordingly, the side wall 10 is the same as the removed portion.
The wiring penetrating into the portion where no is formed contacts the N ⁺ -type impurity diffusion region 8 not only on the side surface of the N ⁺ -type impurity diffusion region 8 due to the trench 11 but also on the upper surface. Resistance can be reduced. Further, since the step shown in FIG. 8D shown in the conventional example is unnecessary, there are disadvantages such as difficulty in accurately leaving the resist, and easy peeling of the resist, resulting in low product yield. Absent.

The sidewalls 10 formed on the sides of the gate electrode 4 can keep the insulation between the gate and the source constant without depending on the precision of the photolithography process. The distance between them can be reduced to improve the degree of integration (for example, about 50%). Also,
ON resistance can also be reduced.

Next, an embodiment of a method for manufacturing a power MOSFET having the above structure will be described with reference to FIGS.

First, as shown in FIG. 2, an N ⁻ -type epitaxial layer 2 is grown on an N ⁺ -type silicon substrate 1.
Then, a field oxide film (not shown) is deposited on the N ⁻ -type epitaxial layer 2 so as to have a thickness of 5000Å10000Å, and an element formation region (active region) is selectively formed by patterning. Then, silicon oxide to be the gate insulating film 3 of the MOS transistor is formed by a thermal oxidation method or the like. Next, polysilicon to be the gate electrode 4 is deposited to a thickness of 5000 ° by a CVD method, and is doped with phosphorus (P) (not shown) to perform a process for making the polysilicon conductive.

Next, as shown in FIG. 3, a silicon oxide to be a gate upper surface insulating film 5 is formed on a polysilicon film to be a gate electrode 4 by 8000.degree.
And a silicon nitride film 6 is deposited on the upper surface thereof to a thickness of 200 ° by a plasma CVD method.

Next, as shown in FIG. 4, the gate patterning of the MOS transistor is performed by using the photolithography technique. That is, the silicon nitride film 6, the silicon oxide that becomes the gate upper surface insulating film 5, and the polysilicon that becomes the gate electrode 4 are etched and removed. At this point, the gate insulating film is not removed. Then, boron (B) is implanted in the removed portion under the condition that the dose amount is 1E14 / cm ^2, and heat treatment is performed for 4 hours at a temperature condition of 1000 ° C. to form a P ⁻ -type first impurity diffusion region 7. Get. Then, after removing the gate insulating film,
Arsenic (As) is implanted under the condition that the dose amount becomes 5E15 / cm ^2, and a heat treatment is performed at 1000 ° C. for 10 minutes to obtain an N ⁺ -type impurity diffusion region 8.
An oxidation treatment is performed at 50 ° C. for 20 minutes.

Next, as shown in FIG. 5, the side wall 10 is formed to have a thickness of about 0.2 μm. The sidewalls 10 can be formed by depositing silicon oxide on the entire surface of the substrate by a high-temperature oxide film deposition method and performing an etch-back process. At this time, the silicon oxide formed during the oxidation after the As implantation at the removal location is removed, and the surface of the N ⁻ epitaxial layer 2 is exposed.

Next, as shown in FIG. 6, the grooves 11, P ⁺
A second impurity diffusion region 9 is formed. The groove 11 is
It is obtained by applying a resist on the entire surface of the substrate to form a resist pattern in which a portion to be the groove 11 is opened, and etching the portion to be the groove 11.
The trench 11 is required to have a depth penetrating the N ⁺ -type impurity diffusion region 8 and reaching the P ⁺ -type first impurity diffusion region 7. P
^{The +} type second impurity diffusion region 9 is obtained by implanting boron (B) under the condition of 2E15 / cm ^{2 using} the resist pattern as a mask and performing a heat treatment at 1000 ° C. for 20 minutes. Can be After that, the resist pattern is removed.

Next, as shown in FIG. 7, a wiring 12 and a passivation film 13 are formed. The wiring 12 is obtained by depositing a metal film such as aluminum to a thickness of 3 μm and performing patterning.

The above-described manufacturing method is an example, and other methods can be used. For example, in the above example, the P ⁺ -type second impurity diffusion region 9 is formed via the trench 11.
Forming the trench 11 and the P ⁺ -type second impurity diffusion region 9 in a so-called self-alignment manner. However, the P ⁺ -type second impurity diffusion region 9 is formed in advance. The groove 1 should be
It is also possible to use a method of forming 1 by photolithography.

Although the side insulating film has a side wall made of silicon oxide, the side insulating film may be made of, for example, phosphorus glass as disclosed in Japanese Patent Application Laid-Open No. 5-121745. Things. In this case, after removing the phosphorus glass other than the portion serving as the side insulating film, as described with reference to FIG.
The trench 11 may be formed by photolithography, and the P ⁺ -type second impurity diffusion region 9 may be formed.
Further, although the wiring is formed leaving the silicon nitride film, the wiring may be formed by removing the silicon nitride film. Further, the semiconductor device of the present invention has the power MO
It is needless to say that the present invention is not limited to the SFET but is also suitable as an IGBT or the like.

[0029]

As described above, according to the present invention, the wiring is in contact with the upper surface of the impurity diffusion region of the first conductivity type, so that the source resistance can be reduced. In the case where the side insulating film is formed of a sidewall, the sidewall can maintain a constant insulation between the gate and the source without depending on the accuracy of the photolithography process. There is an effect that the degree of integration can be improved by narrowing.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process chart showing a method for manufacturing the semiconductor device of FIG. 1;

FIG. 3 is a process chart showing a step subsequent to FIG. 2;

FIG. 4 is a process chart showing a step subsequent to FIG. 3;

FIG. 5 is a process chart showing a step subsequent to FIG. 4;

FIG. 6 is a process chart showing a step subsequent to FIG. 5;

FIG. 7 is a process chart showing a step subsequent to FIG. 6;

FIG. 8 is a process chart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 N ⁺ -type silicon substrate 2 N ^- -type epitaxial layer 3 gate insulating film 4 gate electrode 4 5 gate top insulating film 6 of silicon nitride film 7 P ^- -type first impurity diffusion region 8 N ⁺ -type impurity diffusion regions 9 P of ⁺ -Type second impurity diffusion region 10 sidewall 11 groove 12 wiring

Claims (5)

[Claims] 1. A semiconductor substrate, a laminated film body formed on a gate insulating film, a film to be a gate electrode, and a gate upper surface insulating film formed on the semiconductor substrate, and a place where the laminated film body is removed in a predetermined pattern. A first conductivity type impurity diffusion region formed in the surface layer of the semiconductor substrate; and a second conductivity type impurity diffusion region formed in a lower layer side to cover the first conductivity type impurity diffusion region.
A first impurity diffusion region of a conductivity type; a second impurity diffusion region of a second conductivity type formed in the first impurity diffusion region of the second conductivity type at a higher concentration than the first impurity diffusion region; A side insulating film for preventing a side portion of the electrode from contacting a wiring; and a first conductive film formed on a portion of the semiconductor substrate surface at the removed portion where the side insulating film is not formed; A trench portion penetrating through the impurity diffusion region of the second conductivity type and reaching the second impurity diffusion region of the second conductivity type; A wiring connected to the diffusion region and connected to the second impurity diffusion region of the second conductivity type via the trench. 2. The semiconductor device according to claim 1, wherein said side insulating film is a side wall made of a silicon oxide film formed by etch back. 3. A step of forming a side insulating film for preventing a side portion of the gate electrode from contacting a wiring at a removed portion serving as a contact portion on a side of the gate electrode; Forming a groove in the impurity diffusion region of the surface layer portion in a part of the portion where the side insulating film is not formed at the removed portion. . 4. A step of forming a gate insulating film, a film to be a gate electrode and a gate upper surface insulating film on a semiconductor substrate, a step of removing the film to be a gate electrode and the gate upper surface insulating film in a predetermined pattern, Forming a first conductivity type impurity diffusion region located in a surface layer portion of the semiconductor substrate at the specified location and a second conductivity type first impurity diffusion region located thereunder; and a side portion of the gate electrode. Forming a side insulating film that prevents contact with the wiring, removing the gate insulating film on the substrate beside the side insulating film, applying a resist over the entire substrate, Removing the resist in a part of the portion where the side insulating film is not formed to form a resist pattern; and using the resist pattern as a mask to remove the first conductivity type. Forming a groove extending through the pure diffusion region to reach the first impurity diffusion region of the second conductivity type, and forming a groove having a higher concentration than the first impurity diffusion region of the second conductivity type through the groove. Forming a second impurity diffusion region of the second conductivity type; connecting to the first impurity diffusion region of the first conductivity type; and connecting to the second impurity diffusion region of the second conductivity type via the groove. Forming a wiring. A method for manufacturing a semiconductor device, comprising: 5. A step of forming a gate insulating film made of silicon oxide, a film serving as a gate electrode, a gate upper surface insulating film made of silicon oxide and a silicon nitride film on a semiconductor substrate, and forming the gate electrode film and a gate upper surface on the semiconductor substrate. A step of removing the insulating film and the silicon nitride film in a predetermined pattern; and a step of removing a first conductivity type impurity diffusion region located in a surface layer portion of the semiconductor substrate at the removed portion and a second conductivity type first diffusion region located thereunder. Forming a silicon oxide film and performing etch-back to form a sidewall for preventing a side portion of the gate electrode from contacting a wiring, and forming a sidewall on the side of the sidewall. Removing the gate insulating film on the substrate; applying a resist to the entire surface of the substrate; Forming a resist pattern by removing the resist in a partial region of the first portion; and using the resist pattern as a mask to penetrate the impurity diffusion region of the first conductivity type and form a first portion of the second conductivity type. Forming a groove reaching the impurity diffusion region; forming a second impurity diffusion region of the second conductivity type with a higher concentration than the first impurity diffusion region of the second conductivity type through the groove; ,
Forming a wiring connected to the impurity diffusion region of the first conductivity type and connected to the second impurity diffusion region of the second conductivity type through the trench. Production method.