JP2594697B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a resistor made of polysilicon and a shallow junction.

[Conventional technology]

A method of manufacturing a conventional bipolar integrated circuit having a resistor will be described with reference to FIG.

First, as shown in FIG. 3 (a), after forming a P-type buried layer 2 and an N-type epitaxial layer 3 in a P-type semiconductor substrate 1, the semiconductor substrate is thermally oxidized to form a first oxide film 4. Form. Next, the first oxide film 4 is selectively etched and removed by photolithography, and a diffusion window is opened. Next, FIG. 3 (b)
As shown in FIG. 7, the insulating diffusion layer 5 is formed by diffusing a large amount of P-type impurities. Next, after the first oxide film 4 is removed by etching, the semiconductor substrate is again thermally oxidized to form a second thin oxide film 6.

Next, after the surface of the second oxide film 6 other than on the collector diffusion window is covered and protected by the first photoresist layer 7, a large amount of N-type impurities are ion-implanted from the upper surface to form the collector diffusion layer 8.

Next, as shown in FIG. 3 (c), after the first photoresist layer 7 is entirely removed, a high-temperature heat treatment is performed to anneal the collector diffusion layer, and then the second layer other than on the active base diffusion window is again formed. The surface of the oxide film 6 is covered and protected by a second photoresist layer 9. Then a P-type impurity the second photoresist layer 9 from the upper surface as a mask, for example, a B ⁺ 30 keV,
The active base diffusion layer 10 is formed by ion implantation under the condition of 3 × 10 ¹⁴ / cm ² . Next, as shown in FIG. 3 (d), after removing the second photoresist layer 9, a nitride film 11 is formed by a normal vapor deposition method. Next, the emitter diffusion window, the base contact window, and the collector contact window are opened by selectively etching and removing the nitride film 11 and the second oxide film 6 sequentially by a photolithography method. Thereby, a polysilicon layer 12A having a thickness of about 0.2 μm is formed on the entire surface. Next, as the N type from the upper surface of the polysilicon layer 12A, for example, As ⁺ is ion-implanted under the conditions of 70 keV and 1 × 10 ¹⁵ / cm ² , and at least the surface of the resistance element forming region is made third.
And is covered with a photoresist layer 13.

Next, as shown in FIG.
Again as an N-type impurity, for example, As ⁺ is 70 keV1
After a large amount of ions are implanted under the condition of × 10 ¹⁶ / cm ² , the third photoresist layer 13 is entirely removed. Next, after the third oxide film 14 is formed again to a thickness of 0.1 μm by the vapor phase growth method, the polysilicon layer 12A is annealed at 800 ° C. for 30 minutes to obtain the ion-implanted N-type impurity concentration distribution. Measure uniformity. Next, the third oxide film 14 and the polysilicon layer 12A other than at least the emitter diffusion window, the collector contact window, and the polysilicon resistance element portion are sequentially etched and removed by photolithography. Next, as shown in FIG. 3 (f), annealing of the active base diffusion layer 10 and formation of the emitter diffusion layer 15 having a depth of about 0.1 μm are simultaneously performed by performing a heat treatment at, for example, 950 ° C. for 30 minutes. Next, base contact diffusion (for example, 900
(BCl _{3 for} 30 minutes) to form the base contact diffusion layer 16.

Next, as shown in FIG. 3 (g), the polysilicon layer 12A
The upper third oxide film 14 is entirely etched and removed. Next, after a fourth oxide film 19 is formed by a vapor phase growth method, the fourth oxide film 19 is selectively etched and removed by a photo-etching method, so that a resistive contact window, a base contact window opening and an emitter are formed. The polysilicon layer 12A on the diffusion layer 15 and the collector diffusion layer 8 is exposed. Then, after Al is vapor-deposited from the upper surface, Al is selectively etched away by photolithography, and the collector electrode 20, base electrode 21, emitter electrode 22, resistance electrode 23, and wiring between elements are completed to complete a bipolar integrated circuit. Let it.

[Problems to be solved by the invention]

In general, in order to improve the high frequency characteristics of a bipolar IC, it is important to make the transistor element finer, to make each junction shallower, and to reduce the stray capacitance of the resistance element.
Therefore, in recent years, there has been a tendency to avoid the displacement of the diffusion window by simultaneously opening the emitter diffusion window and the base contact window, and to use a polysilicon layer containing arsenic as the emitter diffusion source and the resistance element. It is.

Therefore, the heat treatment conditions that can be performed after the formation of the polysilicon layer containing arsenic are naturally limited. In the above-described conventional manufacturing method, since the polysilicon layer 12A is annealed at 800 ° C., the impurity concentration distribution can be made uniform. Not enough
A region with the highest impurity concentration is formed at the center of the polysilicon layer, and a concentration gradient is created. As a result, due to the concentration dependency of the etching rate of the polysilicon layer, the shape of the side wall after the etching of the polysilicon layer becomes an inversely tapered shape. This was noticeable in the polysilicon resistance element portion.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, an active base region is formed by forming a first insulating layer on a surface of a semiconductor substrate of a first conductivity type and then selectively introducing impurities of a second conductivity type through the first insulating layer. Forming, forming a second insulating layer that is not etched under the armpit dipping the first insulating layer on the active base region, selectively etching away the second insulating layer and the first insulating layer Opening the emitter diffusion window and the base contact diffusion window, the opening region and the second
Forming a polysilicon layer on the first insulating layer, and then introducing a large amount of impurities of the first conductivity type from the upper surface; and forming a third insulating layer on the polysilicon layer which is not etched by a liquid for immersing the second insulating layer.
Forming an insulating layer, selectively removing the third insulating layer and the polysilicon layer by etching to expose at least the base contact diffusion window, and then introducing an impurity from the polysilicon layer into the active base region. Forming an emitter region, forming an emitter region, introducing a second conductivity type impurity from the base contact diffusion window to form a base contact region, and then removing the entire surface of the third insulating layer by etching to remove the polysilicon. Exposing the layer, etching away the exposed polysilicon layer on the base contact region and the emitter region other than the resistance region of the polysilicon layer, and processing so that at least the side surface of the polysilicon resistance region becomes trapezoidal. And a process.

〔Example〕

Next, this embodiment will be described with reference to the drawings.
FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1 (a), an N-type buried layer 2, an epitaxial layer 3, and a first oxide film layer 4 are formed in a P-type semiconductor substrate 1 in the same manner as in a conventional manufacturing method, and then a diffusion window is formed. Open. Next, as shown in FIG. 1 (b), after a P-type impurity is introduced to form an insulating diffusion layer 5, a second thin oxide film 6 is formed.
To form a first photoresist layer patterned with
The collector impurity is diffused to form a collector diffusion layer 8, and the first photoresist layer is removed, followed by annealing. Next, using the second photoresist layer 9 as a mask, a P-type impurity is ion-implanted to form an active base diffusion layer 10.

Next, as shown in FIG. 1 (c), after removing the second photoresist layer 9, a nitride film 11 is formed on the entire surface by a vapor phase growth method.
To form Next, the nitride film 11 and the second oxide film 6 are selectively etched to form an emitter diffusion window, a base contact diffusion window, and a collector contact window. Polysilicon layer 12
To form Next, As is applied to the polysilicon layer 12 at 70 keV, 1
Ion implantation is performed under the condition of × 10 ¹⁵ / cm ² .

Next, after a third photoresist layer is formed on the resistance element forming region, As is ion-implanted again under the conditions of 70 keV and 1 × 10 ¹⁶ / cm ² , and then the third photoresist layer is removed. Next, after a third oxide film 14 is formed by vapor phase epitaxy, at least the third oxide film 14 and the polysilicon layer 12 on the base contact window are sequentially etched and removed by photolithography, and the base contact diffusion is performed again. Expose the window.

Next, as shown in FIG. 1 (d), high-temperature heat treatment at 950 ° C. for 30 minutes is performed to anneal the active base diffusion layer 10, form the emitter diffusion layer 15, and anneal the polysilicon layer 12 (ion implantation is performed). , The base contact diffusion (for example, 900).
(BCl _{3 for} 30 minutes) to form the base contact diffusion layer 16. Next, after the entire third oxide film 14 is removed by etching, at least the base contact diffusion window is covered and protected by a fourth photoresist layer 17 by photolithography. Next, at least on the emitter diffusion window, on the collector contact window and on the resistance element forming region of the polysilicon layer 12, a fifth
And is covered with a photoresist layer 18.

Next, as shown in FIG. 1E, the polysilicon layer 12 is selectively etched and removed by RIE using the fourth and fifth photoresist layers 17 and 18 as an etching-resistant mask.
The fourth and fifth photoresist layers are removed. Thereafter, in the same manner as in the conventional manufacturing method, a fourth oxide film 19 is formed and then patterned to form a polysilicon layer on the resistive contact window and the base contact window and on the emitter diffusion layer 15 and the collector diffusion layer 8. Make 12 exposures. Next, after an Al film is formed, patterning is performed to form a collector electrode 20, a base electrode 21, an emitter electrode 22, a resistance electrode 23, and a wiring between elements.

As described above, in the first embodiment, after the polysilicon layer 12 on the base contact diffusion window is removed by etching, annealing for uniformizing the concentration distribution of the N-type impurities ion-implanted into the polysilicon layer is performed. As a result, the annealing temperature can be increased to about 950 ° C., which is higher than the conventional 800 ° C. As a result, the impurity concentration in the polysilicon layer 12 can be made uniform, and the cross-sectional shape of the sidewall of the polysilicon layer 12 after etching can be reduced. It has become possible to improve the taper shape (about 60mm).

FIG. 2 is a sectional view of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2A, similarly to the first embodiment, an N-type buried layer 2, an N-type epitaxial layer 3, an insulating diffusion layer 5, a second An oxide film 6, a first collector diffusion layer 8, an active base diffuser 10, a nitride film 11, an emitter diffusion window, a base contact diffusion window, a collector contact window, a polysilicon layer 12, and a third oxide film 14 are formed. Thereafter, at least the third oxide film 14 and the polysilicon layer 12 on the base contact window are sequentially etched and removed by photolithography to expose the base contact diffusion window again. Next, a high-temperature heat treatment (for example, 950 ° C. for 30 minutes) is performed to anneal the active base diffusion layer 10, form the emitter diffusion layer 15, and uniformize the ion-implanted N-type impurity concentration distribution. Is performed, base contact diffusion (900 ° C., BCl _{3 for} 30 minutes) is performed to form a base contact diffusion layer 16.

Next, as shown in FIG. 2 (b), after the entire surface of the third oxide film 14 is removed by etching, at least the base contact diffusion window, the emitter diffusion window, the collector contact window, and the resistive element formation region are removed. 6 is covered and protected by a photoresist layer 24. Next, as shown in FIG.
Normal photoresist layer 24 as an etching resistant mask
After selectively removing the polysilicon layer 12 by RIE, the sixth photoresist layer is entirely etched away. Thereafter, similarly to the first embodiment, the collector electrode 20, the base electrode 21, the emitter electrode 22, the resistance electrode 23, and the inter-element wiring are formed.

As described above, in the second embodiment, the first
The same effect as that of the first embodiment can be obtained, and the step of individually covering and protecting the base contact diffusion window from the photoresist layer 12 as in the first embodiment becomes unnecessary, thereby simplifying the manufacturing process. Has the advantage that it becomes possible.

〔The invention's effect〕

As described above, in the bipolar integrated circuit to which the present invention is applied, the polysilicon layer on the base contact diffusion window is removed by etching, and then the polysilicon layer is annealed. It can be performed at a higher temperature. As a result, the impurity concentration in the polysilicon layer can be made uniform, and the cross-sectional shape of the side wall of the polysilicon layer after etching can be improved from a reverse taper to a tapered shape. There is an effect that the remaining metal can be completely eliminated.

[Brief description of the drawings]

FIGS. 1 and 2 are sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention.
FIG. 1 is a sectional view of a semiconductor chip for explaining a conventional example. DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate, 2 ... buried layer, 3 ... epitaxial layer, 4 ... first oxide film, 5 ... insulating diffusion layer, 6
... A second oxide film, 7... A first photoresist layer, 8.
... collector diffusion layer, 9 ... second photoresist layer, 10 ...
... Active base diffusion layer, 11 ... nitride film, 12,12A ... polysilicon layer, 13 ... third photoresist layer, 14 ... third oxide film, 15 ... emitter diffusion layer, 16 ... base Contact diffusion layer, 17 ... fourth photoresist layer, 18 ... fifth photoresist layer, 19 ... fourth oxide film, 20 ... collector electrode, 21 ... base electrode, 22 ... emitter electrode, 23 ......
Resistive electrode, 24... Sixth photoresist layer.

Claims (1)

(57) [Claims] A first insulating layer formed on the surface of the semiconductor substrate of the first conductivity type; and a second insulating layer selectively formed through the first insulating layer.
A step of forming an active base region by introducing a conductivity type impurity, a step of forming a second insulating layer on the active base region which is not etched by a solution immersing the first insulating layer, the second insulating layer and Selectively etching and removing the first insulating layer to open an emitter diffusion window and a base contact diffusion window; forming a polysilicon layer on the opening region and the second insulating layer; A step of introducing a large amount of impurities, a step of forming a third insulating layer on the polysilicon layer which is not etched by a solution immersing the second insulating layer, and selectively forming the third insulating layer and the polysilicon layer. Removing by etching to expose at least the base contact diffusion window, and then introducing an impurity from the polysilicon layer into the active base region to form an emitter region; Forming a base contact region by introducing a second conductivity type impurity from the base contact diffusion window after the formation, and then removing the entire surface of the third insulating layer by etching to expose the polysilicon layer; Etching and removing the exposed polysilicon layer on the emitter region and the polysilicon layer other than the resistance region to process at least the side surface of the polysilicon resistance region into a trapezoidal shape. Production method.