JPS6143858B2 - - Google Patents
Info
- Publication number
- JPS6143858B2 JPS6143858B2 JP52109877A JP10987777A JPS6143858B2 JP S6143858 B2 JPS6143858 B2 JP S6143858B2 JP 52109877 A JP52109877 A JP 52109877A JP 10987777 A JP10987777 A JP 10987777A JP S6143858 B2 JPS6143858 B2 JP S6143858B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- oxide film
- type
- conductivity type
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000009826 distribution Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000000605 extraction Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Description
【発明の詳細な説明】
この発明は半導体集積回路の製造法、特にイオ
ン打込みにより形成したウエル表面の不純物濃度
分布の均一化処理法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for uniformizing the impurity concentration distribution on the surface of a well formed by ion implantation.
一つのシリコン半導体基板上に相補的な関係を
もつ素子を形成する場合、一方の素子を基板と異
なる導電型の領域、ウエルの中に形成するが、こ
のウエルは通常イオン打込み法により半導体中に
打込んだ不純物を引伸し拡散することにより得
る。この不純物イオン打込みは半導体表面に形成
した酸化膜（SiO2）をマスクとして選択的に形成
するものであるが、不純物拡散を行う際に不純物
は酸化膜とシリコンとの界面で偏析を起し、例え
ばリン不純物の場合はシリコン表面で高濃度化
し、一方、ボロン不純物はSiO2膜に吸収されて
低濃度化する等異常な分布をすることが問題とな
つている。そしてこのような異常な濃度分布のた
め、例えばnpnトランジスタの高耐圧化ができな
いことになつた。 When forming elements with a complementary relationship on one silicon semiconductor substrate, one element is formed in a region or well of a conductivity type different from that of the substrate, but this well is usually implanted into the semiconductor by ion implantation. Obtained by stretching and diffusing implanted impurities. This impurity ion implantation is selectively formed using an oxide film (SiO 2 ) formed on the semiconductor surface as a mask, but when performing impurity diffusion, impurities segregate at the interface between the oxide film and silicon. For example, in the case of phosphorus impurities, the concentration is high on the silicon surface, while boron impurities are absorbed into the SiO 2 film and become low in concentration, resulting in abnormal distribution, which is a problem. Due to such an abnormal concentration distribution, it has become impossible to increase the breakdown voltage of, for example, an npn transistor.
この発明は上記の問題を解決するべくなされた
もので、その目的は耐圧向上を計ると共に不純物
分布のバラツキによるVTHのバラツキを防止し
た半導体集積回路装置を提供することにある。 The present invention has been made to solve the above problems, and its purpose is to provide a semiconductor integrated circuit device that improves breakdown voltage and prevents variations in VTH due to variations in impurity distribution.
上記目的を達成するためこの発明の一つの構成
は、半導体基板の一主表面の一部にこの基板と異
なる導電型の不純物を拡散し、その上全面に基板
と同じ導電型の低不純物濃度エピタキシヤル成長
半導体層を形成し、この半導体層にその表面の一
部に形成した酸化膜をマスクを通し基板と異なる
導電型の不純物イオン打込みを行い、このイオン
打込み不純物と、前記埋込み拡散不純物とを引伸
し拡散して基板と異なる導電型の低不純物濃度ウ
エルを形成し、表面酸化膜を全面酸化膜を全面的
に除去したエピキシヤル成長半導体層の表面を浅
くエツチング除去した後にこの表面に新たに酸化
膜を形成することを要旨とするものである。 In order to achieve the above object, one structure of the present invention is to diffuse an impurity of a conductivity type different from that of the substrate into a part of one main surface of a semiconductor substrate, and then epitaxy the entire surface with a low impurity concentration of the same conductivity type as the substrate. An oxide film formed on a part of the surface of this semiconductor layer is implanted with impurity ions of a conductivity type different from that of the substrate through a mask, and this ion implanted impurity and the buried diffusion impurity are combined. A low impurity concentration well of a conductivity type different from that of the substrate is formed by stretching and diffusion, and after the surface oxide film is removed by shallow etching, a new oxide film is formed on this surface. Its purpose is to form a
以下、実施例にそつて具体的に説明する。 Hereinafter, a detailed description will be given along with examples.
第１図ａ〜ｉは一つのｐ型シリコン基板上に高
耐圧npnトランジスタを含む集積回路を形成する
場合の製造工程を示し、下記の各工程(a)〜(i)にそ
れぞれ対応する。 1A to 1I show manufacturing steps for forming an integrated circuit including a high breakdown voltage npn transistor on one p-type silicon substrate, and correspond to the following steps (a) to (i), respectively.
(a) Ｐ型シリコン結晶基板（ウエハ）１を用意
し、表面酸化して酸化膜（SiO2）２を形成し、
ホトエツチング技術によりその一部を窓開し、
アンチモンSb（又はヒ素）をデポジシヨン乃
至拡散してn+型拡散層３を形成する。(a) Prepare a P-type silicon crystal substrate (wafer) 1, oxidize the surface to form an oxide film (SiO 2 ) 2,
A part of it was opened using photoetching technology,
An n + -type diffusion layer 3 is formed by depositing or diffusing antimony Sb (or arsenic).
(b) 上記n+型拡散層を含む主面上にp-型不純物
ドープエピタキシヤル成長半導体層４を15〜20
μｍの厚さに形成する。このエピタキシヤル半
導体層４において、この半導体層により埋込ま
れたn+型拡散層に対応する側の部分を領域
とし、n+型拡散層と対応しない側の部分を領
域とする。(b) 15 to 20 epitaxially grown semiconductor layers 4 doped with p - type impurities on the main surface including the n + type diffusion layer.
Formed to a thickness of μm. In this epitaxial semiconductor layer 4, the part on the side corresponding to the n + type diffusion layer buried by this semiconductor layer is defined as a region, and the part on the side not corresponding to the n + type diffusion layer is defined as a region.
(c) 上記エピタキシヤル半導体層４を表面酸化し
て酸化膜５を形成し、前記領域に対応する酸
化膜の一部をホトエツチングにより窓開し、こ
の窓開部６を通してリン不純物をイオン打込み
することにより、エピタキシヤル半導体層中に
n+型イオン打込み層７を形成する。(c) The surface of the epitaxial semiconductor layer 4 is oxidized to form an oxide film 5, a portion of the oxide film corresponding to the region is opened by photoetching, and phosphorus impurities are ion-implanted through this window opening 6. As a result, in the epitaxial semiconductor layer
An n + type ion implantation layer 7 is formed.
(d) この後適当の温度条件、例えば1200℃，20時
間で温度処理を行なうことにより、前記イオン
打込み層７及び埋込み拡散層３からn+型不純
物をエピタキシヤル半導体層中に引伸し拡散
し、表面から埋込層に達する低不純物濃度の
n-型ウエル８を形成する。この温度処理によ
り表面に酸化膜９が生成する。(d) After that, by performing a temperature treatment under appropriate temperature conditions, for example, 1200° C. for 20 hours, the n + type impurity is stretched and diffused from the ion implantation layer 7 and the buried diffusion layer 3 into the epitaxial semiconductor layer, Low impurity concentration reaching from the surface to the buried layer
An n - type well 8 is formed. This temperature treatment produces an oxide film 9 on the surface.
(e) 表面酸化膜を全面的にエツチング除去した
後、さらにエピタキシヤル半導体層４の表面層
１０を１μｍ程エツチングする。(e) After removing the surface oxide film by etching the entire surface, the surface layer 10 of the epitaxial semiconductor layer 4 is further etched by about 1 μm.
(f) 表面にCVD（気相化学反応析出）法等によ
る新たな酸化膜１１を形成し、その後デンシフ
アイ処理する。なお、上記酸化膜はウエツト酸
素等を用いた表面酸化法により形成しても差支
えない。(f) A new oxide film 11 is formed on the surface by a CVD (vapor phase chemical reaction deposition) method or the like, and then a densifier treatment is performed. Note that the oxide film may be formed by a surface oxidation method using wet oxygen or the like.
(g) 領域において酸化膜の一部を窓開し、リン
等の不純物イオン打込みによりｎ型チヤネル層
１２を形成する。なおこのｎ型チヤネル層形成
は前記した工程ｃ，ｄのイオン打込工程で同時
に行つてもよい。A part of the oxide film is opened in the region (g), and an n-type channel layer 12 is formed by implanting impurity ions such as phosphorus. Note that this n-type channel layer formation may be performed simultaneously in the ion implantation steps c and d described above.
(h) 領域及び領域において酸化膜の一部をホ
ツトエツチングにより窓開し、ボロン不純物の
デポジシヨン乃至拡散により、p+型ベース１
３及びP+型ゲート取出し部１４をそれぞれ形
成する。(h) A part of the oxide film is opened by hot etching in the regions and regions, and p + type base 1 is formed by depositing or diffusing boron impurities.
3 and P + type gate extraction portions 14 are respectively formed.
(i) 同様に酸化膜の他の一部をホトエツチングに
より窓開し、リン（又はヒ素）不純物のデプジ
シヨン乃至拡散によりn+型エミツタ１５、n+
型コレクタ取出し部１６及びn+型ソース，ド
レイン各取出し部１７，１８をそれぞれ形成す
る。この後コンタクトホトエツチング，アルミ
ニウム蒸着，電極パターン・ホトエツチングの
諸工程を経て各領域にコンタクトする電極
（Ｃ，Ｂ，Ｅ，Ｓ，Ｇ，Ｄ）を形成することに
より、領域にnpn型トランジスタ、領域に
ｎチヤネルＪ−FET（接合型電界効果トラン
ジスタ）をそれぞれ完成する。(i) Similarly, another part of the oxide film is opened by photoetching, and the n + type emitter 15, n +
A type collector extraction portion 16 and n + type source and drain extraction portions 17 and 18 are formed, respectively. After that, electrodes (C, B, E, S, G, D) that contact each region are formed through the various steps of contact photoetching, aluminum vapor deposition, and electrode pattern photoetching. Completed n-channel J-FET (junction field effect transistor).
以上実施例で述べた構成によれば下記のように
前記発明の目的を達成できる。 According to the configuration described in the embodiments above, the object of the invention can be achieved as described below.
工程ｃ，ｄで形成したｎ型ウエルにおいては、
不純物リンの濃度分布はSiO2−Si界面で第３図に
示すようにシリコン表面で異常に高いが、工程ｅ
により表面を１μｍ除することにより均一な不純
物濃度分布を得る。 In the n-type well formed in steps c and d,
The concentration distribution of impurity phosphorus is abnormally high on the silicon surface at the SiO 2 -Si interface as shown in Figure 3, but in process e.
By dividing the surface by 1 μm, a uniform impurity concentration distribution is obtained.
一般にnpn型トランジスタにおいては第４図に
示すようにベース，コレクタ接合ＪBC付近におけ
るウエル部のn+型不純物濃度が高く、ＶCBO，Ｖ
CEOがその値で決まり高耐圧化できないが、同図
の破線で示す部分で取除くことにより耐圧が向上
する。 In general, in an npn transistor, as shown in Figure 4, the n + type impurity concentration in the well near the base-collector junction J BC is high, and V CBO , V
The CEO is determined by that value, and it is not possible to increase the voltage resistance, but the voltage resistance can be improved by removing the portion indicated by the broken line in the figure.
この発明は前記実施例に限定されず、これ以外
の種々な変形例を採り得る。例えば実施例１の工
程ｅで全面エツチングに代り、第２図に示すよう
に、n-型ウエルの表面部分のみを選択的にエツ
チングするようにしてもよい。 The present invention is not limited to the above-mentioned embodiments, and various other modifications may be made. For example, instead of etching the entire surface in step e of Example 1, only the surface portion of the n - type well may be selectively etched as shown in FIG.
この発明の適用技術分野は、バイポーラ−
MOSIC，バイポーラーＪ−FET・IC等である。 The technical field to which this invention is applied is bipolar
MOSIC, bipolar J-FET/IC, etc.
第１図ａ〜ｉは本発明の一実施例の製造法の各
工程における半導体の断面図、第２図は本発明の
他の実施例の一部工程における半導体の断面図、
第３図は不純物濃度分布曲線図、第４図は本発明
の原理を説明するためのバイポーラ素子の拡大断
面図である。
１……ｐ型シリコン基板、２……表面酸化膜、
３……n+型埋込拡散層、４……p-型エピタキシ
ヤル半導体層、５……表面酸化膜、６……窓開
部、７……不純物イオン打込み層、８……ｎ型ウ
エル、１０……エツチングされる表面層、１１…
…CVD酸化膜、１２……ｎ型チヤンネル層、１
３……p+型ベース、１４……ｐ型＋ゲート取出
し部、１５……n+型エミツタ、１６……n+型コ
レクタ取出し部、１７，１８……n+型ソース，
ドレイン各取出し部、Ｃ，Ｂ，Ｅ……npnトラン
ジスタの各電極、Ｓ，Ｇ，Ｄ……ｎチヤネルＪ−
FETの各電極。
1A to 1I are cross-sectional views of a semiconductor in each step of a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor in some steps of another embodiment of the present invention.
FIG. 3 is an impurity concentration distribution curve diagram, and FIG. 4 is an enlarged sectional view of a bipolar element for explaining the principle of the present invention. 1...p-type silicon substrate, 2...surface oxide film,
3...n + type buried diffusion layer, 4...p - type epitaxial semiconductor layer, 5... surface oxide film, 6... window opening, 7... impurity ion implantation layer, 8... n type well , 10... surface layer to be etched, 11...
...CVD oxide film, 12...n-type channel layer, 1
3... p + type base, 14... p type + gate extraction section, 15... n + type emitter, 16... n + type collector extraction section, 17, 18... n + type source,
Each drain extraction part, C, B, E...each electrode of npn transistor, S, G, D...n channel J-
Each electrode of FET.
Claims (1)
る導電型の不純物を拡散し、その上全面に基板と
同じ導電型の低不純物濃度エピタキシヤル成長半
導体層を形成し、この半導体層にその表面の一部
に形成した酸化膜をマスクとして基板と異なる導
電型の不純物イオン打込みを行い、このイオン打
込み不純物と前記埋込み拡散不純物とを引伸し拡
散して基板と異なる導電型の低不純物濃度ウエル
を形成し、表面酸化膜を全面的に除去した上記エ
ピタキシヤル成長半導体層の表面を浅くエツチン
グ除去した後にこの表面に新たに酸化膜を形成す
ることを特徴とする半導体集積回路装置の製造
法。1 Semiconductor substrate - impurities of a conductivity type different from that of the substrate are diffused into a part of the main surface, and a low impurity concentration epitaxially grown semiconductor layer of the same conductivity type as the substrate is formed on the entire surface, and the surface of the semiconductor layer is Impurity ions of a conductivity type different from that of the substrate are implanted using the oxide film formed on a part of the substrate as a mask, and the implanted ion impurities and the buried diffusion impurity are stretched and diffused to form a low impurity concentration well of a conductivity type different from that of the substrate. A method for manufacturing a semiconductor integrated circuit device, characterized in that the surface of the epitaxially grown semiconductor layer from which the surface oxide film has been completely removed is removed by shallow etching, and then a new oxide film is formed on this surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10987777A JPS5443688A (en) | 1977-09-14 | 1977-09-14 | Production of semiconductor integrated circuit unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10987777A JPS5443688A (en) | 1977-09-14 | 1977-09-14 | Production of semiconductor integrated circuit unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5443688A JPS5443688A (en) | 1979-04-06 |
| JPS6143858B2 true JPS6143858B2 (en) | 1986-09-30 |
Family
ID=14521427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10987777A Granted JPS5443688A (en) | 1977-09-14 | 1977-09-14 | Production of semiconductor integrated circuit unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5443688A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55146960A (en) * | 1979-05-02 | 1980-11-15 | Hitachi Ltd | Manufacture of integrated circuit device |
| JPS58225663A (en) * | 1982-06-23 | 1983-12-27 | Toshiba Corp | Manufacture of semiconductor device |
| KR930008899B1 (en) * | 1987-12-31 | 1993-09-16 | 금성일렉트론 주식회사 | Manufacturing method of semiconductor device |
| JPH0770703B2 (en) * | 1989-05-22 | 1995-07-31 | 株式会社東芝 | Semiconductor device including charge transfer device and manufacturing method thereof |
-
1977
- 1977-09-14 JP JP10987777A patent/JPS5443688A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5443688A (en) | 1979-04-06 |
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