JPS5443688A - Production of semiconductor integrated circuit unit - Google Patents

Production of semiconductor integrated circuit unit

Info

Publication number
JPS5443688A
JPS5443688A JP10987777A JP10987777A JPS5443688A JP S5443688 A JPS5443688 A JP S5443688A JP 10987777 A JP10987777 A JP 10987777A JP 10987777 A JP10987777 A JP 10987777A JP S5443688 A JPS5443688 A JP S5443688A
Authority
JP
Japan
Prior art keywords
type
area
layer
diffusion
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10987777A
Other languages
Japanese (ja)
Other versions
JPS6143858B2 (en
Inventor
Kaoru Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10987777A priority Critical patent/JPS5443688A/en
Publication of JPS5443688A publication Critical patent/JPS5443688A/en
Publication of JPS6143858B2 publication Critical patent/JPS6143858B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make dielectric strength higher and avoid the irregularity of the threshold voltage by removing slightly the substrate surface, which includes the well area constituting an NPN transistor, by etching to remove the high-impurity concentration layer on the surface and making the surface concentration distribution uniform.
CONSTITUTION: SiO2 film 2 is caused to adhere onto P type Si substrate 1, and an open hole is provided to form N+ type buried area 3 by diffusion, and P type layer 4 is grown epitaxially throughout the surface. Next, the all surface is covered with SiO2 film 5 to open window 6 on area 3, and N+ type ion injection area 7 is provided in layer 4, and N- type well 8 which reaches area 3 is formed by extending diffusion. After that, generated SiO2 film 9 and exposed surface layer 10 of layer 4 are removed by etching, and SiO2 film 11 is newly grown. Next, an open hole is provided in the position apart from area 8, and N type channel area 12 is formed by diffusion, and P+ type gate leading-out part 14 and N+ type souce drain leading- out parts 17 and 18 are provided in area 12. After that, N+ type emitter and N+ type collector leading-out parts 15 and 16 are formed respectively in area 8 by diffusion.
COPYRIGHT: (C)1979,JPO&Japio
JP10987777A 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit Granted JPS5443688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10987777A JPS5443688A (en) 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10987777A JPS5443688A (en) 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit

Publications (2)

Publication Number Publication Date
JPS5443688A true JPS5443688A (en) 1979-04-06
JPS6143858B2 JPS6143858B2 (en) 1986-09-30

Family

ID=14521427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10987777A Granted JPS5443688A (en) 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit

Country Status (1)

Country Link
JP (1) JPS5443688A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146960A (en) * 1979-05-02 1980-11-15 Hitachi Ltd Manufacture of integrated circuit device
US4484388A (en) * 1982-06-23 1984-11-27 Tokyo Shibaura Denki Kabushiki Kaishi Method for manufacturing semiconductor Bi-CMOS device
JPH03114235A (en) * 1989-05-22 1991-05-15 Toshiba Corp Semiconductor device containing charge transfer device and its manufacture
US5156984A (en) * 1987-12-31 1992-10-20 Goldstar Co., Ltd. Manufacturing method for a bi-cmos by trenching

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146960A (en) * 1979-05-02 1980-11-15 Hitachi Ltd Manufacture of integrated circuit device
US4484388A (en) * 1982-06-23 1984-11-27 Tokyo Shibaura Denki Kabushiki Kaishi Method for manufacturing semiconductor Bi-CMOS device
US5156984A (en) * 1987-12-31 1992-10-20 Goldstar Co., Ltd. Manufacturing method for a bi-cmos by trenching
JPH03114235A (en) * 1989-05-22 1991-05-15 Toshiba Corp Semiconductor device containing charge transfer device and its manufacture

Also Published As

Publication number Publication date
JPS6143858B2 (en) 1986-09-30

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