JPS624339A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To achieve a highly integrated semiconductor device, by providing an N<+> type buried layer and a P<+> type buried layer constituting a part of an element isolation region, on the surface of a P-type silicon substrate, in the manner such that they are contacted with each other. CONSTITUTION:A polycrystalline film 2 is formed on the surface of a P-type silicon substrate 1 and arsenic ions are implanted thereinto. The film 2 is then etched with the use of a CVD oxide film 3 as a mask. Thermally oxidized films 5 and N<+> type buried layers 6 are provided. Thereafter, boron ions are implanted to form implanted layers 7. The layers 7 are activated to provide P<+> type buried layers 8. The substrate is subjected to hydrogen burning oxidation, whereby the film 2 is converted into an oxide film. An N-type epitaxial layer 9 is deposited on the whole surface of the substrate 1. The boron ions are diffused into the layer 9 so as to form P-type diffused layers 10 each of which provides an isolation region in cooperation with the layer 8. Emitter regions 12 and collector lead-out regions 13 are then formed.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device of a bipolar type or a semiconductor device in which bipolar and MOS type elements are mixed, by improving element isolation and reducing the cost. This is an attempt to achieve voltage conversion and integration.

[Technical background of the invention]

Bipolar type semiconductor device or bipolar type and MO
A semiconductor device in which S-type elements are mixed includes, for example, an n+ type buried diffusion layer formed on the surface of a p-type silicon substrate, an n-type epitaxial layer formed on the entire surface of this substrate, and a bipolar transistor in this epitaxial layer. It has a structure in which a diffusion layer is formed to constitute an element such as. Conventionally, element isolation of such a semiconductor device has been performed using the following two techniques. First, the first technique is to form an n4'' type buried diffusion layer on the surface of a p-type silicon substrate, form an n-type epitaxial layer on the entire surface, and then diffuse p-type impurities from the surface of the epitaxial layer. The second technique is to form a p+ type resistive diffusion layer that reaches the substrate and use it as an element isolation region.
After forming the type resistance diffusion layer and forming the epitaxial layer,
P-type impurities are diffused from the surface of the corresponding epitaxial layer on the p+ type scattering layer, and p+ is formed by diffusion from both directions.
A resistive diffusion layer is formed to serve as an element isolation region.

[Same subject in background technology]

In the first technique, productivity decreases due to the long time required to diffuse impurities to form the element isolation region, and the lateral spread of the formed element isolation region is large, making it difficult to integrate. It becomes difficult to improve the degree of

On the other hand, in the second technique, since impurities are diffused from both the substrate side and the surface side of the epitaxial layer, the diffusion time is shortened, and the drawbacks of the first technique can be overcome. However, when using the second technique, in order to particularly increase the junction breakdown voltage between the n1 type buried layer and the p+ type element isolation region, the gap between the n+ type buried layer and the p type buried layer is increased. It is necessary to form them at a certain distance (approximately 1 to 2 mm in consideration of mask alignment accuracy). For this reason, high integration of elements is limited. Furthermore, the n+ type and p1 type buried layers must be formed in separate selective diffusion processes.

Therefore, two photolithography steps (PEP) are required before forming the epitaxial layer, making the process complicated.
It also becomes a factor that reduces yield.

[Purpose of the invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks, and provides a bipolar type semiconductor device that can achieve high integration, or a semiconductor device in which bipolar type and MOS type elements are mixed, and a semiconductor device that can be manufactured using an extremely simple process. The aim is to provide a method for manufacturing.

[Summary of the invention]

The present inventor believes that if high integration of elements can be achieved, it will be possible to lower the operating voltage, and as a result, there will be fewer problems even if the junction breakdown voltage between the buried layer and the element isolation region is low. The present invention was developed based on the idea of forming an n+ type buried layer and a p++ buried layer constituting a part of an element isolation region in contact with each other on the surface.

That is, the semiconductor device of the invention of the present application cylinder 1 includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate, and a boundary region between the semiconductor substrate and the semiconductor layer. first and second conductivity type high concentration diffusion layers formed in contact with each other; an element isolation region formed to reach the first conductivity type high concentration diffusion layer from the surface of the semiconductor layer; It is characterized by comprising a conductive type high concentration diffusion layer and a diffusion layer constituting a semiconductor element formed in a semiconductor layer surrounded by an element isolation region.

According to such a semiconductor device, the second conductivity type high concentration diffusion layer (buried layer) and the first
Since the conductive type high concentration diffusion layers are formed in contact with each other, the device can be integrated. As a result,
The operating voltage can be lowered, and no problem occurs even if the junction breakdown voltage between the first and second conductivity type high concentration diffusion layers is low.

Further, the method for manufacturing a semiconductor device according to the second invention of the present application includes the method for manufacturing a semiconductor device according to the first invention.
A step of forming a non-single crystal silicon film doped with a second conductivity type impurity on the surface of a conductivity type semiconductor substrate;
After forming the insulating film, a step of selectively removing a part of the insulating film, a step of removing the exposed non-single-crystal silicon layer using the remaining first insulating film as a mask, and a step of removing the exposed non-single-crystal silicon layer on the exposed surface of the substrate. a second step of forming an insulating film; a step of diffusing impurities from the non-single crystal silicon film to form a second conductivity type high concentration diffusion layer; forming a first conductivity type high concentration diffusion layer in contact with the second conductivity type high concentration diffusion layer by ion-implanting impurities and then heat-treating the first and second insulating films; a step of converting the remaining non-single crystal silicon film into an oxide film and then removing the oxide film; a step of forming a semiconductor layer of the first conductivity type on the entire surface; A step of forming an element isolation region (which may be a first conductivity type diffusion layer or an insulating film) selectively reaching a part of the first conductivity type high concentration diffusion layer; The method is characterized by comprising a step of forming a diffusion layer constituting a semiconductor element in a semiconductor layer surrounded by a high concentration diffusion layer and an element isolation region.

According to such a method, the first and second conductivity type high concentration diffusion layers on the surface of the semiconductor substrate can be formed in a self-aligned manner, so that the second conductivity type semiconductor layer (epitaxial layer) can be formed. Previous photolithography process (PEP)
only needs to be done once. Therefore, the low voltage and
Highly integrated semiconductor devices can be manufactured with simple steps and extremely high yields.

(Embodiments of the Invention) Examples of the present invention will be described below with reference to manufacturing steps shown in FIGS. 1(a) to (i).

First, a film with a thickness of 300 to 500 is applied to the surface of the p-type silicon substrate 1.
After forming human polycrystalline silicon [12°, for example, acceleration energy 50 keV 1 dose 1X1016/α
Arsenic ions are implanted under the conditions of 2.

The ion implantation conditions are determined depending on the layer resistance value, diffusion depth, etc. of the n1 type buried layer to be finally formed. In addition,
Under the above conditions, the peak position of arsenic concentration is at substrate 1.
The impurity distribution is located at a position slightly closer to the polycrystalline silicon film 2 than the polycrystalline silicon 1lI2 boundary (as shown in FIG. 1(a)). Next, a film thickness of 450o was applied to the entire surface.
After depositing ~5,000 CvD oxide films 3, selective etching is performed only on the intended part of the element isolation region to form the openings 4.
(Illustrated in Figure (b)). Subsequently, the polycrystalline silicon 112 exposed in the opening 4 is etched by reactive ion etching (RIE) as the remaining CVOm compound 11, and the arsenic concentration is further reduced to about 1.
The substrate 1 is etched to a region where the etching ratio is 0''/a13 or less (as shown in FIG. 2C).

Next, thermal oxidation is performed at 1000° C., and the surface of the substrate 1 exposed in the opening 4 is thermally oxidized to a thickness of 1000° C. Form A5. Subsequently, in a nitrogen atmosphere, 120
Heat treatment is performed at 0°C for 4 to 6 hours to form polycrystalline silicon film 2.
Arsenic is diffused from the wafer to form an n+ type buried layer 6 (as shown in FIG. 4(d)).

Subsequently, using the remaining CVD oxide film 3 as a mask, the substrate 1 is exposed to an acceleration energy of 50 keV and a dose of 3.4 through thermal oxidation 115 formed in the opening.
Boron is ion-implanted under the conditions of X 10''/3'' to form a boron ion-implanted layer 7 (as shown in FIG. 3(e)).

Subsequently, annealing is performed at 1200 DEG C. for 20 to 30 minutes in a nitrogen atmosphere to activate the boron ion implantation layer 7 and form a p++ buried layer 8 that will become a part of the element isolation region. Subsequently, the remaining CvD oxide film 3 and thermal oxide film 5 are etched (as shown in FIG. 3(f)).

Next, hydrogen combustion oxidation is performed at 1000° C. in an oxidizing atmosphere to completely convert the remaining polycrystalline silicon film 2 into an oxide film. At this time, a thin oxide film is also formed on the exposed surface of the substrate 1. Subsequently, all of the oxide film formed on the surface of the substrate 1 is removed (as shown in FIG. 3(a)). Next, the entire surface of the substrate 1 is coated with a thickness of 4 to 6 layers and a specific resistance of 1.5 to 1.
An n-type epitaxial layer 9 of 2Ω·C scrap is formed. At this time, the impurities in the n1 type buried layer 6 and the p+ type buried layer 8 are epitaxial! It also spreads to the 19th side. Furthermore, the final n++ buried layer 6 has a diffusion depth of about 1.5 to 2
The layer resistance value is 40 to 50 Ω·σ, the diffusion depth of the n1 type buried layer 8 is approximately 2 tan, and the layer resistance value is 170 to 200 Ω·1.

The layer resistance value of this p+ type buried layer 8 is set to a considerably high resistance value compared to the layer resistance value of the conventional p'' type buried layer, that is, several tens of Ω/hole (see figure (h)). ).Continued,
Boron is selectively diffused into a part of the epitaxial layer 9 to form a p-type diffusion layer 10 that constitutes the element isolation am together with the n3-type buried layer 8. . At the same time, a p-type base region 11 is formed. Next, epitaxial layer 9
By selectively diffusing arsenic into a part of n++
An emitter region 12 and an n4 type collector extraction region 13 are formed, and a bipolar semiconductor device is manufactured (as shown in the same figure).
(Illustrated).

In the bipolar semiconductor device shown in FIG. 1(i), n4
Since the '-type buried layer 6 and the p+-type buried layer 8 are formed in contact with each other, high integration of the device can be achieved. As a result, the operating voltage can be lowered, so that no problem occurs even if the junction breakdown voltage between the n0 type buried layer 6 and the p+ type buried layer 8 is low.

Furthermore, in the above method, the pattern of the polycrystalline silicon film 2 formed in the step of FIG. 1(C) becomes a diffusion source for the n4'' type buried layer 6 in the step of FIG. 1(d), and The n++ buried layer 6 and the p+ type buried layer 8 are used as masks for boron ion implantation in the process shown in FIG. 1(e).
can be formed in a self-consistent manner. therefore,
Prior to the formation of the epitaxial layer 9, the photolithography process (PEP) was performed in the CvDl conversion process 113 in the process shown in FIG.
It is used only for etching, and PEP can be reduced by one time compared to the conventional method. Therefore, the process can be made simpler than in the past, and the yield can also be improved. Furthermore, since the element isolation region is formed by diffusion from both the upper and lower directions of the epitaxial layer 9, the diffusion time can naturally be reduced.

In addition, the area of the element isolation region itself is reduced, making it easy to achieve high integration of elements.

In the above embodiment, the element isolation region is formed by a p+ type buried layer 8.
However, instead of the p-type diffusion layer 10, an oxide film formed by, for example, a selective oxidation method may be used.

Further, in the above embodiment, a bipolar type semiconductor element is formed in the epitaxial layer, but the present invention is not limited to this, and bipolar type and MOS type semiconductor elements may be mixed.

〔Effect of the invention〕

As detailed above, according to the present invention, it has a high degree of integration,
Furthermore, it is possible to provide a semiconductor device that operates at low voltage and includes a bipolar type or a mixture of bipolar and MOS type elements, and a method for manufacturing such a semiconductor device using extremely simple steps.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(i) are cross-sectional views showing manufacturing steps for obtaining a bipolar semiconductor device in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Polycrystalline silicon substrate, 3... CVOAA coating, 4... Opening part, 5...
Thermal oxide film, 6... n0 type buried layer, 7... boron ion implantation layer, 8... double type buried layer, 9... n type epitaxial layer, 10... p type diffusion layer (element separation area)
, 11...p-type base region, 12...n0-type emitter region, 13...n1-type collector extraction region.

Claims (4)

[Claims] (1) A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate, and a first conductivity type semiconductor layer formed in contact with each other in a boundary region between the semiconductor substrate and the semiconductor layer.
and a high concentration diffusion layer of a second conductivity type, an element isolation region formed to reach the high concentration diffusion layer of the first conductivity type from the surface of the semiconductor layer, and the high concentration diffusion layer of the first conductivity type; What is claimed is: 1. A semiconductor device comprising: a diffusion layer constituting a semiconductor element formed within a semiconductor layer surrounded by an element isolation region. (2) forming a non-single crystal silicon film doped with second conductivity type impurities on the surface of the first conductivity type semiconductor substrate;
After forming the first insulating film on the entire surface, a step of selectively removing a part of the first insulating film, a step of removing the exposed non-single crystal silicon film using the remaining first insulating film as a mask, and a step of removing the exposed non-single-crystal silicon film using the remaining first insulating film as a mask. forming a second insulating film on the surface of the substrate; diffusing impurities from the non-single crystal silicon film to form a second conductivity type high concentration diffusion layer; After ion-implanting impurities of the first conductivity type,
forming a first conductivity type high concentration diffusion layer in contact with the second conductivity type high concentration diffusion layer by heat treatment;
a step of removing the first and second insulating films, a step of converting the remaining non-single crystal silicon film into an oxide film and then removing the oxide film, and a step of removing a semiconductor layer of a first conductivity type over the entire surface. forming an element isolation region selectively reaching the first conductivity type high concentration diffusion layer in a part of the semiconductor layer; 1. A method of manufacturing a semiconductor device, comprising the step of forming a diffusion layer constituting a semiconductor element in a semiconductor layer surrounded by a region. (3) A second layer is added to the non-single-crystal silicon film by ion implantation.
3. The method of manufacturing a semiconductor device according to claim 2, wherein a conductive type impurity is added. (4) The method of manufacturing a semiconductor device according to claim 2 or 3, wherein arsenic is used as the second conductivity type impurity, and boron is used as the first conductivity type impurity.