JPH0555593A - Manufacture of insulated-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a vertical MOSFET with reduced input capacitance, feedback capacitance, and ON resistance and an improved reliability by a simple manufacturing process. CONSTITUTION:A pattern of a phosphor glass film 6 is formed at a drain region on a gate insulation film 4 on a surface of a semiconductor substrate 1, a polycrystalline silicon film gate electrode 5 is formed so that the pattern of the phosphor glass film 6 is covered, a P-type impurity is diffused for forming a channel diffusion region 2, and at the same time an N-type impurity is diffused from the phosphor glass film 6, thus forming a high-concentration diffusion layer 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor, and more particularly to a vertical insulated gate field effect transistor suitable for power MOSFETs and the like.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view of a conventional vertical insulated gate field effect transistor (hereinafter referred to as MOSFET). Reference numeral 1 is an N-type semiconductor substrate, which is a MOSFET
Forming a drain region of. Reference numeral 2 is a P ⁺ type vertical MO
This is the channel diffusion region of the SFET. Reference numeral 3 is an N ⁺ type diffusion layer provided in the channel diffusion region 2 and forms a source diffusion region. Reference numeral 4 is a gate insulating film made of a thin oxide film, reference numeral 5 is a gate electrode made of a polycrystalline silicon film, and when a voltage is applied to the gate electrode 5, the source diffusion region 3 and the drain region are separated from each other. Conduction is controlled through the gate insulating film 4. Reference numeral 9 is an interlayer insulating film made of an oxide film or the like, and reference numeral 10 is a metal electrode such as an aluminum film, which forms a source electrode or the like of the MOSFET. Such a vertical MOSFET has a structure suitable for a power MOSFET handling a high breakdown voltage and a large current.

However, the M having the structure shown in FIG.
In the OSFET, since the gate electrode 5 directly faces the semiconductor substrate 1, which is the drain region, through the thin gate insulating film 4, the feedback capacitance between the gate and drain of the MOSFET and the input capacitance between the gate and source become large, There is a problem that the switching speed becomes slow. Further, since the drain region is a low-concentration N-type semiconductor substrate, there is a problem that the ON resistance becomes large in the power MOSFET. To solve this problem, the gate insulating film 4 is formed thick on the drain region to reduce the capacitance, and the drain region directly below the thick gate insulating film is increased in concentration to reduce the ON resistance. However, JP-A-63-21876 and JP-A-2-37
No. 777, etc.

[0004]

As described above, in the conventional vertical MOSFET structure shown in FIG. 2, since the gate electrode and the drain region directly face each other through the thin insulating film, the input capacitance of the MOSFET is reduced. However, there is a problem that the feedback capacitance becomes large, and a problem that the ON resistance in the drain region becomes large. In addition, the above-mentioned JP-A-63-2
The MOSFETs disclosed in Japanese Patent No. 1876 and Japanese Patent Laid-Open No. 2-37777 have a problem that the manufacturing process is complicated.

[0005]

In order to solve the above problems, the present invention provides a method of manufacturing a vertical MOSFET, including a step of forming a gate insulating film on the surface of a semiconductor substrate, and a phosphorus glass film on the gate insulating film. And forming a pattern on the drain region of the semiconductor substrate by photoetching, and by depositing a polycrystalline silicon film on the phosphor glass film and by photoetching so as to cover the pattern of the phosphor glass film. Forming a gate electrode; depositing a P-type impurity using the gate electrode made of the polycrystalline silicon film as a mask; heat-treating the P-type impurity to form a channel diffusion region; A step of diffusing phosphorus from the film to form a high-concentration diffusion layer in the drain region, and a gate electrode and a photo resist made of the polycrystalline silicon film. It was composed of a step of forming a source diffusion region by diffusing N-type impurity as Makusu, and forming a metal electrode provided contact openings.

[0006]

In the present invention, since the phosphor glass film which is a thick insulating film is provided on the semiconductor substrate 1 which forms the drain region under the gate electrode, the input capacitance and the feedback capacitance of the MOSFET are shown in FIG. Significantly reduced compared to the conventional structure shown. Further, since the N ⁺ type high-concentration diffusion layer is formed in the drain region of the semiconductor substrate 1 from the phosphorus glass film, the MOSF
ON resistance of ET decreases. Since the thick insulating film is formed by using the phosphor glass film, a simple manufacturing process for realizing the above structure was realized.

[0007]

EXAMPLE First, a semiconductor substrate 1 having an N type epitaxial layer on an N ⁺ type substrate was prepared, and a P type deep diffusion layer serving as a diffusion layer for separating cells and a guard ring diffusion layer was prepared. Form an area. This grows an oxide film by thermal oxidation, opens it by photoetching, deposits or ion-implants boron, and forms a diffusion layer by heat treatment. Next, an N ⁺ type deep diffusion layer to be an annular diffusion layer at the chip end is formed. This opens the oxide film by photoetching,
A diffusion layer is formed by depositing phosphorus and driving it in. Then, the oxide film in the cell portion of the MOSFET is opened by photoetching.

FIG. 2 is a sectional view of an embodiment of the manufacturing process of the MOSFET of the present invention. (A) is a cross-sectional view after forming a phosphorus glass film pattern. First, the gate oxide film 6 is formed on the entire surface of the cell portion by thermal oxidation. Then, a phosphorus glass film is deposited on the entire surface of the semiconductor substrate by chemical vapor deposition (CV).
At D), it is applied. Then, a photoresist is applied, and a phosphorus glass film is patterned on the drain region by photoetching to form a phosphorus glass film 6 on the drain region.

FIG. 3B is a cross-sectional view after depositing a polycrystalline silicon film on the phosphor glass film 6 and forming the gate electrode 5 by photoetching so as to cover the pattern of the phosphor glass film 6. First, a polycrystalline silicon film is deposited on the entire surface of a semiconductor substrate by CVD. Then, a photoresist is applied, and a pattern of the gate electrode 5 is formed so as to cover the phosphorus glass film 6 patterned by photoetching.

FIG. 1C is a sectional view after the MOSFET is completed. Channel diffusion region 2 and N ⁺ which are P-type diffusion layers
The source diffusion region 3 which is the type diffusion layer is doubled to the gate electrode 5
Is used as a mask to form a self-aligned diffusion.
In this diffusion, first, boron is ion-implanted using the gate electrode as a mask and heat treatment is performed to form the channel diffusion region 2 as a diffusion layer. With the heat treatment at this time, through the gate insulating film 4 which is an oxide film thinner than the phosphorus glass film 6,
Phosphorus is diffused into the semiconductor substrate 1 which is the drain region to form the high concentration diffusion layer 11. Next, using the resist and the gate electrode as a mask, the source diffusion region 3 is similarly formed by ion implantation and diffusion of phosphorus. Then, a thick phosphorus-doped oxide film is grown on the entire surface of the semiconductor substrate by CVD. The phosphorus-doped oxide film (PSG) serves as an interlayer insulating film 9 between the gate electrode 5 made of polycrystalline silicon and the metal electrode such as aluminum to be wired thereon. Then, a contact pattern such as a contact to the source diffusion region is opened by photoetching, an aluminum film is formed by aluminum vapor deposition, and a metal electrode 10 or the like of the aluminum film is formed by photoetching to complete the MOSFET.

[0011]

According to the present invention, since the thick phosphorus glass film is provided on the semiconductor substrate 1 forming the drain region, the input capacitance and the feedback capacitance of the MOSFET are reduced. Further, since the N ⁺ type high-concentration diffusion layer is formed in the drain region of the semiconductor substrate 1 from the phosphor glass film, the ON resistance of the MOSFET is reduced. Since the thick gate insulating film is formed by using the phosphorus glass film, a simple manufacturing process for realizing the above structure was realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a method for manufacturing an insulated gate field effect transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional insulated gate field effect transistor.

Claims (1)

[Claims] 1. A step of forming a gate insulating film on the surface of a semiconductor substrate, a step of forming a phosphorus glass film on the gate insulating film, and forming a pattern on the drain region of the semiconductor substrate by photoetching, Depositing a polycrystal silicon film on the phosphor glass film, and forming a gate electrode by photoetching so as to cover the pattern of the phosphor glass film; and using the gate electrode made of the polycrystal silicon film as a mask, a P-type impurity And a step of depositing the P-type impurity by heat treatment to form a channel diffusion region, and diffusing phosphorus from the phosphorus glass film to form a high-concentration diffusion layer in the drain region. Forming a source diffusion region by diffusing N-type impurities using the gate electrode and the photoresist made of a mask as masks; And a step of forming a metal electrode to provide a contact opening, and a method of manufacturing an insulated gate field effect transistor.