JPH06326316A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the passing-through of impurities when P-type impurities are introduced into a gate polysilicon and improve the characteristics and reliablility of a semiconductor device. CONSTITUTION:In manufacturing a semiconductor device made of a P-type gate polysilicon 5, a gate oxide film 3 is formed on one conductivity type expitaxial layer 2 which is grown on the same conductivity type semiconductor substrate 1 and an N-type impurity layer is formed on the surface of the gate oxide film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a P-type polysilicon gate.

[0002]

2. Description of the Related Art As one of semiconductor devices, an insulated gate field effect transistor (so-called MOS transistor) is used.
Are widely used, and there are a horizontal type in which the drain and the source are on the same surface of the substrate and a vertical type in which the drain and the source are on the opposite side of the substrate. The former is used as a circuit element such as an LSI, and the latter is used as a switching element because a large current can be obtained.

FIG. 4 shows each manufacturing step of a method of manufacturing a vertical insulated gate field effect transistor as an example of a conventional semiconductor device.

In the manufacturing process shown in FIG. 4A, a gate oxide film 23 is formed on the surface of the P type epitaxial layer 22 on the P type substrate 21. Next, after forming the gate polysilicon 25 on the gate oxide film 23, a window is formed by using the photolithography technique. After the gate polysilicon 25 and the gate oxide film 23 are etched, the N-type base layer 26 is formed using the gate polysilicon 25 as a mask.
To form.

Subsequently, in a manufacturing process shown in FIG. 4B, the N-type base layer 26 is exposed to N as a mask.
After forming the ⁺ layer 27, the P-type source layer 28 is formed by ion implantation using the gate polysilicon 25 and the resist as a mask, and at the same time, P-type impurities are introduced into the gate polysilicon 25. After that, the interlayer insulating film 2 is further formed on the entire surface.
9 is formed, a window is opened by using a photolithography technique, and then an aluminum electrode 30 and a back surface electrode 31 are formed.

By the way, in the above manufacturing method, when the P-type impurity in the gate polysilicon 25 is introduced, the P-type impurity penetrates into the P-type substrate 21. Therefore, in order to prevent this, the conventional source layer 28 is formed at a low temperature. A method of processing or introducing an N-type impurity into the gate polysilicon 25 is adopted. For example, JP-A-63-4886
In the invention disclosed in No. 5, polysilicon containing N-type impurities is attached for the purpose of preventing penetration of implanted impurities during ion implantation. Also, JP-A-58-201369
In No. 6, a method is adopted in which the grain size of polysilicon is increased by using laser annealing or the like without introducing impurities into polysilicon.

[0007]

However, if the former low-temperature treatment is performed, the concentration of P-type impurities in the gate polysilicon becomes non-uniform, which causes characteristic fluctuations and lowers reliability and pushes in the source. Was limited, and it was difficult to improve the characteristics.

According to the experiments conducted by the inventors of the present invention, the latter method is applied to the gate polysilicon in advance of 10 ¹³
Even if a heat treatment is performed at 1000 ° C or higher after doping phosphorus of about cm ^-2 , if the heat treatment after introducing the P-type impurity is 1000 ° C or higher, P-type impurity penetration occurs, and laser annealing or the like is sufficient. Turned out not to be.

The present invention has been made in view of the above points, and prevents penetration of impurities when introducing P-type impurities into gate polysilicon in manufacturing an insulated gate semiconductor device, thereby improving characteristics and reliability. The purpose is to improve.

[0010]

In order to solve the above problems, the present invention is a method for manufacturing an insulated gate type semiconductor device in which gate polysilicon is P type, which is grown on a semiconductor substrate having one conductivity type. A feature is that a gate oxide film is formed on an epitaxial layer of the same conductivity type, and an N-type impurity layer is formed on the surface of the gate oxide film.

[0011]

The N-type impurity layer formed on the surface of the gate oxide film prevents the P-type impurity from penetrating.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing each manufacturing step of a method of manufacturing a semiconductor device according to the present invention. In the embodiment shown in FIG. 1, the method of the present invention is applied to a vertical insulating field effect transistor.

In the manufacturing process shown in FIG. 1A, a gate oxide film 3 is formed on the surface of the P type epitaxial layer 2 formed on the P type substrate 1. N-type impurities 4 are introduced into the surface of the oxide film 3. As the introduction method at this time, an ion implantation technique, a lamp annealing method, or the like is conceivable, but the method is not particularly limited as long as N-type impurities can be introduced into the surface of the oxide film.

Next, in the manufacturing process shown in FIG.
A gate polysilicon 5 is formed on the oxide film 3, a window is opened using a photolithography technique, and then an N-type base layer 6 is formed using the gate polysilicon 5 as a mask.
Next, after forming the N ⁺ layer 7 in the N-type base layer 6, the P-type source layer 8 is formed using the gate polysilicon 5 as a mask.

Subsequently, in a manufacturing process shown in FIG. 1C, an interlayer insulating film 9 is formed on the entire surface, a window is opened using a photolithography technique, and then an aluminum electrode 10 and a back surface electrode 11 are formed. .

FIG. 2 is a schematic cross-sectional view showing, in an enlarged manner, an N-type impurity introduced portion of the transistor thus manufactured.

As can be seen from FIG. 2, N in the oxide film 3 is
The type impurity layer 12 is shown. The N-type impurities (shown by diagonal lines) introduced near the interface of the oxide film 3 with the gate polysilicon 5 diffuse into the gate polysilicon 5 by the subsequent heat treatment, and finally, the gate polysilicon 5 and the oxide are oxidized. An N-type impurity layer is formed at the interface between the film 3 and the gate polysilicon 5. This can prevent P-type impurities introduced into gate polysilicon 5 from penetrating through gate polysilicon 5 in the subsequent step. The higher the concentration of the N-type impurity, the better the penetration of the P-type impurity can be prevented. However, according to the experiment, about 10 ¹⁴ to 10 ¹⁵ cm ⁻² is suitable.

As a result, it becomes possible to increase the temperature and duration of the indentation performed in the step after introducing the P-type impurity into the gate polysilicon 5. According to the experiments by the inventors,
This pushing process is performed at 900 ℃ for 15 minutes to 9 minutes.
When the temperature was set to 00 ° C. for 90 minutes, the on-resistance (the resistance between the drain and the source when a certain voltage was applied to the gate) was improved by about 10%. Also, regarding the characteristic variation that is an index of reliability, the rate of change in transmission admittance (gm or YFS) immediately after manufacturing and after 1000 hours is -25 of the conventional level.
% (Average) to -9.2% (average).

FIG. 3 shows another embodiment of the method of manufacturing a semiconductor device according to the present invention.

In the embodiment shown in FIG. 3, the method of the present invention is applied to a lateral insulated gate field effect transistor, 3 is an oxide film, 5 is gate polysilicon, 9 is an interlayer insulating layer, and 13 is a drain electrode. , 14 is a source electrode, 15 is an N-type substrate, 16 is a P-type source layer, 17 is a P-type drain layer, and 19 is an element isolation oxide film. Although the manufacturing process is well known, it is not shown here, but the introduction of N-type impurities into the oxide film 3 is the same as in the first embodiment shown in FIG.

In the first embodiment, in the semiconductor device in which the gate polysilicon 5 is P type, gate oxidation is performed on the P conductive type epitaxial layer 2 grown on the semiconductor substrate 1 having P conductive type. The case where the film 3 is formed and the N-type impurity layer 12 is formed on the surface of the gate oxide film 3 has been described, but after the gate oxide film is formed on the N-type epitaxial layer on the N-type semiconductor substrate 1. Can be similarly applied to a method of manufacturing a semiconductor device in which P-type gate polysilicon is formed.

[0023]

As described above, according to the method of manufacturing an insulated gate semiconductor device of the present invention, the N-type oxide film is formed on the gate oxide film before introducing the P-type impurity into the gate polysilicon.
By introducing the type impurity, it is possible to suppress the penetration of the P type impurity introduced in the subsequent process, improve the on-resistance by about 10% in terms of characteristics, and reduce the characteristic variation by -25% (compared to the conventional level) in terms of reliability. The excellent effect of being able to improve from (average) to -9.2% (average) is obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing each manufacturing step of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic sectional view showing an N-type impurity introduced portion in an enlarged manner.

FIG. 3 is a cross-sectional view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing each manufacturing step of a conventional semiconductor device manufacturing method.

[Explanation of symbols]

1 P-type substrate 2 P-type epitaxial layer 3 Oxide film 4 N-type impurity 5 Gate polysilicon 6 N-type base layer 7 N ⁺ layer 8, 16 P-type source layer 9 Interlayer insulating film 10 Aluminum electrode 11 Backside electrode 12 N-type impurity Layer 13 Drain electrode 14 Source electrode 15 N-type substrate 17 P-type drain layer

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device in which gate polysilicon is P-type, wherein a gate oxide film is formed on an epitaxial layer of the same conductivity type grown on a semiconductor substrate having one conductivity type, A method of manufacturing a semiconductor device, comprising forming an N-type impurity layer on the surface of a gate oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is P-type.