JPH0444432B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a vertical MOSFET.

Conventional configurations and their problems In recent years, vertical MOSFETs have begun to be used for power applications. Among them, double diffused vertical type
MOSFETs (hereinafter referred to as VDMOSFETs) are the most widely manufactured.

FIG. 1 shows the cross-sectional structure of a conventional n-channel VDMOSFET.

This n-channel VDMOSFET is formed in an n ^- epitaxial layer 2 on an n ⁺ semiconductor substrate 1,
Current flows from the lower drain 1 to the upper source region 4 through a channel formed by lateral diffusion of the back gate layer 3. Further, during reverse bias, a depletion layer expands in the n ^- buffer layer 2 to support the applied voltage. The source electrode 7 is often etched into the substrate to a depth that penetrates the upper source region 4 and reaches the lower back gate layer 3 so that it has the same potential as the back gate layer 3, and an electrical connection is made to the etched portion. . However, when etching, it is difficult to control the etching, and when etching is performed with the goal of completely penetrating the source region 4, the back gate layer 3 is often etched more than necessary, so-called over-etching. A leakage current may occur between the two. Furthermore, if a deep, highly-concentrated back gate layer 3 is formed in advance so as not to be affected by such overetching, the number of mask alignment steps increases. In FIG. 1, 5 is an oxide film and 6 is a gate electrode.

Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a vertical MOSFET that can form a step-like deep region that will become a highly doped back gate layer before performing diffusion without increasing the number of steps. It is something.

SUMMARY OF THE INVENTION To achieve this objective, the present invention provides a highly doped backgate layer by using multiple selective etching steps in a single mask step, before double diffusion is performed. This method includes a step of forming the step in advance in a stepwise manner in a self-aligned manner.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows the vertical type of the present invention.
FIG. 2 is a cross-sectional view of the process order showing an example of a method for manufacturing a MOFET.

First, an n ^- /n ⁺ epitaxial silicon substrate,
That is, the oxide film 13 is grown to a thickness of 1000 Å on the n ^- epitaxial layer 12 on the n ⁺ silicon substrate 11, and the polysilicon film 14 is depressurized to a thickness of 4000 Å.
After growing using CVD and diffusing phosphorus into the polysilicon film 14, a Si ₃ N ₄ film 15 is grown to a thickness of 2000 Å by low pressure CVD (FIG. 2a).
Next, the three layers of the Si ₃ N ₄ film 15, the polysilicon film 14, and the oxide film 13 are sequentially etched using, for example, reactive ion etching to form a first opening that passes through these three layers. Through this opening, boron is ion-implanted at a dose of, for example, 1×10 ¹⁵ at 100 KeV, and heat treated for annealing and diffusion to form a diffusion layer 16 (FIG. 2b). Thereafter, while leaving the Si ₃ N ₄ film 15, only the polysilicon film 14 is etched with, for example, an ethylene diamine solution at about 100°C, so that the side surface is etched from the first opening, and the second opening is etched. (Fig. 2c).

After removing the Si ₃ N ₄ film 15 with hot phosphoric acid or the like, the P-type back gate layer 17 is widened in the lateral direction by, for example, boron ion implantation at a dose of 7×10 ¹³ at 100 KeV. Form a back gate layer of
The source region 18 is formed by ion implantation at 10 ¹³ and 40 KeV and by a predetermined heat treatment. Incidentally, during this heat treatment process, an oxide film 13 is grown to a thickness of about 1000 Å on the exposed portion of the substrate (FIG. 2d).

Next, an opening is formed in the oxide film 13 again, and through this opening, the source region 18 is etched using a reactive ion etching method or the like until it reaches the P ⁺ diffusion layer 17, thereby forming a third opening. A hole is formed, Al is formed in this third hole by sputtering to provide a source electrode 19, and the n ⁺ region 1
8 and P ⁺ region 16 at the same time (FIG. 2e).

As a result, the n ⁺ substrate 11 is used as a drain region,
A VDMOSFET is completed in which the n ^- epitaxial layer 12 is used as a buffer region, the n ⁺ region 18 is used as a source region, and the polysilicon film 14 is used as a gate.

The VDMOSFET configured as above is
By etching the diffusion region itself on the substrate, the source region 18 and back gate region 17 are electrically connected at the same time. In this case, even if the etching is slightly deeper,
Since the P ⁺ layer 17 has the deep diffusion region 16, no electrical short circuit occurs with the drain side of the n ^- epitaxial layer 12. Further, since the source region and the back gate layer are each formed in a self-aligned manner by a single mask process, there is no need to increase the number of process steps.

Although this embodiment describes an n-channel VDMOSFET, it goes without saying that the same manufacturing process can be applied to vertical VMOSFETs and P-channel VDMOSFETs.

Effects of the Invention As described above, according to the present invention, a step-like deep diffusion region is self-aligned in the back gate layer by a single mask process and a plurality of selective etching processes before double diffusion is performed. It is possible to manufacture a vertical MOSFET that is less prone to shorting between the source and drain without increasing the number of steps.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional VDMOSFET, Figure 2 is a cross-sectional view of a conventional VDMOSFET.
Figures a to e are cross-sectional views in the order of steps of an embodiment of the present invention. 11... n ⁺ layer (drain region), 12... n ^- epitaxial layer (buffer region), 13... oxide film, 14... polysilicon film (gate electrode), 1
5...Si ₃ N ₄ film, 16...P ⁺ diffusion layer, 17...P
Type layer (back gate region), 18...n ⁺ layer (source region), 19...Al electrode (source electrode).

Claims (1)

[Claims] 1 Step of sequentially forming three layers of an oxide film, a conductive film, and an insulating film on a semiconductor substrate of one conductivity type, and forming a first hole penetrating the oxide film, the conductive film, and the insulating film. a step of introducing an impurity of an opposite conductivity type into the semiconductor substrate through the first opening to form a first region; and a step of side etching the conductive film to increase the diameter of the opening in the conductive film. a step of forming a second opening to make the diameter larger than the diameter of the first region; a step of removing the insulating film; and a step of introducing an impurity of an opposite conductivity type into the semiconductor substrate through the second opening. introducing an impurity having the same conductivity type as the semiconductor substrate into the first region and the second region, forming a second region having a diameter larger than the first region; forming a third region smaller in diameter than the second region; and a third region penetrating the third region to reach the second region.
and forming an electrode in contact with each of the second and third regions by providing a metal layer in the third opening.
MOSFET manufacturing method.