JPH11224945A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having high pressure resistance and a high operating speed. SOLUTION: A semiconductor device has a semiconductor subsrate on which is conductive source region 13 and a conductive drain region 14 are formed, a gate electrode 18 formed on the surface of the substrate via an oxide film 16 which is thicker than the other portion and an oxide film 17, conductive diffused layers 15a, 15b having a lightly doped and formed in a region between the source region 13 and the drain region 14 and adjacent to the drain region 14, in which a portion interposed between the diffusion layers of the oxide film and the gate electrode 18 includes a thicker portion and the diffusion layers have two or more regions having different concentrations of impurities.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device used as a transistor.

[0002]

2. Description of the Related Art In a MOS transistor, a gate electrode is formed on a semiconductor substrate surface via an insulating film, and a voltage is applied to the gate electrode to induce a channel on the semiconductor surface. Conventionally, various measures have been taken to improve the breakdown voltage of this MOS transistor. As one of such measures, in order to reduce the electric field concentration near the surface of the drain region, which is one of the causes of the breakdown voltage, an impurity diffusion layer having a lower concentration than the drain region is provided in the region adjacent to the drain region. It has been proposed to provide The structure of this conventional MOS transistor will be described with reference to a cross-sectional view of FIG. 17 taking an n-channel transistor using a p-type substrate as an example. A p-type well 52 is formed along one main surface of the p-type semiconductor substrate 51, and a source region 53 and a drain region 54 are formed in the p-type well 52 by diffusing an n-type impurity. . Further, an n-type diffusion layer 55 is formed in the well 52 in a region adjacent to the drain region 54. A gate electrode 58 is formed via the oxide films 56 and 57 on the surface of the substrate on which the source region, the drain region, the diffusion layer and the like have been formed, thus forming a MOS transistor. In such a semiconductor device, the electric field concentration generated when a drain voltage is applied can be reduced by depletion of the diffusion layer 55.

[0003]

In the MOS transistor, since the channel region is formed on the surface of the diffusion layer 55, the on-resistance of the channel is determined by the resistance of the diffusion layer 55. In the conventional MOS transistor as described above, generally, the higher the length of the diffusion layer 55 and the lower the impurity concentration of the diffusion layer 55, the higher the breakdown voltage can be achieved. However, an increase in the length of the diffusion layer and a decrease in the impurity concentration tend to increase the resistance of the diffusion layer and, consequently, increase the on-resistance of the channel, thereby lowering the operation speed of the transistor. It was difficult to achieve both.

An object of the present invention is to provide a semiconductor device having a high withstand voltage and a high operation speed.

[0005]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor device in which a source region and a drain region of the same conductivity type are formed on a surface of a semiconductor substrate. A gate electrode is also formed via an oxide film formed as a thick film, and the conductive region having a lower impurity concentration than the drain region is provided between the source region and the drain region in contact with the drain region. Type diffusion layer is formed, a portion of the oxide film interposed between the diffusion layer and the gate electrode includes a thick film portion, and the diffusion layer has two or more regions having different impurity concentrations. It is characterized by the following. Further, in the semiconductor device, it is preferable that the diffusion layer has a region including an end on the source region side and a region having a higher impurity concentration than this region.

[0006] With this configuration, while a region having a low impurity concentration is formed in the diffusion layer, a high withstand voltage characteristic is ensured, and the impurity concentration in the other region is adjusted to a relatively high level, whereby the channel of the channel is formed. Since the on-resistance can be reduced, a semiconductor device having both high withstand voltage and high-speed operation can be obtained.

[0007]

(First Embodiment) FIGS. 1 to 4
1 is a sectional view showing an example of the structure of a semiconductor device of the present invention.
You. In a p-type well 12 formed in a semiconductor substrate 11, n
Source region 13 and drain region 14 are formed.
ing. Usually, the surface impurity concentration of the well is 10^Fifteen-10
¹⁶cm ^-3And the diffusion depth is about 3-20 μm.
The surface impurity concentration of the source region and the drain region is 10¹⁹
-10²⁰cm^-3Degree, diffusion depth is about 0.2-1.5μm
Degrees.

An n-type diffusion layer 15 having an impurity concentration lower than that of the drain region is formed in a region in contact with the drain region 14 and the surface of the substrate 11, and the diffusion layer 15 is formed of two or more regions having different impurity concentrations, preferably Is composed of about 2 to 3 regions. Among these regions, the impurity concentration in the region including the end on the source region side is relatively low for improving the withstand voltage, and preferably the surface concentration is 10 ¹⁶ to 10 ¹⁷ cm ^−3.
Adjusted to the extent. On the other hand, the impurity concentration of the other region is preferably as high as possible within a range lower than the impurity concentration of the drain region in order to reduce the on-resistance of the channel. The diffusion layer is formed, for example, as shown in FIG. 1 (impurity concentration 15a> 15b) or FIG. 2 (impurity concentration 15a>
15b> 15c), the impurity concentration is formed so as to decrease stepwise or continuously in the direction from the drain region side to the source region side (the length direction of the diffusion layer). Further, since the channel is formed on the surface of the substrate, as shown in FIG. 3, even if the high impurity concentration region 15a formed near the drain region exists only in the shallow region of the substrate, The same effect as in the example shown in FIG. 1 can be obtained. Further, as shown in FIG. 4, a diffusion layer may also be formed on the source region side to obtain a semiconductor device having a symmetrical structure. The length of the diffusion layer is about 2 to 6 μm,
An appropriate diffusion depth is about 0.3 to 2 μm.

Further, a gate electrode 18 is formed on the surface of the substrate 11 on which the source region 13, the drain region 14, the diffusion layer 15 and the like are formed as described above via the oxide films 16 and 17, thereby forming a semiconductor device. . The electric field concentration near the surface of the drain region, which is one of the causes of the breakdown voltage, is caused by the presence of the gate electrode near the drain region. Therefore, in order to sufficiently insulate the drain region from the gate electrode and reliably improve the withstand voltage, the thickness of a portion of the oxide film formed under the gate electrode which is above at least a part of the drain region and the diffusion layer Is large, preferably 500 to 800 nm. Further, by forming the gate electrode so as not to be above the drain region and the diffusion layer, the gate electrode and the drain region can be sufficiently insulated.

FIGS. 5 to 9 are process diagrams illustrating an example of a method of manufacturing the semiconductor device shown in FIG. Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described with reference to these drawings.

First, a p-type or n-type silicon substrate 11
Then, a p-type impurity such as boron is ion-implanted to form a p-type well 12. An oxide film 30 having a thickness of about 30 nm is grown on the surface of the well 12 by thermal oxidation, and a silicon nitride film 3 having a thickness of about 120 nm is formed by low-pressure CVD.
Grow one. The silicon nitride film 31 is patterned by dry etching, and a portion of the silicon oxide film 31 where a thick oxide film is to be formed in a subsequent oxidation step (step shown in FIG. 8) is removed (FIG. 5).

N-type diffusion layers (15a and 15b in FIG. 1) are formed by ion implantation of impurities (FIGS. 6 and 7). By performing this ion implantation in multiple stages, a plurality of regions having different impurity concentrations are formed in the diffusion layer.

First, a resist 32a is patterned so that impurity ions are implanted only into a portion of the diffusion layer which becomes a high concentration region (15a in FIG. 1), and then n-type impurity ions are implanted (FIG. 6). This first ion implantation
For example, using phosphorus ions, the accelerating voltage is 50 keV,
The dose is set to about 5 × 10 ¹² cm ⁻² . Next, the resist 32a is removed, and n-type impurity ions are implanted into the entire region (15a and 15b in FIG. 1) where the diffusion layer is to be formed (FIG. 7). The second ion implantation is performed using, for example, phosphorus ions at an acceleration voltage of 50 keV and a dose of about 2 × 10 ¹² cm ⁻² . Note that the order of performing the first ion implantation and the second ion implantation is not particularly limited.

Further, as another method of forming the n-type diffusion layer,
A step of ion-implanting a p-type impurity only into a portion to be a low concentration region (15b in FIG. 1);
And a step of ion-implanting a type impurity. In this case, the p-type impurity concentration partially implanted is
It is necessary to lower the concentration of the n-type impurity implanted in the entire region.
0 keV, dose amount 3 × 10 ¹² cm ^-2 , n
Ion implantation of type impurities is performed with an acceleration voltage of 50 keV and a dose of 6 × 10 ¹² cm ⁻² . The order in which the above steps are performed is not particularly limited. However, it is preferable that the p-type impurity is implanted first and the n-type impurity is implanted afterward, because the stability of the impurity distribution near the diffusion layer surface is excellent. Therefore, it is preferable.

By the above-described two-stage ion implantation, a diffusion layer composed of two regions having different impurity concentrations is formed. When the diffusion layer is formed of a larger number of regions, the same resist forming step and ion implantation step as described above may be repeated as many times as necessary.

After all the ions are implanted into the diffusion layer, a thick oxide film portion 16 is formed by thermal oxidation. At this time, since the previously formed silicon nitride film 31 serves as a mask, only the upper part of the diffusion layer can be oxidized. The thickness of the thick film portion 16 of the oxide film is suitably about 500 to 800 nm. After the thermal oxidation, the silicon nitride film 31 is removed (FIG. 8).

The oxide film 30 is removed except for the portion that will become the gate oxide film 17, and, for example, C
The gate electrode 18 is formed by patterning the polycrystalline silicon deposited by the VD method. The gate electrode may have a bar shape or a ring shape in plan view. Further, ions of an n-type impurity are implanted to form a source region 13 and a drain region 14 (FIG. 9). This ion implantation is performed, for example, at an acceleration voltage of 50 keV and a dose of 5 × 10
Perform at ¹⁵ cm ^-2 . In addition, necessary members such as a passivation film and metal wiring are formed to manufacture the semiconductor device of the present invention.

When the characteristics of the semiconductor device of the present invention as described above are compared with those of a conventional semiconductor device of the same size (semiconductor device having the structure shown in FIG. 17), the on-resistance of the channel is about The breakdown voltage was about 20% higher when the on-resistance of the channel was made equivalent by 30%.
As described above, the semiconductor device of the present invention can reduce the on-resistance of the channel while maintaining the high withstand voltage characteristics.

In this embodiment, an n-channel transistor has been described. However, if an n-type well is used and a source region, a drain region and a diffusion layer are p-type, p-type
It can be a channel transistor.

Second Embodiment The structure of the semiconductor device according to the present invention can be applied to a CMOS (complementary MOS) transistor. FIG. 10 shows such a CM.
FIG. 3 is a cross-sectional view illustrating an example of the structure of an OS transistor, in which an n-channel region is on the left and a p-channel region is on the right. As shown in FIG. 10, this CMOS transistor includes a p-channel MOS transistor (pMOS) and an n-type well in an n-type well and a p-type well formed in the same substrate.
A channel MOS transistor (nMOS) is formed, and each of the pMOS and the nMOS has the same structure as that described in the first embodiment. Also,
Regarding the manufacturing method, the same manufacturing process as that described in the first embodiment may be applied to both channel regions.

FIGS. 11 to 16 show the CMOS shown in FIG.
FIG. 4 is a process chart illustrating a preferred example of a method for manufacturing a transistor. FIGS. 11 to 16 show only the transistor portions in both channel regions.

First, a p-type or n-type silicon substrate 11
P-type impurities such as boron are ion-implanted into a predetermined region (a portion to be an n-channel region)
Form 2 Further, another predetermined region (p
Channel region) includes n such as phosphorus or arsenic.
An n-type well 122 is formed by ion implantation of a type impurity. An oxide film 130 having a thickness of about 30 nm is grown on the surfaces of the wells 112 and 122 by thermal oxidation, and a silicon nitride film 13 having a thickness of about 120 nm is formed by low-pressure CVD.
Grow one. This silicon nitride film 131 is patterned by dry etching, and is subjected to an oxidation step (FIG. 15).
In the step shown in FIG. 11, the nitride film in the portion where the thick oxide film is to be formed is removed (FIG. 11).

Due to impurity ion implantation, n-type diffusion layers (115a and 115b in FIG. 10) are formed in the n-channel portion.
And a p-type diffusion layer (125a in FIG. 10)
And 125b) are each formed. First, a portion to be a low concentration region (115b in FIG. 10) in the n-type diffusion layer;
The resist 132a is formed so that impurity ions are implanted into the high concentration region (125a in FIG. 10) in the p-type diffusion layer.
Is formed, p-type impurity ions are implanted (FIG. 12). This first ion implantation is performed, for example, by using boron ions at an acceleration voltage of 50 keV and a dose of 3 ×.
It is performed at about 10 ¹² cm ^-2 . Next, the resist 132a
Is removed, the resist 132b is patterned to prevent impurities from being implanted into the entire p-type diffusion layer formation region (125a and 125b in FIG. 10) and not into the n-type diffusion layer formation region. After that, a second p-type impurity ion implantation is performed (FIG. 13). The second ion implantation is performed, for example, by using boron ions to increase the acceleration voltage to 50.
KeV and the dose are set to about 5 × 10 ¹² cm ⁻² .
Further, after the resist 132b is removed, impurities are added to the entire region where the n-type diffusion layer is formed (115a and 11a in FIG. 10).
After the resist 132c is patterned so as to be implanted in 5b) and not into the p-type diffusion layer formation region, n-type impurity ions are implanted (FIG. 15). The amount of n-type impurity ions implanted in the third ion implantation needs to be larger than the amount of p-type impurity ions implanted in the first p-type impurity ion implantation (the step of FIG. 12). For example, when the first p-type impurity ion implantation is performed under the above-described conditions, the third ion implantation is suitably performed by implanting phosphorus ions at an acceleration voltage of 50 keV and a dose of 6 × 10 ¹² cm ^−2. .

By the three-stage ion implantation as described above,
In the n-type diffusion layer, a low concentration region (115 in FIG. 10) is obtained by partially implanting a p-type impurity into the diffusion layer.
b) is formed, and in the p-type diffusion layer, a p-type impurity is partially overlapped and implanted to form a high concentration region (125a in FIG. 10), and both diffusion layers have different impurity concentrations. Three regions are each formed. The order in which the first to third ion implantations are performed is not particularly limited.

As a method of forming the diffusion layer, a high impurity concentration region is formed by injecting an n-type impurity in the n-type diffusion layer in a partially overlapping manner,
In the p-type diffusion layer, a method of forming a low impurity concentration region by partially implanting an n-type impurity into the diffusion layer may be adopted.

However, as in the above example, when a method of partially implanting an impurity of a conductivity type opposite to that of the diffusion layer is adopted as a method of forming the diffusion layer, the implantation of the p-type impurity is performed first, and then the n-type impurity is implanted.
It is preferable that the implantation of the type impurity be performed later. Since the p-type impurity is more easily absorbed by the oxide film than the n-type impurity,
This is because if the p-type impurity is implanted later, the impurity distribution near the surface of the formed diffusion layer may become unstable.

Of course, it is also possible to adopt a method in which both the n-type diffusion layer and the p-type diffusion layer are formed by implanting impurity ions of the same conductivity type as the diffusion layer so as to partially overlap.

After all the ions are implanted into the diffusion layers, the thick film portion 1 of the oxide film is formed above both diffusion layers by thermal oxidation.
16 and 126 are formed. Thick film portions 116 and 12 of oxide film
The film thickness of 6 is suitably about 500 to 800 nm. After this thermal oxidation, the silicon nitride film 131 is removed (FIG. 1).
5).

The oxide film 130 is removed except for portions to be the gate oxide films 117 and 127, and the gate oxide films 117 and 127 are removed.
The gate electrodes 118 and 128 are formed by patterning polycrystalline silicon deposited on the substrate 27 by, for example, a CVD method. Further, an n-type impurity is ion-implanted in the n-channel portion and a p-type impurity is ion-implanted in the p-channel portion, thereby forming source regions 113 and 123 and drain regions 114 and 124 (FIG. 16). This ion implantation is performed, for example, at an acceleration voltage of 50 keV and a dose of 5 × 10 ^15.
cm ^-2 . Further, necessary members such as a passivation film and metal wiring are formed to manufacture the semiconductor device of the present invention.

The characteristics of the above-described CMOS transistor are compared with those of a conventional CMOS transistor of the same size (the MOS transistors in both channel regions have the structure shown in FIG. 17).
The on-resistance of the channel is about 30% when the withstand voltage is the same
It was low, and the withstand voltage was about 20% higher when the on-resistance of the channel was made equal. Thus, the semiconductor device of the present invention
The channel on-resistance can be reduced while maintaining high withstand voltage characteristics.

[0031]

As described above, according to the semiconductor device of the present invention, a part of the semiconductor substrate on which the source and drain regions of the same conductivity type are formed is thicker than other parts. A gate electrode is formed via an oxide film formed on the substrate, and a diffusion of the conductivity type having a lower impurity concentration than the drain region is provided between the source region and the drain region in contact with the drain region. A layer is formed, a portion of the oxide film interposed between the diffusion layer and the gate electrode includes a thick film portion, and the diffusion layer has two or more regions having different impurity concentrations. Thus, the operating speed can be improved by reducing the on-resistance of the channel while maintaining the high withstand voltage characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view of an example of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of an example of the semiconductor device according to the first embodiment.

FIG. 3 is a sectional view of an example of the semiconductor device according to the first embodiment;

FIG. 4 is a sectional view of an example of the semiconductor device according to the first embodiment;

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG. 1;

6 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

7 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

8 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

9 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

FIG. 10 is a sectional view of an example of a semiconductor device according to a second embodiment.

11 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

12 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

13 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

14 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

15 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

16 is a process sectional view illustrating the method for manufacturing the semiconductor device shown in FIG.

FIG. 17 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 11, 51 Silicon substrate 12, 52 Well 13, 53 Source region 14, 54 Drain region 15a, 15b, 15c, 55 Diffusion layer 16, 17, 56, 57 Oxide film 18, 58 Gate electrode 30 Oxide film 31 Silicon nitride film 32a , 32b resist 111 silicon substrate 112 p-type well 113 n-type source region 114 n-type drain region 115a, 115b n-type diffusion layer 116 oxide film (n channel side) 117 gate oxide film (n channel side) 118 gate electrode (n channel) Side) 122 n-type well 123 p-type source region 124 p-type drain region 125 a, 125 b p-type diffusion layer 126 oxide film (p-channel side) 127 gate oxide film (p-channel side) 128 gate electrode (p-channel side) 130 oxidation Film 131 silicon nitride Film 132a, 132b, 132c resist

Claims (2)

[Claims] 1. A gate electrode is formed on a surface of a semiconductor substrate on which a source region and a drain region of the same conductivity type are formed via an oxide film partially formed to be thicker than other portions. In the region between the source region and the drain region, which is in contact with the drain region, the conductive type diffusion layer having a lower impurity concentration than the drain region is formed, and the diffusion layer of the oxide film and A semiconductor device, wherein a portion interposed between the gate electrode and the gate electrode includes a thick film portion, and the diffusion layer has two or more regions having different impurity concentrations. 2. The semiconductor device according to claim 1, wherein the diffusion layer has a region including an end on the source region side and a region having a higher impurity concentration than the region.