JPS62120082A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the operating speed of an element, by composing each of source and drain regions of a low-concentration first diffusion layer provided in an element region near a gate electrode, of a low-concentration second diffusion layer located in an element region deeper than the first diffusion layer and of a high-concentration diffusion layer in an element region shallower than the second diffusion layer. CONSTITUTION:Phosphorus ions are implanted with a gate electrode 24 used as a mask for forming first impurity layers 25a and 26a (a). Using the gate electrode 24 and a silicon oxide film 27' on the side wall thereof as a mask, phosphorus and arsenic ions are implanted sequentially to form second impurity layers 25b and 26b, and third impurity layers 25c and 26c (b). The structure is then subjected to thermal treatment so that low-concentration first diffusion layers 28a and 29a are formed near the electrode 24, second diffusion layers 28b and 29b are formed in deeper locations than the first diffusion layers and third diffusion layers 28c and 29c are formed to be surrounded by the second diffusion layers 28b and 29b, respectively (c). Thus, an MOS transistor having an LDD structure can be obtained. In such MOS transistor, the operating speed of element, namely the operating speed of the device would be decreased by the reason that current driving ability in the transistor is decreased by the utilization of the low-concentration diffusion layer. According to the invention, however, the decrease in operating speed of the device can be decreased by the decrease in drain capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MIS type semiconductor device with improved formation of source/drain regions and a method of manufacturing the same.

[Technical background of the invention and its problems]

In the field of semiconductor devices, the miniaturization of Mo8 ICs is remarkable. In particular, from the viewpoint of improving the switching speed of MoS transistors, efforts are being made to reduce the channel length of the gate electrode.

However, as the channel length decreases, the following problems arise in terms of device characteristics.

First, as the channel length decreases, the threshold voltage of the transistor in the short channel region becomes shallower.
A so-called short channel effect may occur (as shown in FIG. 2). In other words, the threshold voltage of a transistor decreases rapidly in the short channel region, and the threshold voltage fluctuates significantly due to slight changes in the device manufacturing process. This is because the gap between the source and drain regions is short. This is explained by the fact that in the channel region, the influence of the depletion layer generated near the source/drain region cannot be ignored, and as a result, the gate voltage required to effectively invert the surface of the channel region becomes lower.

Generally, the potential of the substrate forming the channel region is equal to or very close to the potential of the source region, so it is stronger in the channel region near the source/drain region, and this region also has an effect on the reduction of the threshold voltage. becomes the strongest.

In addition, as the channel length decreases, the electric field generated in the channel region by the voltage applied between the source and drain regions becomes stronger, and as a result, some of the electrons and holes generated by impact ionization due to the channel current are transferred to the semiconductor substrate. and jump into the gate insulating film,
A portion of the current flows into the gate and generates a gate current, but some of it is trapped within the gate insulating film and accumulates, causing changes in the transistor's threshold voltage, channel conductance, etc., which affect the operation of the transistor. This is a major cause of changes in characteristics and deterioration of device reliability. Therefore, the electric field between the source and drain regions is
Since the impact ionization is concentrated in the channel region near the drain region, impact ionization mainly occurs in this region. For this reason, as shown in FIG. 3, among the impurity regions forming the drain region, there is a relatively low impurity concentration fIA in the region near the channel f14 region.
L D D (Lightly
A MOS transistor with a D oped drain structure has been developed.

1 in the figure is, for example, a P-type semiconductor substrate.

A field oxide film 2 is provided on the surface of this substrate 1. In the element region of the substrate 1 surrounded by the field oxide 112, source/drain regions 3.4 are provided spaced apart from each other. Here, the source region 3 is located at a relatively high concentration (~10zO/
ClR3 degree>+7) N'' type impurity diffusion region 3a,
Relatively low concentration near the channel region (~1018/c
It is composed of an N- type impurity diffusion region 3b with an IR of about 3).

Similarly, the drain region 4 is also an N1 type impurity diffusion region t.
ii14a, and an N- impurity diffusion region 4b. The source/drain region [substrate 1 between 3 and 4]
A gate electrode 6 is provided thereon via a gate oxide 11!5. An interlayer insulating film 7 is provided on the entire surface including these gate electrodes 6, and the source/drain regions 3.4
A contact hole 8 is formed in the upper interlayer insulating film 7 . This contact hole 8 is provided with a wire 9 electrically connected to the source/drain region 3.4.

According to the MOS transistor shown in FIG. 3, the drain region iii! in contact with the channel region! Since 4 is an impurity diffusion region tg4b with a low concentration, this region can bear part of the voltage applied between the source and drain regions 4 and 3.4, and the channel region near the drain region 144 It is possible to weaken the electric field concentrated in the Therefore, it is possible to improve the variation in threshold voltage and device reliability due to the above-mentioned reduction in channel length. However, in the case of the above-mentioned Mo8)-transistor, the source/drain regions 3.4 in contact with the channel region are N-type impurity diffusion regions 3b, 4b, so the resistance value of that part inevitably increases. . This causes a reduction in the switching speed of the transistor, impairing its high speed performance.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a fine semiconductor device that allows high-speed VJ fabrication of an element, and a method for manufacturing the same.

[Summary of the invention]

The invention of the present application cylinder 1 includes a first low concentration diffusion layer in which source and drain regions are respectively provided in device regions near gate electrodes;
It is characterized by being composed of a low concentration second diffusion layer provided in an element region deeper than this first diffusion layer, and a high concentration third diffusion layer provided in an element region shallower than this second diffusion layer. The main idea is to achieve high-speed operation of the device.

The second invention of the present application includes a step of forming a field oxide film on the surface of a semiconductor substrate of a first conductivity type, and a gate electrode formed on the element fr4 region of the substrate surrounded by the field oxide film via a gate oxide film. a step of introducing a first impurity of a second conductivity type into the element region at a low concentration using the gate oxide film as a mask; and a step of forming a film over the entire surface and removing it by reactive ion etching. , a step of leaving the film on the side wall of the gate electrode, a step of introducing a first impurity of a second conductivity type into the element region at a low concentration using the gate electrode and the remaining film as a mask, and a step of introducing a first impurity of a second conductivity type into the element region at a low concentration, and a step of introducing a second impurity at a high concentration into the remaining film, and the main point is to achieve high-speed operation of the device.

[Embodiments of the invention]

Hereinafter, a case in which the present invention is applied to the manufacture of an N-channel MO8FET will be described with reference to FIGS. 1(a) to 1(l).

[1] First, a field oxide film 22 for element isolation was formed on the surface of a P-type (100) silicon substrate 21 by a well-known selective oxidation method (as shown in FIG. 1(a)). Continuing,
A gate oxide film (S i 02
To form a film 23 (as shown in FIG. 1(b)). Next, after forming a polycrystalline silicon film over the entire surface of the substrate, a gate electrode 24 having a desired shape was formed using a well-known microfabrication technique. After that, phosphorus was ion-implanted into the entire surface at an acceleration voltage of 40 KeV and a dose of 1.0" cm°2.
To form the first impurity layers 25a and 26a with a low concentration, the first
Figure (C) (Illustrated). Furthermore, after cleaning the entire surface of the substrate 21, approximately 200 gates 1i11 are exposed on the surface of the substrate.
An oxide film (not shown) is formed on the surfaces of the i24 and the substrate 21, and then a silicon oxide film 27 as a coating is formed by vapor phase growth (as shown in FIG. 1(d)).

[2] Next, the silicon oxide film 26 is coated with, for example, CF4.
Silicon is etched on the sidewalls of the gate electrode 24 by reactive ion etching (RIE) using a mixed gas of gas and H2 gas as an etchant gas. l! The 1st membrane 27' was left intact. Next, using the gate electrode 24 and the remaining silicon oxide film 27' as a mask, phosphorus is ion-implanted into the element region under conditions of an acceleration voltage of 60 KeV and a dose of 4×10 13 α da, to form low-concentration second impurity layers 25 b and 2 .
5b was formed. Subsequently, using the same material as a mask, an acceleration voltage of 50 KeV and a dose of ff15X10 were applied to the element region.
Ion implantation is performed under the condition of "clR" to form the second impurity layer 2.
High concentration third impurity layers 25c, 2 shallower than 5b, 26b
6c (as shown in FIG. 1(e)). Next, heat treatment is performed at 900° C. in an oxygen atmosphere to remove the exposed substrate 21.
and silicon oxide Ml (not shown) on the gate electrode 24.
, and the impurity layers 25a to 25c, 2
The impurities in 6a-26C were activated. As a result, a lightly doped first diffusion layer 28a (29a) is formed in the element region (near the gate electrode (near the channel region)), and a lightly doped second diffused layer 28b (29b) is formed in the deeper element region. A third diffusion layer with a high concentration is formed in an element region shallower than the diffusion layer 28b (29b) so as to be surrounded by the second diffusion layer! 28c (2
9c) were formed respectively. Here, the diffusion layers 28a to 28
C is collectively called a source region 128, and 29a to 29G are collectively called two drain regions. Furthermore, after forming silicon oxide 11130 on the entire surface using a well-known technique, phosphorus-doped glass 1131 was formed (Fig. 1(f)).
(Illustrated). Thereafter, after annealing in N2 at 950°C, the glass 1 on the source/drain regions 29, 30 is removed.
A contact hole 32 was formed by selectively opening holes in I31, silicon oxide 1130, and the like. Finally, a Δ2 wiring 33 is formed in this contact hole 32 to form an N-channel MO
3FET is manufactured (as shown in Figure 1(g)).

According to the present invention, after forming the first impurity layers 25a and 26a by ion-implanting phosphorus using the gate electrode 24 as a mask in FIG. 1(C), the gate electrode 24 and this impurity layer are formed in FIG. Using the silicon oxide film 27' formed on the sidewall as a mask, ions of phosphorus and arsenic are sequentially implanted under predetermined conditions to form the second impurity layers 25b, 26b, and the third impurity layer.
In order to form impurity layers 250 and 260 and further perform heat treatment, a low concentration first diffusion 112 is formed near the gate electrode wA24.
8a, 29a are deeper than the second diffusion layers 28b, 29
Third diffusions 1128c and 29c are formed such that the third diffusion layers 1128c and 29c are surrounded by the second diffusion layers 28b and 29b, respectively. Therefore, according to the present invention, the reduction in the operating speed of the device due to the reduction in the current driving ability in the transistor due to the use of a low concentration diffusion layer in the MOS transistor with the LDD structure, that is, the reduction in the speed of the device, is due to the drain capacitance. It is reduced by lowering, and on the contrary, it increases under optimal conditions.

This will be explained with reference to FIG. According to the figure, in general, in an LDD structure MoS transistor,
It is clear that the capacitance of the N+ layer decreases depending on the reverse voltage applied to the junction by replacing it with a single N layer. In fact, especially at low applied voltages, the
It becomes 10. In the above embodiment, the third diffusion JI2
Similarly, the capacitance of 8c (29C) is reduced by wrapping the second diffusion layer 28b (29b) in the depth direction.

At this time, as shown in FIG. 5, the amount of ion implantation of phosphorus for forming a low concentration diffusion layer was changed from 1×1013α to 4×1014.
ctx”, the second diffusion layer 28b (29b)
The phosphorus profile extends in the depth direction to form a deep junction, and the second expanded rl1 layer 28b (29b) increases in the depth direction. Therefore, this deep second diffusion 128b (2
9b) is depleted, the width of the depletion layer on the diffusion layer side increases, and the junction capacitance decreases.

The N-channel MO8FET according to the present invention is shown in FIG.
As shown in FIG.
a, 29a are provided in the vicinity of the gate electrode 24, and second diffusion layers 28a, 29b, which are shallower than the first diffusion layers 1128a, 29a and have a relatively low concentration, are provided.
The relatively high concentration third diffusion layer 28C1 is surrounded by b.
It has a structure with 29G. Therefore, as described above, it is possible to reduce the junction capacitance compared to the conventional method and achieve high-speed operation of the element.

In the above example, the goo 1-
Although phosphorus was ion-implanted using the electrode as a mask, the implantation is not limited to this, and for example, arsenic may be used. Further, the same applies to the ion implantation using the gate electrode and silicon oxide film as masks in the step of FIG. 1(e). However, since it is preferable that the impurity in this region be formed deeply and at a low concentration, phosphorus is more effective than arsenic. Further, in the above embodiment, phosphorus ions are implanted, but a diffusion technique at 950° C. or lower may be used, for example.

In the above embodiment, arsenic ions are implanted to form the third diffusion layer having a relatively high degree of PIM, but the present invention is not limited to this, and phosphorus may also be used. However, when using phosphorus, the silicon oxide film remains on the sidewalls of the gate electrode, and after doping the n-type first impurity at a low concentration, this impurity is formed deeper than the second diffusion layer. It is necessary to perform an annealing process before introducing impurities for forming the second diffusion layer.

In the above embodiment, the case where the present invention is applied to the manufacture of an N-channel MO8FET has been described, but the present invention is not limited to this, and may be applied to the manufacture of a P-channel MO8FET, for example. However, P
In the case of channel MO8FET, for example, B1 is used as an impurity for forming a relatively low concentration diffusion layer, and B+ or BF is used as an impurity for forming a relatively high concentration diffusion layer.
2"" can be used.

(Effects of the Invention) As described in detail above, according to the present invention, it is possible to provide a fine semiconductor device capable of high-speed operation of an element and a method for manufacturing the same.

[Brief explanation of drawings]

FIGS. 1(a) to (g) are cross-sectional views showing the manufacturing method of an N-channel MO8FET according to an embodiment of the present invention in order of steps, and FIG. 2 is a characteristic diagram showing the relationship between the gate channel and the threshold voltage. , FIG. 3 is a cross-sectional view of a conventional MoS transistor, FIG. 4 is a characteristic diagram showing the relationship between reverse applied voltage and junction capacitance ω, and FIG. 5 is a characteristic diagram showing the relationship between depth and impurity concentration. . 21... P-type silicon substrate, 22... Field oxide film, 23... Gate oxide film, 24... Gate electrode, 25a to 25C126a to 26 c-... Impurity layer, 27.27'-・・Silicon a training, 8a~28C
129a to 29c...diffusion layer, 30...silicon oxide film, 31...glass film, 32...contact hole, 33...AQ wiring. Applicant's agent Patent attorney Takehiko Suzue (-'vda.

Claims (4)

[Claims] (1) A semiconductor substrate of a first conductivity type, a field oxide film provided on the surface of this semiconductor substrate, and a source region of a second conductivity type provided in an element region of the substrate surrounded by the field oxide film. In a semiconductor device comprising a drain region and a gate electrode provided via a gate oxide film over an element region including at least a channel region between the source and drain regions, the source and drain regions are respectively connected to the gate electrode. a first low concentration diffusion layer provided in a nearby element region; a second low concentration diffusion layer provided in the element region deeper than the first diffusion layer; and a second diffusion layer shallower than the second diffusion layer. 1. A semiconductor device comprising a highly doped diffusion layer provided in an element region. (2) forming a field oxide film on the surface of a first conductivity type semiconductor substrate; and forming a gate electrode via a gate oxide film on the element region of the substrate surrounded by the field oxide film. , a step of introducing a first impurity of a second conductivity type into the element region at a low concentration using this gate electrode as a mask, and forming a film on the entire surface and removing it by reactive ion etching, and removing the film by reactive ion etching. a step of allowing the first impurity to remain on the side wall of the electrode; a step of introducing a first impurity of a second conductivity type into the element region at a low concentration using the gate electrode and the remaining film as a mask; A method for manufacturing a semiconductor device, comprising the step of introducing a second impurity at a high concentration. (3) The method for manufacturing a semiconductor device according to claim 2, wherein the first impurity of the second conductivity type is phosphorus, and the impurity of the second conductivity type is arsenic. (4) The method for manufacturing a semiconductor device according to claim 2, wherein the first impurity of the second conductivity type is poron, and the second impurity of the second conductivity type is BF_2 ions.