JP2586000B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a gate polysilicon is a P-type.

[0002]

2. Description of the Related Art An insulated gate field effect transistor (so-called MOS transistor) is used as one of semiconductor devices.
Are widely known, and there are a horizontal type in which the drain and the source exist on the same surface of the substrate and a vertical type in which the drain and the source exist on the opposite side of the substrate. The former is used as a circuit element such as an LSI, and the latter is used as a switching element because a large current can be obtained.

FIG. 4 shows the steps of manufacturing a vertical insulated gate field effect transistor as an example of a conventional semiconductor device.

[0004] As shown in FIG.
A P-type epitaxial layer 2 is grown thereon. Next, a gate oxide film 3 is formed on the P-type epitaxial layer 2, and boron, which is a P-type impurity, is implanted in a later step to make the gate oxide film 3 P-type. In this stage, nitridation and re-oxidation are continuously performed in order to prevent the occurrence. Nitriding is performed by using NH ₃ or N ₂ O gas at a high temperature for a short time such as lamp annealing. After nitriding, a gate polysilicon 4 is formed on the gate oxide film 3 as shown in FIG. After opening a window using a photolithography technique, an N-type base layer 5 is formed using the gate polysilicon 4 as a mask. After forming the back gate contact portion 6, a P-type source layer 7 is formed using the gate polysilicon 4 and the resist as a mask. Thereafter, as shown in FIG. 4C, an interlayer insulating film 8, a source electrode 9, and a back electrode 10 functioning as a drain electrode are formed.

[0005]

In the above-described manufacturing method, when nitriding is performed, if nitriding is performed with NH ₃ , hydrogen is introduced into the gate oxide film 3, which causes a reduction in reliability. _If nitriding is performed with ₂ O, the gate oxide film 3 will be oxidized during the nitriding process, so that it is difficult to control the thickness of the gate oxide film 3.

In addition, in the conventional nitriding by the diffusion furnace, the film quality of the gate oxide film is changed and the film becomes a nitride film, so that there is a problem that a characteristic variation occurs in a gate bias test.

The present invention has been made in view of the above points, and has as its object to provide a method of manufacturing a semiconductor device in which the thickness of a gate oxide film can be controlled without lowering reliability due to nitriding. And

[0008]

According to the present invention, in order to achieve the above object, a gate oxide film is formed on an epitaxial layer of the same conductivity type grown on a semiconductor substrate of a semiconductor device. Was ion-implanted, followed by dry oxidation.

[0009]

According to the present invention, a nitride film is formed on the front and back surfaces of a gate oxide film to prevent the penetration of a P-type impurity in the subsequent implantation of a P-type impurity into gate polysilicon. Needless to say, the change in the thickness of the gate oxide film during nitriding can be reduced, and there is no introduction of hydrogen into the gate oxide film as in the case of using conventional NH ₃ .

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a method of manufacturing a semiconductor device according to the present invention, and shows a manufacturing process when applied to a method of manufacturing a vertical insulated gate field effect transistor as an example of a semiconductor device. First, a P-type epitaxial layer 2 is grown on a P-type substrate 1 as shown in FIG. Next, a gate oxide film 3 is formed on the P-type epitaxial layer 2, where nitrogen ions are implanted. The ion implantation energy is 1 when the gate oxide film 3 is about 500 °.
0 to 20 keV is appropriate. By the implantation of the nitrogen ions, the upper and lower surfaces of the gate oxide film 3 are nitrided as shown by reference numeral 11 in FIG. 2 to generate a nitrided oxide film layer.

Then, at (950 ± 50) ° C., (90 ± 6)
A heat treatment of about 0) seconds is performed to grow the gate polysilicon 4 as shown in FIG. Next, after opening a window using a photolithography technique, dry oxidation is performed to form an N-type base layer 5 using the gate polysilicon 4 as a mask. After the back gate contact portion 6 is formed, the gate polysilicon 4 and the resist
A mold source layer 7 is formed. At this time, P-type impurities are simultaneously implanted to make the gate polysilicon 4 P-type. In this embodiment, the N-type base layer 5 and the P-type source layer 7 are formed by diffusion self-alignment (DSA). Then Figure 1
As shown in (c), the interlayer insulating layer 8 made of phosphorus glass,
A source electrode layer 9 and a back electrode 10 are formed. Oxidation after the nitriding treatment until the formation of the back electrode 10 is all performed by dry oxidation.

According to the experiments of the present inventors, the increase in the thickness of the gate oxide film, which was conventionally 5% on average and 12% at the maximum during nitriding by N ₂ O, was increased by the implantation of nitrogen ions according to the present invention. It could be reduced to 2% and up to 3%. The rate of change of the threshold voltage in the gate bias test is
What was about 0% was reduced to about 3%.

The ion implantation energy is 10 to 20.
The range at keV is 209 ° to 428 ° and does not penetrate the oxide film (about 500 °).

FIG. 3 shows another embodiment of the method of manufacturing a semiconductor device according to the present invention.

In this embodiment, the present invention is applied to a manufacturing process of a lateral insulated gate field effect transistor. In the drawing, the same reference numerals as those in FIG. 1 indicate the same components.

In this embodiment, an N-type substrate 1a is used, and heat treatment and dry oxidation are performed by implanting nitrogen ions into the gate oxide film 3, thereby providing a highly reliable low on-resistance P-channel MOS transistor. The power loss in the IC can be reduced. Also in this embodiment, the source region 12 and the drain region 13
Are formed by diffusion self-alignment (DSA). 14 is a drain electrode, and 15 is an element isolation film.

[0018]

As described above, according to the present invention,
The ion implantation method for nitriding the gate oxide film enables accurate control of the thickness of the gate oxide film during nitridation, which causes instability in characteristics, and reduces the introduction of hydrogen into the gate oxide film, resulting in a stable A semiconductor device having characteristics can be realized.
Further, since a diffusion furnace is not used, there is no change in the film quality of the gate oxide film due to nitriding, and a semiconductor product having no characteristic change can be obtained.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C show main manufacturing steps when a semiconductor device manufacturing method according to the present invention is applied to a vertical insulated gate field effect transistor.

FIG. 2 is a schematic enlarged view of a nitrided oxide film formed in a manufacturing method according to the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device when the method of manufacturing a semiconductor device according to the present invention is applied to a lateral insulated gate field effect transistor.

FIGS. 4A, 4B, and 4C show main manufacturing steps of a method for manufacturing a conventional vertical insulated gate field effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type substrate 2 P-type epitaxial layer 3 Gate oxide film 4 Gate polysilicon 5 N-type base layer 6 Back gate contact part 7 P-type source layer 8 Interlayer insulating film 9 Source electrode

Claims (5)

(57) [Claims] In a method of manufacturing a semiconductor device in which a gate polysilicon is a P-type, a gate oxide film is formed on an epitaxial layer of the same conductivity type as the semiconductor substrate grown on the semiconductor substrate of the semiconductor device. A method of manufacturing a semiconductor device, wherein nitrogen is ion-implanted into the gate oxide film, followed by dry oxidation. 2. The method according to claim 1, wherein the semiconductor substrate is a P-type, and the semiconductor device is a vertical insulated gate field-effect transistor. 3. The method according to claim 1, wherein the semiconductor substrate is N-type, and the semiconductor device is a lateral insulated gate field effect transistor. 4. A semiconductor device having a MOS structure on a surface thereof,
The base and source are diffusion self-aligned (DS
3. The method for manufacturing a semiconductor device according to claim 2, wherein the method is performed according to A). 5. A semiconductor device having a MOS structure on a surface thereof,
4. The method according to claim 3, wherein a source region and a drain region are formed on the surface of the device by diffusion self-alignment (DSA).