JP2834058B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to the manufacture of semiconductor devices.
A method, semi particularly having a vertical double diffused MOSFET
The present invention relates to a method for manufacturing a conductor device .

[0002]

2. Description of the Related Art A conventional vertical double diffusion MOSFET has a structure as shown in FIG. In FIG. 1, n formed on an n ⁺ type silicon substrate 1 serving as a drain region is formed.
-Type epitaxial layer 5 and n-type epitaxial layer 5
And a p-type base layer 8 formed in the n-type epitaxial layer 5 in a region corresponding to the outside of the gate electrode 7A via the gate oxide film 6A.
And an n ⁺ -type source layer 10 formed in the p-type base layer 8, a p ⁺ -type back gate layer 9 for contacting the p-type base layer 8, and a surface formed on the gate electrode 7A. Interlayer insulating film 11, n ⁺ -type source layer 10 and p ⁺
A source electrode 12 formed so as to make contact at the portion of the mold back gate layer 9, a surface protective film 13 formed on the surface of the source electrode 12, and a drain electrode 14 formed on the lower surface of the silicon substrate 1. It is mainly composed of

The above-mentioned conventional vertical double diffusion MOSFET
In order to reduce the withstand voltage BV _DSS between the drain and the source to about 30 V or less, if the resistivity ρ _epi of the n-type epitaxial layer 5 is reduced to increase the impurity concentration, the impurity is formed later in the n-type epitaxial layer 5. Since the impurity concentration of the p-type base layer 8 is low, the depletion layer from the n ⁺ -type source layer 10 extends to the p-type base layer 8 to easily cause punch-through,
The variation in the drain-source breakdown voltage BV _DSS increases. Therefore, p is set so that punch-through hardly occurs.
The impurity concentration of the p-type base layer 8 serving as the gate / channel region is increased near the substrate surface, and the gate cutoff voltage V _{GS (off) serving as} the drive voltage of the MOSFET is increased. However, it has been difficult to realize a MOSFET having a low withstand voltage and a low driving voltage.

As a countermeasure against this, the inventor disclosed in Japanese Patent Laid-Open No.
No. 663 proposed a MOSFET having a structure shown in FIG. 4 differs from FIG. 3 in that an epitaxial layer formed on an n ⁺ -type silicon substrate 1 serving as a drain region is composed of an n ⁺ -type epitaxial layer 2 and an n-type epitaxial layer 5.

[0005]

In the conventional vertical double-diffused MOSFET shown in FIG. 4, it is not necessary to increase the impurity concentration of the p-type base layer 8 in order to make it difficult for punch-through to occur. Although the gate cutoff voltage V _{GS (off) serving as the} driving voltage does not increase, the drain-source breakdown voltage BV _DSS is determined by the impurity concentration of the n ⁺ -type epitaxial layer 2 and the p-type base layer 8. It is difficult to reduce the breakdown voltage to about 30 V or less, and it is difficult to realize a MOSFET having a low breakdown voltage and a low driving voltage.

An object of the present invention is to provide a vertical double diffusion MOSFE.
It is an object of the present invention to provide a method of manufacturing a semiconductor device having a T having a low withstand voltage and a low driving voltage.

[0007]

[0008]

According to a method of manufacturing a semiconductor device of the present invention, a first epitaxial layer made of a first-conductivity-type high-concentration impurity layer is formed on a first-conductivity-type semiconductor substrate. Selectively forming a first base layer made of a second conductivity type high concentration impurity layer on the surface of the layer, and forming a second epitaxial layer consisting of a first conductivity type low concentration impurity layer on the entire surface including the first base layer Forming a gate electrode and a gate oxide film by patterning the polycrystalline silicon film and the oxide film, and forming the second epitaxial layer using the gate electrode as a mask. Forming a second base layer made of a low-concentration impurity layer reaching the first base layer by ion-implanting a second conductivity type impurity into the second base layer; Forming a source made of a first-conductivity-type high-concentration impurity layer on the surface of the second base layer including a peripheral portion of the back gate layer. It is a feature.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 (a) to 1 (c) and 2 (a),
(B) is sectional drawing of the semiconductor chip shown in order of process for describing one Embodiment of this invention.

First, as shown in FIG. 1A, an n ⁺ -type epitaxial layer 2 containing a high concentration impurity of 10 ¹⁶ to 10 ¹⁷ cm ^{-3 and serving as} a first drain layer is formed on an n ⁺ -type silicon substrate 1.
Is formed to a thickness of about 4 μm. Next, an oxide film having a thickness of about 200 nm is formed on the entire surface by a thermal oxidation method, and then patterned to form a mask 3. Next is boron 10 ¹⁵ c on the entire surface
^{Implanted by} about m ^-2 and heat-treated to form a first base layer p
^{The +} type base layer 4 is formed.

Next, as shown in FIG. 1B, after the mask 3 is removed, a second impurity containing a low concentration impurity of 10 ¹⁵ to 10 ¹⁶ cm ^-3 is entirely contained including the surface of the n ⁺ type epitaxial layer 2. An n-type epitaxial layer 5 serving as a drain layer is formed to a thickness of about 5 μm. Next, after an oxide film 6 having a thickness of 20 to 50 nm is formed, a polycrystalline silicon film 7 containing a high concentration impurity of 10 ¹⁸ to 10 ¹⁹ cm ⁻³ is formed by a CVD method.

Next, as shown in FIG. 1C, the polycrystalline silicon film 7 and the oxide film 6 are patterned to form a gate electrode 7A.
Then, a gate oxide film 6A is formed. Then, using this gate electrode 7A as a mask, boron is applied to the entire surface at 10 ¹³ to 10 ¹⁴ cm ⁻²
Ion implantation and heat treatment are performed to form a p-type base layer 8 serving as a second base layer.

Next, as shown in FIG. 2A, a photoresist film is formed on the entire surface and then patterned to form an opening in the center of the p-type base layer 8. Next, boron ions are implanted into the entire surface to form ap ⁺ -type back gate layer 9 on the surface of the p-type base layer 8. Next, after removing the photoresist film used as the mask, a photoresist film is formed again on the entire surface and patterned to form an opening in the surface of the p-type base layer 8 including the peripheral portion of the back gate layer 9.

Next, heat treatment is performed by ion-implanting phosphorus into the entire surface at about 10 ¹⁶ cm ⁻² to form an n ⁺ -type source layer 10. Next, after removing the photoresist film as a mask, an interlayer insulating film 11 made of an oxide film or the like is formed on the entire surface including the surface of the gate electrode 7A by the CVD method.

Next, as shown in FIG. 2B, the interlayer insulating film 11 is patterned to form a p ⁺ type back gate layer 9 and n ⁺
After forming an opening on the mold source layer 10, an Al film having a thickness of about 2 μm is deposited on the entire surface to form a source electrode 12.
Next, a surface protection film 1 made of a PSG film is formed on the source electrode 12.
3 and a drain electrode 14 made of Ti-Ni-Ag or the like is formed on the lower surface of the silicon substrate 1 to form a vertical double diffused MOSF.
Complete the ET.

According to the present embodiment configured as described above, the drain-source breakdown voltage BV _DSS is determined by the n ⁺ -type epitaxial layer 5 and the p ⁺ -type base layer 4 having a high impurity concentration. In order to achieve this, the concentration of these impurities may be controlled. Further, since the gate cutoff voltage V _{GS (off), which} is the drive voltage of the MOSFET, is determined by the impurity concentration near the surface of the p-type base layer 8 inside the n-type epitaxial layer 5, the drain-source breakdown voltage BV _DSS
Can be independently controlled without depending on the part for determining the MOSFET, and a MOSFET having a low withstand voltage (for example, about 30 V or less) and a low drive voltage (for example, about 1 V or less) can be realized.

In the above embodiment, the case where the drain layer is of the n-type has been described, but it is needless to say that the drain layer may be of the p-type.

[0018]

The effect of the present invention is that the gate cutoff voltage V _{GS (off), which} is the drive voltage of the MOSFET, does not increase even if the drain-source breakdown voltage BV _DSS is reduced. Thus, a semiconductor device having a MOSFET with a low withstand voltage and a low drive voltage can be realized.

The reason is that the drain-source breakdown voltage BV
_DSS is determined by the impurity concentration of the n ⁺ -type epitaxial layer and the p ⁺ -type base layer, and the gate cutoff voltage V
_{This is because GS (off)} is determined by the impurity concentrations of the n-type epitaxial layer and the p-type base layer irrespective of the impurity concentration of the n ⁺ -type epitaxial layer, and can be independently controlled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for describing one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for describing one embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 4 is a cross-sectional view illustrating another conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 n ⁺ type silicon substrate 2 n ⁺ type epitaxial layer 3 mask 4 p ⁺ type base layer 5 n type epitaxial layer 6 oxide film 6 A gate oxide film 7 polycrystalline silicon film 7 A gate electrode 8 p type base layer 9 p ⁺ type back Gate layer 10 n ⁺ type source layer 11 interlayer insulating film 12 source electrode 13 surface protective film 14 drain electrode

Claims (1)

(57) [Claims] A first conductive type high-concentration impurity layer formed on a first conductive type semiconductor substrate, and a second epitaxial layer formed selectively on a surface of the first epitaxial layer.
Forming a first base layer made of a conductive-type high-concentration impurity layer, and forming a second epitaxial layer consisting of a first-conductivity-type low-concentration impurity layer, an oxide film and a polycrystalline silicon film on the entire surface including the first base layer; Forming a gate electrode and a gate oxide film by patterning the polycrystalline silicon film and the oxide film, and ion-implanting a second conductivity type impurity into the second epitaxial layer using the gate electrode as a mask. Forming a second base layer made of a low-concentration impurity layer reaching the first base layer, and forming a back gate layer made of a second conductivity type high-concentration impurity layer at the center of the second base layer. And a step of forming a source layer made of a first-conductivity-type high-concentration impurity layer on the surface of the second base layer including a peripheral portion of the back gate layer. Production method.