JPH022170A - Manufacture of insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To avoid the floating state of gate electrodes by a method wherein a plurality of the adjacent gate electrodes having different work functions corresponding to the difference in impurity concentration are exposed and a metal or metal-semiconductor compound film 17 is selectively built up on the surfaces of the gate electrode materials only. CONSTITUTION:A silicon oxide film 18 for element isolation is formed on a silicon substrate 11 and a gate oxide film 12 formed on an element forming region and a polycrystalline silicon film 19 is built up over the whole surface. Phosphorus contained in phosphorus glass of a spacer 14 is diffused into the polycrystalline silicon film 19 to make only both the side wall parts of the polycrystalline silicon film 19 n-type. With this constitution, a plurality of adjacent (n<+>-type, p<+>-type and n<+>-type) gate electrodes 13 having different work functions correcponding to the difference in impurity concentration are formed. As the gate electrodes 13 having different work functions corresponding to the difference in impurity concentration are mutually short-circuited by a selective silicide forming method, the floating state of the gate electrodes 13 can be avoided.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a method of manufacturing an insulated gate field effect transistor, the method of manufacturing a gate electrode having a work function change in the channel length direction includes using a semiconductor such as polycrystalline silicon as the gate electrode material. The purpose of the present invention is to provide a method for manufacturing insulated gate field effect transistors that can maintain a high concentration gradient even in a method in which work function change is controlled by impurity concentration and that can be applied to minute devices. In a method for manufacturing an insulated gate field effect transistor having a plurality of adjacent gate electrodes having different work functions due to differences in concentration, a step of depositing a metal film over the entire surface with the plurality of gate electrodes exposed. and,
A method for manufacturing an insulated gate field effect transistor, comprising the steps of chemically reacting the metal film with a gate electrode constituent material by heat treatment, and selectively removing the unreacted metal film, and an impurity. In a method for manufacturing an insulated gate field effect transistor having a plurality of adjacent gate electrodes (13) having different work functions due to differences in concentration, a metal film or A method for manufacturing an insulated gate field effect transistor, comprising a step of selectively growing a metal-semiconductor compound (17) only on the surface of a material constituting a gate electrode (13) by chemical vapor deposition. Contains and composes.

[Industrial application field]

The present invention relates to a method for manufacturing an insulated gate field effect transistor.

[Prior Art] In recent years, with the miniaturization of insulated gate field effect transistors, the hot carrier effect due to an increase in the internal electric field has become a problem. In order to solve this problem, for example, in a device with a gate length of about 1 μm or less, a so-called LDD (Lightly Detailed Drive) is proposed, in which a lightly doped impurity layer is provided at the end of the drain, expanding the depletion layer and relaxing the electric field in this region.
-Doped-Drain) structure is adopted. According to such a structure, the amount of hot carriers generated can be suppressed to a low level, but it cannot be completely suppressed.

In the current manufacturing method, as will be described later, since an insulating spacer exists above the low concentration layer, a deterioration mode specific to LDD structure transistors appears. Therefore, there is a need for a method of manufacturing an LDD structure transistor that does not cause such a deterioration mode.

FIGS. 3A to 3C are cross-sectional views showing the manufacturing process of a conventional LDD structure transistor.

First, as shown in the same figure (a), on a silicon substrate 1,
After forming the gate oxide film 2 and the polycrystalline silicon film 3 in this order, the gate oxide film 2a and the polysilicon film 3a which will become the gate electrode are formed by etching.

Next, as shown in FIG. 2, a through oxide film 4 is formed, and a low concentration layer (n15) is formed by ion implantation or the like.

Next, as shown in the same figure (C), chemical vapor deposition (CVD)
A silicon oxide film 6 is deposited by the method, and spacers 6a (solid lines) are formed on both side walls of the polysilicon layer 3a by anisotropic etching. Using the spacers 6a as a mask, high concentration (n+) sources and drains are formed by ion implantation. Region 7 is formed.

In such a structure, the electric field in this region can be relaxed due to the low concentration layer 5, and the hot carrier effect can be suppressed. However, since the insulating spacer 6a is formed above the low concentration layer 5, charges generated by hot carriers are accumulated there, and this charge depletes the low concentration layer 5, increasing the surface resistance. As a result, a deterioration mode unique to LDD structure transistors appears in which the mutual conductance gm significantly deteriorates as the operating time (stress time) increases.

In order to reduce such deterioration mode, conventionally, the fourth
2. Description of the Related Art A semiconductor device shown in FIG. Note that parts corresponding to those in FIG. 3 are denoted by the same reference numerals. As shown in the figure (a), the gate electrode 8 is configured to cover the periphery of the p-type region 8a and the n-type region 8b, and as shown in FIG. Area 9a
The structure is such that n-type regions 9b9b are formed adjacent to each other on both sides. That is, instead of seeking a charge relaxation effect in a low concentration layer of impurities, the work function of the gate electrode 8.9 is made different in the channel length direction, and the gate end on the drain side is formed with a low work function gate where the channel is easily inverted. It is a semiconductor device that is made of an electrode material and effectively has the same electric field relaxation effect as an LDD structure (for example, Japanese Patent Laid-Open No. 6
2-73668).

According to such a structure, since the gate electrode also exists above the electric field relaxation layer where the local electric field is strongest (in this structure, the channel region below the gate electrode having a low work function), the mutual conductance gm can prevent major deterioration. However, depending on its potential distribution, this structure becomes an electrically good pn junction or Schottky junction, and becomes electrically non-conductive in the case of reverse bias. When manufacturing an insulated gate field effect transistor using such a gate electrode 8.9, either the P-type head region or the N-type region of the pn junction of the gate electrode, or the semiconductor region or the metal region of the Schottky junction. If the wiring metal is contacted only on one side, the uncontacted side becomes electrically floating under reverse bias conditions, which poses a serious problem in device operation.

[Problem to be solved by the invention]

In the case of FIGS. 4(a) and 4(b), in which a pn junction is formed in the gate electrode 8.9, it can be seen that it is difficult to make contact with both the p-wall region and the n-type region.

In other words, when formed as shown in FIG. 2A, contact holes for the source and drain are formed, the gate electrode is etched through the n-type region 8b and the p-type region 8a, and then the P0-type region is etched. It is necessary to make contact with 8a and n+ type region 8b at the same time. Also,
If the contact holes are formed as shown in FIG. The above process is difficult due to the accuracy of lithography alignment.

Therefore, the present invention provides a method for manufacturing a gate electrode having a work function change in the channel length direction, in which a semiconductor such as polycrystalline silicon is used as the gate electrode material and the work function change is controlled by the impurity concentration. An object of the present invention is to provide a method for manufacturing an insulated gate field effect transistor that can maintain a high value and can be applied to minute devices.

[Means to solve problems]

The above problem is solved in a method for manufacturing an insulated gate field effect transistor having a plurality of adjacent gate electrodes, which have different work functions due to differences in impurity concentrations. An insulated gate type electric field characterized by comprising the steps of: depositing the metal film on the metal film, chemically reacting the metal film with a material constituting the gate electrode through heat treatment, and selectively removing the unreacted metal film. In the method for manufacturing an effect transistor and the method for manufacturing an insulated gate field effect transistor having a plurality of mutually adjacent gate electrodes (13) having different work functions depending on a difference in impurity concentration, the plurality of gate electrodes (13) are exposed. The insulation is characterized by comprising a step of selectively growing a metal film or a metal-semiconductor compound (17) only on the surface of the material constituting the gate electrode (13) by chemical vapor deposition in a state where the metal film or the metal-semiconductor compound (17) is The problem is solved by a method for manufacturing gated field effect transistors.

FIG. 1 is a perspective view of a semiconductor device using the manufacturing method according to the present invention. In the figure, 11 is a silicon substrate, 12
13 is a gate oxide film, 13 is a gate electrode formed to have a different work function due to a difference in impurity concentration in the channel length direction,
14 are spacers formed on both side walls of the gate electrode 13;
5 is a low concentration layer, 16 is a high concentration layer forming source/drain regions, and a metal film 17 is deposited on the gate electrode 13 and the source/drain. The above object is to provide a method for manufacturing an insulated gate field effect transistor having a plurality of gate electrodes 13 adjacent to each other, each having a different work function due to a difference in impurity concentration. The metal film 17 is formed into the gate electrode 1 by a process of depositing the film 17 on the entire surface and by heat treatment.
This is achieved by a method for manufacturing an insulated gate field effect transistor characterized by comprising a step of chemically reacting with the three constituent materials and a step of selectively removing the unreacted metal film 17.

[Effect]

In the present invention, gate electrodes 13 having different work functions due to different impurity concentrations are short-circuited using a selective silicide formation method, as shown in FIG. Therefore, a normal contact hole formation method can be used, and any gate electrode 13 is prevented from being in a floating state in either positive or negative switching.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

FIGS. 2(a) to (□□□ are cross-sectional views of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 5A, a silicon oxide film 18 for element isolation is formed on a silicon substrate 11 by a selective oxidation method (LOCOS method), and a gate oxide film 12 is formed in the element formation region.
A polycrystalline silicon film 19 is deposited on the entire surface by CVO method to a thickness of about 400 nm. This polycrystalline silicon film 19 was heated with boron (B) at 60KeV and 1X
Ions are implanted under the conditions of 1014 cm-'' to make it P-type.Furthermore, the silicon oxide film 20 is
The film is deposited to a thickness of about 00 nm.

Next, as shown in the same figure (1)), after patterning the gate electrode shape, the low concentration (n) layer 15 for LDD is implanted with arsenic (As) ions (60KeV, IXIO"cm-
”).

Next, as shown in the same figure (C), 7χ (weight) of phosphorus CP)
200% phosphorus glass (PSG) containing 21% by CVD method
It is deposited to a film thickness of about nm.

Next, as shown in FIG. 4(d), only the side walls of the polycrystalline silicon 18 are left by anisotropic etching, and the spacer 14 is
form.

Next, as shown in the same figure (e), arsenic (As) ions were added to 8
Ion implantation is performed under the conditions of 0 KeV and 4 XIO cm-, and high concentration (n'') N16 is formed for the source and drain by annealing in a later step.

Next, as shown in the same figure), annealing for 900" of Cl2O is performed to activate the source and drain, and the phosphorus contained in the phosphorus glass of the spacer 14 is diffused into the polycrystalline silicon 19. , only the side walls of polycrystalline silicon 19 n
Make it into a mold. As a result, a plurality of adjacent (n"p",n'
) is formed.

Next, as shown in the figure, the silicon oxide film 20 remaining on the top of the polycrystalline silicon 19 is removed by anisotropic etching. This is to perform the described silicidation in a self-aligned manner.For example, a 200 nm thick tungsten film is deposited as a metal over the entire surface using the CVD method.
Annealing is performed at about 600° C. for 20 minutes to chemically react the region in contact with the silicon surface, forming a tungsten silicide (SiWz) film as the metal film 17, and washing out unreacted tungsten.

In subsequent steps, an interlayer insulating film, a wiring film, etc. are formed by conventional methods, and an insulated gate field effect transistor is completed.

According to the above method for manufacturing a semiconductor device, the gate electrodes 13 having different work functions due to different impurity concentrations are short-circuited using a selective silicide formation method, and therefore a normal contact hole formation method is used. The contact can be made completely, and either gate electrode 13 can be connected in either positive or negative switching.
will be prevented from becoming floating.

In the above embodiments, the gate material may be any material that forms a plurality of adjacent gate electrodes that have different work functions depending on the difference in impurity concentration.

Further, the insulated gate field effect transistor can be applied to either an n-channel or a p-channel, and the work function of the gate electrode can be varied depending on the impurity concentration depending on the channel.

Further, in the above embodiment, the metal film 17 is a tungsten silicide (SiWz) film, but other materials such as molybdenum (Mo) and titanium (Ti) may be deposited and silicided by a chemical reaction. may be converted into

Next, a second embodiment of the present invention will be explained with reference to FIG. 2, which was referred to in the first embodiment. As shown in FIG. 2(a), a silicon oxide film 18 for element isolation is formed on a silicon substrate 11 by a selective oxidation method (LOCO5 method), a gate oxide film 12 is formed in the element formation region, and a multilayer film is formed on the entire surface. A crystalline silicon film 19 is deposited to a thickness of about 400 nm by CVD. This polycrystalline silicon film 19 is made into p-type by ion implantation of boron (B) under the conditions of 60 KeV and IXl01 cm-2. Furthermore, a silicon oxide film 20 is deposited to a thickness of about 200 nm by CVD.

Next, as shown in the same figure (b), after patterning the gate electrode shape, the low concentration (N1 layer 15 for LDD) is
As) ion implantation (60KeV, I x 10” cm
−”).

Next, as shown in the same figure (C), 7χ (weight) of phosphorus (P)
200% phosphorus glass (PSG) containing 21% by CVO method
It is deposited to a film thickness of about nm.

Next, as shown in FIG. 4(d), only the side walls of the polycrystalline silicon 18 are left by anisotropic etching, and the spacer 14 is
form.

Next, as shown in the same figure (e), arsenic (As) ions were added to 8
Ion implantation is performed under the conditions of 0 KeV and 4 XIOIscm-'', and a high concentration (n') layer 16 for the source and drain is formed by annealing in a later step.

Next, as shown in the same figure (f), 900° Cl2O is annealed to activate the source and drain, and the phosphorus contained in the phosphorus glass of the spacer 14 is diffused into the polycrystalline silicon 19. Then, only both side walls of the polycrystalline silicon 19 are made n-type. As a result, a plurality of mutually adjacent (n'', p'', n''
) is formed.

Next, as shown in the figure, the silicon oxide film 20 remaining on the top of the polycrystalline silicon 19 is removed by anisotropic etching. This is because the silicidation to be described is performed by self-alignment.The steps up to this point are the same as in the first embodiment.

Next, a tungsten (W) film is grown only on the exposed silicon surface by selective CVD. Selection IHC v
As the o method, for example, a method using tungsten fluoride gas diluted with hydrogen (I+□) is effective.

In the subsequent steps, an interlayer film, a wiring film, etc. are formed by a conventional method, and an insulated gate field effect transistor is completed.

According to the above method for manufacturing a semiconductor device, the gate electrodes 13 having different work functions due to different impurity concentrations are short-circuited using a selective silicide formation method, and therefore a normal contact hole formation method is used. The contact can be made completely, and either gate electrode 13 can be connected in either positive or negative switching.
will be prevented from becoming floating.

In the above embodiments, the gate material may be any material that forms a plurality of adjacent gate electrodes that have different work functions depending on the difference in impurity concentration.

Further, the insulated gate field effect transistor can be applied to either an n-channel or a p-channel, and the work function of the gate electrode can be varied depending on the impurity concentration depending on the channel.

Furthermore, in the above embodiment, the metal film is made of tungsten (W).
Although a film is used, other materials such as tungsten silicide (WSi6) may be deposited by a selective CVO method.

〔Effect of the invention〕

As explained above, according to the present invention, by selectively using a silicide formation method, even if a work function difference is formed in the channel length direction using, for example, a pn junction in the gate polycrystalline silicon, it is possible to create a work function difference in the channel length direction. In the contact hole forming method, p
, n, so that the degree of freedom in the process is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a semiconductor device using the manufacturing method of the present invention, FIGS. 2(a) to (C) are cross-sectional views of the manufacturing process of the first embodiment of the present invention, and FIGS. 3(a) to (C) 4(a) and 4(b) are perspective views of a conventional semiconductor device. In the figure, 11 is a silicon substrate, 12 is a gate oxide film, and 13 is a gate. Electrode, 14 is a spacer, 15 is a low concentration layer, 16 is a high concentration layer, 17 is a metal film, 18 is a silicon oxide film, 19 is a polycrystalline silicon film, 20 is a silicon oxide film, 21 is a phosphorous glass (PSG) film Indicates. Until the end of the year 1 Noibarasu Misaki 5, Yongsenbagamino 1 use anus 2 soroto" Ezamata 0-su 4 Princess Sansen 9 Fukuyoshi A5" 9 'Mami & 511 Tsu・7 prefectures 5 20 >1+v゛/'1itAu* 21 f to p'raz As'A<M'f:,tTue'PiP'la!J-iiIn
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Claims (2)

[Claims] (1) In a method for manufacturing an insulated gate field effect transistor having a plurality of mutually adjacent gate electrodes (13) having different work functions due to differences in impurity concentration, the plurality of gate electrodes (13) are exposed. , a process of depositing a metal film (17) on the entire surface, and heat treatment to convert the metal film (17) into a gate electrode (13).
A method for manufacturing an insulated gate field effect transistor, comprising: a step of causing a chemical reaction with a constituent material; and a step of selectively removing the unreacted metal film (17). (2) In a method for manufacturing an insulated gate field effect transistor having a plurality of mutually adjacent gate electrodes (13) having different work functions due to differences in impurity concentration, the plurality of gate electrodes (13) are exposed. , an insulated gate field effect characterized by comprising a step of selectively growing a metal film or a metal-semiconductor compound (17) only on the surface of the material constituting the gate electrode (13) by chemical vapor deposition. Method of manufacturing transistors.