JPS6228587B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor electronic device, and particularly to a method of manufacturing a semiconductor electronic device, which increases the degree of integration of circuit elements such as transistors constituting a large-scale integrated circuit, and simplifies the process.

A bipolar transistor based on planar technology has three regions: an emitter, a base, and a collector.Looking at the planar pattern, for example, the emitter is surrounded by the base, and the base is further surrounded by the collector. According to the prior art,
In forming these three regions, we had to repeatedly open a window in the surface oxide film by photoetching and diffuse impurities into the semiconductor substrate through the window, so it was difficult to align the mask when opening the window three times. It is necessary to provide dimensional margin for misalignment. Furthermore, since the electrodes from the three regions are drawn out through the respective windows, the distance between the windows must be increased in order to maintain the distance between the electrodes. As a result, the dimensions of the transistors have inevitably increased, making it difficult to increase the integration density of elements in integrated circuits. Furthermore, as the size of the transistor increases, parasitic elements such as base series resistance and inter-element parasitic capacitance also increase, resulting in deterioration of the characteristics of the transistor.

The present invention solves the above-mentioned problems of the prior art, and can achieve miniaturization of elements while ensuring sufficient mask alignment margin when forming internal regions such as transistors and forming electrodes.
An object of the present invention is to provide a method for manufacturing a semiconductor electronic device.

In order to achieve the above object, the present invention provides the following steps: (a) A first insulating material film is formed on the surface of a semiconductor substrate of a first conductivity type, and this is patterned to form a first insulating material film having one opening. a step of forming an insulating film; (b) a step of introducing a first impurity through the opening to form a first semiconductor region of a second conductivity type in the semiconductor substrate; (c) a step of forming the first insulator. a second layer on top of the membrane and said opening;
forming a first electrode material film containing impurities and a second insulating material film on the first electrode material film;
A second insulating film is formed by patterning the second insulating material film so as to have a side end surface at least above the opening, and then using the second insulating film as a mask, the first electrode material film is patterned. forming a first electrode layer containing a second impurity that is etched more toward the second insulating film than the side end surface above the opening of the second insulating film; d) A step of providing a third insulating film only on the side end surface of the first electrode layer by performing one of the following steps (i) or (ii): (i) forming an exposed portion of the opening; The surface of the semiconductor substrate, the side end surface of the first electrode layer, and the second electrode layer.
After forming a silicon oxide film covering the surface of the insulating film and implanting ions into the silicon oxide film to make it more susceptible to etching, (ii) removing the silicon oxide film except for a portion thereof by chemical etching and providing a third insulating film made of the silicon oxide film only on the side end surface of the first electrode layer; (ii) exposing the opening; the surface of the semiconductor substrate, the side end surface of the first electrode layer, and the second electrode layer.
A third insulating material film is deposited to cover the surface of the insulating film, and the third insulating material film is selectively removed by directional dry processing, thereby forming a surface of the first electrode layer on the side of the first electrode layer. (e) providing a third insulating film made of the third insulating material film only on the end face; (e) forming a second insulating film containing a third impurity so as to cover at least the exposed surface of the semiconductor substrate After forming an electrode layer or introducing a third impurity into the surface of the semiconductor substrate exposed in the opening to form a second semiconductor region having the first or second conductivity type, forming a second electrode layer so as to cover at least the surface of the semiconductor substrate where the opening is exposed; (f) diffusing the second impurity from the first electrode layer to form a surface of the semiconductor substrate; first or second
(g) When the second electrode layer contains a third impurity, a third semiconductor region is formed from the second electrode layer containing the third impurity. manufacturing a semiconductor electronic device, including the step of: diffusing impurities to form a second semiconductor region having a first or second conductivity type on the surface of the semiconductor substrate;

In the steps (a) to (f) above, the spaces between the first and second electrode layers and between the second and third semiconductor regions are formed in a self-aligned manner. In addition, adopting the above step (d) increases the degree of freedom in selecting the thickness of the third insulating film, and since the first insulating film is hardly etched, the first insulating film The initial film thickness is retained.

A detailed description will be given below with reference to the drawings.

FIG. 1 is a cross-sectional view of the emitter and base portions of a transistor according to the prior art. Although the collector generally uses an epitaxial layer, it is simply represented as an n-type semiconductor substrate 1 here.

A base region 4 is formed by introducing p-type impurities through a first opening (the edge of which is indicated by 3) formed in the first oxide insulating film 2 covering the surface of the substrate 1 by the first photoetching. A second oxide insulating film 5 is formed thereon, and an n ⁺ type impurity is introduced through a second opening (the edge of which is indicated by 6) formed in the second oxide insulating film 5 by second photo-etching. Then, the emitter region 7 is formed. Furthermore, a third opening (the edge of which is indicated by 8) for connecting the base electrode is formed in the second oxide insulating film 5 by a third photo-etching process.
Open. Then, an emitter electrode 9 and a base electrode 10 are formed so as to cover the second and third openings 6 and 8.

With this structure, the first, second, and third openings are provided in order to provide a dimensional margin against misalignment of the mask during photoetching and to maintain a distance between the emitter and base electrodes. In providing the transistors, it is necessary to set large distances between the respective edges 3 and 6, 6 and 8, and 3 and 8, making it difficult to reduce the dimensions of the transistor.

Next, the basic configuration of the present invention will be explained with reference to FIG. FIG. 2a is a cross-sectional view, and FIG. 2b is a plan view showing the pattern shape of each part. Similarly to FIG. 1, the collector region of the transistor is simply shown as the semiconductor substrate 11. In the following description, the substrate 11 will be used as a collector region, but it goes without saying that the substrate 11 will be an emitter when used as a reverse direction transistor.

In FIG. 2, reference numeral 12 indicates a first insulating film, and reference numeral 13 indicates an edge of an opening provided in the first insulating film 12. In FIG. 14
15 indicates a first electrode layer, 15 indicates a second insulating film, and 16 indicates an edge of the second insulating film. 17 is the second electrode layer, 1
8 indicates the edge of the second electrode layer. 19 is a base region, 20 is an emitter region, and 21 is a base electrode connection region.

To describe the manufacturing method of this semiconductor electronic device, a first insulating film (normal oxide insulating film) 12 is formed on the surface of an n-type semiconductor substrate 11, and a known method is applied to the first insulating film 12 as shown in FIG. One opening having a pattern shape as shown by 13 in b is provided. From this opening, the substrate 1 is exposed using the first insulating film 12 as a mask.
A base region 19 is formed by diffusing p-type impurities into the base region 19. Next, a first electrode layer 14 made of polycrystalline semiconductor that covers a part of the substrate surface extending into the opening and a part of the first insulating film 12 in the periphery, and
A second insulating film 15 is formed to cover the upper surface and side end surfaces of the electrode layer. The method for forming the first electrode layer 14 and the second insulating film 15 will be described in detail later. Thereafter, a second electrode layer 17 is formed by covering the remaining portion of the substrate surface that is not covered with the first electrode layer 14 and the second insulating film 15 and looking into the opening.
form. First electrode layer 14 and second insulating film 1
5 has a pattern shape as shown by 16 in FIG. 2b, and the second electrode layer 17 has a pattern shape as shown by 18 in FIG. 2b.

The polycrystalline semiconductor constituting the first electrode layer 14 is made to contain an n ⁺ -type impurity in advance, and the n ⁺ -type impurity is diffused into the substrate 11 by heat treatment to form the emitter region 20 . Then, a transistor is constructed by using the first electrode layer 14 as an emitter electrode and the second electrode layer 17 as a base electrode.

Preferably, the second electrode layer 17 is also made of a polycrystalline semiconductor, and a p ⁺ impurity contained therein is introduced into the substrate 1 by thermal diffusion to form a base electrode connection region as indicated by a dotted line 21 in the figure. It is recommended to form a This not only improves the ohmic contact of the base electrode, but also improves the ohmic contact between the first and second electrodes 14,
Due to impurity diffusion from both 17, a pn junction is formed in the substrate 11 in the middle.
Even if the second insulating film 15 is thin, the emitter region 20 can be prevented from coming into contact with the base electrode 17.

In the above embodiment, two electrodes, base and emitter, are connected to one
In this example, the first electrode layer 14 becomes the emitter electrode and the second electrode layer 14 becomes the base electrode.
The electrode layer 17 is adjacent to the inside of one small opening provided in the first insulating film 12 via the second insulating film 15 that covers the upper surface and side end surfaces of the first electrode layer 14. Using the first and second insulating films 12 and 15 as a mask, the second electrode layer 17 covers the remaining portion not covered by the first electrode layer 14 and the second insulating film 15 within the opening. It is provided to compensate for the Therefore, the boundary position between the electrode 14 and the electrode 17 is automatically determined only by the pattern 16 of the electrode 14 shown in FIG. 17 is the distance from the insulating film 1 covering the side end surface of the electrode 14.
Since the thickness is determined by the thickness of 5, both electrodes can be brought very close to each other. On the other hand, in the internal region of the semiconductor substrate, the base region 19 is formed by diffusion from the opening, so its position corresponds to the pattern 13 in FIG. 2b, and the emitter region 20 contains the electrode 14. Since it is formed by the diffusion of impurities, its position is determined by the patterns 13 and 16 in FIG. 2b. Therefore, the mutual positions of the internal region of the transistor and each electrode on the substrate surface are automatically aligned,
In addition, regarding the alignment of the patterns 15, 16, and 18 in the figure, a sufficiently large dimensional margin is provided regardless of the dimensions of the transistor, so that the transistor can be miniaturized. Further, while the conventional technique shown in FIG. 1 required photo-etching three times, this configuration only requires two photo-etching steps. Therefore, high density and economical integrated circuits are achieved at the same time.

Next, the method for forming the first electrode layer 14 and the second insulating film 15 necessary for carrying out the present invention will be explained in the third section.
This will be explained using figures. Figure 3 a, b, c, d are
The method is shown in the order of steps, and a shows a state in which an opening is made in the first pattern shape in the first insulating film 12 and a base region 19 is formed in the substrate 11. On top of this, a first layer such as polycrystalline silicon is applied.
an electrode layer 14 and an insulating film 15a such as a silicon oxide film covering the upper surface of the electrode layer 14;
As shown in FIG. 3, the second pattern shape is removed by etching, leaving only the second pattern shape. At this time, the side end surface of the first electrode layer 14 is etched more than the insulating film 15a. Next, as shown in c, an insulating film 15b such as a silicon oxide film is deposited using chemical means, and ions of boron, argon, nitrogen, or the like are implanted into this insulating film 15b from above. In this way, the insulating film 15b becomes susceptible to etching except for the shaded portion shown by double hatching in the figure. When the parts that are susceptible to etching are removed by chemical etching, the upper surface and side end surfaces of the first electrode layer 14 are covered with the second insulating film 15a and 16b, as shown in d. Become.

Instead of the ion implantation and chemical etching described in step c above, the insulating film 1 is processed using a directional dry process such as ion milling (a technique in which argon ions are accelerated and collided to scrape the surface).
Even if the unnecessary portion of 5b is directly removed, the second insulating film as shown in d can be formed.

Based on the above configuration, subsequent steps such as diffusing the n ⁺ impurity contained in the first electrode layer 14 into the substrate 11 to form the emitter region 20 can be performed.

FIG. 4 shows another embodiment of the present invention in which three electrodes, an emitter, a base, and a collector, are drawn out from one opening provided in the first insulating film. FIG. 4a is a sectional view, and FIG. 4b is a plan view showing the pattern shape of each part.

In this embodiment, an opening (the edge of which is shown as 13) provided in the first insulating film 12 is entered into an n-type collector region 22 formed in a p-type semiconductor substrate 11. Base region 19 is formed by performing base diffusion according to the pattern shape. Thereafter, the first
The electrode layers 14, 14' are formed as an emitter electrode and a collector electrode, and the second electrode layer 17 is formed as a base electrode. In this case, the first electrode layer is divided into two regions 14 and 14' having patterns shown as 16 and 16' with the second electrode layer 17 in between, and the upper surface and side end surface of each region are It is covered with two insulating films 15 and 15'. The emitter region 20 and the collector electrode connection region 24 are
The first electrode layers 14 and 14' are formed by diffusing n ⁺ type impurities contained in the polycrystalline semiconductor into the substrate 11. Further, the base electrode connection region 21 is formed by diffusing p ⁺ type impurities contained in the polycrystalline semiconductor constituting the second electrode layer 17 into the substrate 11. Area 21
can also be formed by introducing p ⁺ type impurities by diffusion or ion implantation from the surface prior to the formation of the second electrode layer 17.

According to this embodiment, three electrodes can be drawn out closely from one small opening provided in the first insulating film 12, so that the emitter, base, and collector electrodes are on the same plane. Certain transistors can be made extremely small. Moreover, high precision is not required for positioning the mask patterns 13, 16, 16', 18, and 23, which alleviates manufacturing difficulties associated with miniaturization.

In the embodiment shown in FIG. 4, the first electrode layer is assigned to the emitter electrode and the collector electrode, and the second electrode layer is assigned to the base electrode. However, by reversing this relationship, the first electrode layer is assigned to the base electrode. It is clear that a transistor having three adjacent electrodes can be similarly constructed by allocating the second electrode layer divided with the first electrode layer in between as the emitter electrode and the collector electrode.

As described above with respect to the embodiments, the present invention enables circuit elements such as transistors to be made extremely small by drawing out a plurality of electrodes in close proximity through one small opening provided in a surface insulating film of a semiconductor substrate. With this, it is possible to configure
High performance can also be achieved by reducing base series resistance and inter-element parasitic capacitance. moreover,
By reducing the number of masks and relaxing mask alignment accuracy, the manufacturing process is simplified, and this has an extremely large effect in promoting higher density integrated circuits.

In the present invention, a third insulating film (15 in FIGS. 2 and 4) and a third insulating film (15 in FIGS. 2 and 4) provided on the side end surfaces of the first electrode layer (14 in FIGS. 2 and 4) The thickness of the second insulating film 15 (depicted as a part of the second insulating film 15 in FIGS. 2 and 4) can be freely selected, so by increasing this film thickness appropriately, 21) in FIG. 4 and the third semiconductor region (20 in FIGS. 2 and 4) can be separated, increasing the junction breakdown voltage and reducing the junction capacitance between these semiconductor regions. be able to.

Further, in the transistor formed using the present invention shown in FIG. 2, the third semiconductor region 20 is set as p ⁺ and the first electrode layer 14 is used as the base electrode, and the second semiconductor region 21 is set as n ⁺ and is used as an emitter. However, if the manufacturing method of the present invention is used to manufacture a transistor with such a structure, the second
When forming the insulating film 15, the second electrode layer 17
Since the first insulating film at the bottom of the etching is hardly etched and has a sufficient thickness, a sufficient distance can be maintained between the collector (semiconductor substrate 11) and the emitter (second semiconductor region 21). It becomes possible to manufacture high-performance transistors that do not cause short-circuits or leaks between them.

It goes without saying that the present invention is not limited to the illustrated and described embodiments, but can be implemented with various modifications within the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a transistor according to the prior art, FIGS. b, c, d
is an explanatory diagram of the manufacturing process of the transformer shown in FIG.
FIGS. 4a and 4b are a cross-sectional view of a transistor shown as another embodiment and a plan view showing the pattern shape of each part. Explanation of symbols 11... Semiconductor substrate, 12... First insulating film, 13... Edge of opening, 14, 14'... First
electrode layer, 15, 15'... second insulating film, 16,
16'... Edge of second insulating film, 17... Second electrode layer, 18... Edge of second electrode layer, 19... Base region, 20... Emitter (collector) region, 21... Base electrode connection region, 22 ...Collector area, 23...
Edge of base region, 24... Collector electrode connection region.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor electronic device including the following steps: (a) forming a first insulating material film on the surface of a semiconductor substrate of a first conductivity type, and patterning this to form a single insulating material film; a step of forming a first insulating film having an opening; (b) a step of introducing a first impurity through the opening to form a first semiconductor region of a second conductivity type in the semiconductor substrate; c) A second insulating film on the first insulating film and the opening.
forming a first electrode material film containing impurities and a second insulating material film on the first electrode material film;
A second insulating film is formed by patterning the second insulating material film so as to have a side end surface at least above the opening, and then using the second insulating film as a mask, the first electrode material film is patterned. forming a first electrode layer containing a second impurity that is etched more toward the second insulating film than the side end surface above the opening of the second insulating film; d) A step of providing a third insulating film only on the side end surface of the first electrode layer by performing one of the following steps (i) or (ii): (i) forming an exposed portion of the opening; The surface of the semiconductor substrate, the side end surface of the first electrode layer, and the second electrode layer.
After forming a silicon oxide film covering the surface of the insulating film and implanting ions into the silicon oxide film to make it more susceptible to etching, (ii) removing the silicon oxide film except for a portion thereof by chemical etching and providing a third insulating film made of the silicon oxide film only on the side end surface of the first electrode layer; (ii) exposing the opening; the surface of the semiconductor substrate, the side end surface of the first electrode layer, and the second electrode layer.
A third insulating material film is deposited to cover the surface of the insulating film, and the third insulating material film is selectively removed by directional dry processing, thereby forming a surface of the first electrode layer on the side of the first electrode layer. (e) providing a third insulating film made of the third insulating material film only on the end face; (e) forming a second insulating film containing a third impurity so as to cover at least the exposed surface of the semiconductor substrate After forming an electrode layer or introducing a third impurity into the surface of the semiconductor substrate exposed in the opening to form a second semiconductor region having the first or second conductivity type, forming a second electrode layer so as to cover at least the surface of the semiconductor substrate where the opening is exposed; (f) diffusing the second impurity from the first electrode layer to form a surface of the semiconductor substrate; first or second
(g) When the second electrode layer contains a third impurity, a third semiconductor region is formed from the second electrode layer containing the third impurity. forming a second semiconductor region having a first or second conductivity type on the surface of the semiconductor substrate by diffusing impurities;