JPS54154966A - Semiconductor electron device - Google Patents
Semiconductor electron deviceInfo
- Publication number
- JPS54154966A JPS54154966A JP6341578A JP6341578A JPS54154966A JP S54154966 A JPS54154966 A JP S54154966A JP 6341578 A JP6341578 A JP 6341578A JP 6341578 A JP6341578 A JP 6341578A JP S54154966 A JPS54154966 A JP S54154966A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- etching
- film
- sio
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To realize miniaturization of the circuit elements by drawing out plural units of electrodes through one small opening provided on the surface film of the semiconductor substrate.
CONSTITUTION: The opening is drilled to insulator film 12 of n-type Si substrate 11 to form p-type base layer 19, and poly Si electrode layer 14 and SiO215a are laminated on layer 19. Then both layer 14 and 19 are removed by etching except for the fixed pattern-shaped area. In this case, the eaves part is formed to film 15a. After this, SiO215b is laminated, and then the B ion and the like are injected to facilitate the etching excluding the area under the eaves. Then the etching is given to make layer 15b remain at the eaves part selectively. The diffusion is then carried out through electrode layer 14 to form n+-emitter layer 20 with electrode 17 attached. In such constitution, the electrodes close to each other can be drawn out through the same opening, and as a result the circuit elements can be miniaturized. At the same time, the parasitic capacity can be reduced between the base serial resistance and the element.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6341578A JPS54154966A (en) | 1978-05-29 | 1978-05-29 | Semiconductor electron device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6341578A JPS54154966A (en) | 1978-05-29 | 1978-05-29 | Semiconductor electron device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54154966A true JPS54154966A (en) | 1979-12-06 |
JPS6228587B2 JPS6228587B2 (en) | 1987-06-22 |
Family
ID=13228627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6341578A Granted JPS54154966A (en) | 1978-05-29 | 1978-05-29 | Semiconductor electron device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54154966A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57211251A (en) * | 1981-06-23 | 1982-12-25 | Toshiba Corp | Manufacture of semiconductor integrated circuit |
JPS59217327A (en) * | 1983-05-26 | 1984-12-07 | Toshiba Corp | Manufacture of semiconductor device |
JPS62150747A (en) * | 1985-12-24 | 1987-07-04 | Rohm Co Ltd | Semiconductor device |
JPS63207154A (en) * | 1987-02-23 | 1988-08-26 | Nec Corp | Manufacture of semiconductor device |
US4980304A (en) * | 1990-02-20 | 1990-12-25 | At&T Bell Laboratories | Process for fabricating a bipolar transistor with a self-aligned contact |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3303071A (en) * | 1964-10-27 | 1967-02-07 | Bell Telephone Labor Inc | Fabrication of a semiconductive device with closely spaced electrodes |
JPS5091288A (en) * | 1973-12-12 | 1975-07-21 | ||
JPS5227355A (en) * | 1975-08-27 | 1977-03-01 | Hitachi Ltd | Diffusion layer formation method |
JPS534469A (en) * | 1977-05-26 | 1978-01-17 | Toshiba Corp | Semiconductor device |
-
1978
- 1978-05-29 JP JP6341578A patent/JPS54154966A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3303071A (en) * | 1964-10-27 | 1967-02-07 | Bell Telephone Labor Inc | Fabrication of a semiconductive device with closely spaced electrodes |
JPS5091288A (en) * | 1973-12-12 | 1975-07-21 | ||
JPS5227355A (en) * | 1975-08-27 | 1977-03-01 | Hitachi Ltd | Diffusion layer formation method |
JPS534469A (en) * | 1977-05-26 | 1978-01-17 | Toshiba Corp | Semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57211251A (en) * | 1981-06-23 | 1982-12-25 | Toshiba Corp | Manufacture of semiconductor integrated circuit |
JPS639748B2 (en) * | 1981-06-23 | 1988-03-01 | Tokyo Shibaura Electric Co | |
JPS59217327A (en) * | 1983-05-26 | 1984-12-07 | Toshiba Corp | Manufacture of semiconductor device |
JPS62150747A (en) * | 1985-12-24 | 1987-07-04 | Rohm Co Ltd | Semiconductor device |
JPS63207154A (en) * | 1987-02-23 | 1988-08-26 | Nec Corp | Manufacture of semiconductor device |
US4980304A (en) * | 1990-02-20 | 1990-12-25 | At&T Bell Laboratories | Process for fabricating a bipolar transistor with a self-aligned contact |
Also Published As
Publication number | Publication date |
---|---|
JPS6228587B2 (en) | 1987-06-22 |
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