JPS63207154A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a semiconductor integrated circuit device easily by coating the side surface of a conductive substance layer, the upper surface of a first insulating film and a surface, from which the conductive substance layer is removed selectively, with a second insulating film and uniformly getting rid of the second insulating film. CONSTITUTION:An insulating element-isolation region 102 is formed to the surface of an silicon semiconductor substarte 101, and an insulating film 105 is shaped so as to be applied onto the upper surface of a gate electrode 104 formed onto a gate insulating film 103 for an insulated gate field-effect transistor. An N<+> diffusion region 109 is shaped through the implantation of arsenic ions, an insulating film 106 is formed so as to be applied onto the side surface of the gate electrode 104, an insulating film 107 different from the insulating film 105 and the insulating film 106 by boring a window, and a wiring 108 is shaped. Consequently, the diffusion region 109 for a source and a drain and the wiring 108 are connected electrically, employing the insulating films 105, 106, 107 as interlayer insulating films. Lastly, a protective film 110 is applied, thus constituting a semiconductor element with a self-alignment type opening section. Accordingly, density can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an opening required for electrode wiring of a semiconductor element.

[Conventional technology]

Semiconductor integrated circuit devices, especially integrated circuit devices mounted on silicon semiconductor substrates, have increased in capacity as manufacturing process technology, especially microfabrication technology, advances.

Densification has progressed rapidly.

However, with the development of microfabrication technology, the pattern area margin (margin) that takes into account misalignment between circuit forming patterns at several levels during the transfer process of circuit forming patterns has become a major factor in increasing the density of integrated circuits. This has become a hindrance. This point will be explained in detail below.

Generally, in the manufacture of semiconductor devices, a known photoresist process is used to transfer a circuit formation pattern onto the surface of a semiconductor substrate.
It also includes a semiconductor surface processing step using this photoresist as a mask. In addition, here, a heavy photoresist mask is required to transfer the circuit formation pattern.
Accordingly, there are several stages of processing steps. In each of these processing steps, it is necessary to form a desired patterned pattern in a shape that matches the previous patterned pattern. However, alignment is required for transferring the circuit forming pattern, and misalignment of the pattern due to misalignment cannot be avoided. This misalignment is large (currently about 0.1 to 0.3 μm, depending on the photoresist technology).Therefore, in consideration of this misalignment, an area margin is provided between the circuit forming patterns. This areal margin is
In particular, in integrated circuits that use insulated gate field effect transistors as active elements, which are being increasingly densified, this has emerged as an impediment to the densification. Under these circumstances, the margin area between circuit formation patterns accompanying the formation of openings essential for electrode wiring of integrated circuits has become a particularly strong impediment to higher density.

Conventionally, this opening is formed by forming an insulating element isolation region 302. which is selectively formed on the surface of a silicon semiconductor substrate 301, as shown in FIG. Gate film 303 of insulated gate field effect transistor. After a glabellar insulating film 306 is formed to cover the gate electrode 304 and the source/drain diffusion region 305, openings are formed in the interlayer insulating film 306 using known photoresist phosphorography technology and etching technology. Let's do it by doing this. After this, a wiring 307 is formed and electrically connected to the diffusion region 305 to form an active element. Here, the protective film 308 is coated at the final stage to protect the semiconductor element.

In such a formation method, it is necessary to provide a sufficient area margin between the gate electrode 304 or the insulating element isolation region 302 and the opening, taking into account the misalignment in the phosphorography technique described above. For this reason, this area increases, and higher density is hindered.

[Problem that the invention seeks to solve]

In the above-mentioned conventional hole forming method, in manufacturing such an integrated circuit device, an increase in the area of the circuit forming pattern due to the hole formation required for taking out the electrodes is unavoidable.
It has the disadvantage that the layer density and miniaturization of circuit elements do not progress.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes a step of forming a conductive material layer on the entire surface of a semiconductor substrate, a step of forming a first insulating film on the conductive material layer, and a step of selecting the first insulating film. a step of selectively removing the conductive material layer using the first insulating film as a mask, and then selectively removing the side surface of the conductive material layer, the upper surface of the first insulating film, and the conductive material layer; The method includes a step of covering the surface from which the second insulating film has been uniformly removed with a second insulating film, and a step of exposing the surface from which the second insulating film has been uniformly removed.

[Example] Next, the present invention will be explained with reference to the drawings. Figure 1-a shows a sectional view of a semiconductor device according to a first embodiment of the present invention, and Figures ib and・Figure 1-i is the first diagram of the present invention.
FIG. 3 is a cross-sectional view of the main manufacturing process of the semiconductor device according to the embodiment.

An insulating element isolation region 1 is formed on the surface of a silicon semiconductor substrate 101.
02 is formed, and an insulating film 105 is formed to cover the upper surface of the gate electrode 104 formed on the gate insulating film 103 of the insulated gate field effect transistor (Figures ib-b), and then an n diffusion region is formed by arsenic ion implantation. 1-c to 1-d), and then an insulating film 106 is formed to cover the side surface of the gate electrode 104 (FIGS. 1-e to 1-d).
Figures 1-f). After doing so, the insulating film 105 and the insulating film 10
An insulating film 107 different from 6 is formed with a window opening.
Figure 1-g, Figure 1-h), and wiring 108 is formed (Figure 1-h).
Figure i). In this way, the source/drain diffusion regions 109 are
and wiring 108 are electrically connected. Finally, the protective film 110
A semiconductor device having self-aligned openings is constructed. In the first embodiment, it is a cross-sectional view showing a manufacturing process in which the opening portion is formed so as to self-fit into the pattern of the insulating element isolation region 102 and the gate electrode 104.

As shown in FIG. 4, a silicon oxide film 402 for a gate film is formed on the surface of a P-type silicon substrate 401 to a thickness of 100 to 200 nm.
After forming by thermal oxidation method to form A, polysilicon,
After depositing a conductive film 403 made of polycide or high-melting point metal by sputtering or CVD, an insulating film 404 made of silicon oxynitride or the like is deposited to a thickness of 2000 to 2000 nm.
4000-A, approximately formed.

Next, as shown in Figure 5, photoresist is applied using the known Lingraph 1 technology! 405 as a mask, the lower insulating film 404.
After dry etching the conductive film 403 and removing the photoresist layer 405 used as an etching mask as shown in FIG.
An n diffusion region 407 is formed by implanting under the condition of 0 ions/d. Subsequently, as shown in FIG. 7, the insulating film 408 is formed to a thickness of 2000 to 500 using the CVD method with good step coverage.
It accumulates about 0A. Here, the insulating film 408 may be made of silicon oxynitride made of the same material as the insulating film 404, or may be any other insulating film.

After this, the insulating film 408 is etched by a highly anisotropic dry etching method until the insulating film 1408 on the center of the n+ diffusion region 407 is removed. Because of this highly anisotropic etching, the conductive film 403 and the insulating film 40
4, as shown in FIG.
Ru.

Subsequently, as shown in FIG. 9, an insulating film 409 is formed to a thickness of about 400 OA by CVD or coating. Here, the insulating film 409 needs to be of a different type from the insulating films 404 and 408. For example, when the insulating films 404 and 408 are made of silicon oxynitride film,
Insulating film 40 with silicon oxide film or silicon nitride film
9 should be formed.

Next, as shown in FIG. 1θ, etching is performed using the photoresist layer 410 as a mask to selectively remove the insulating film 409. This window opening can be done by dry etching or wet etching. However, the insulating films 404, 40
It is necessary to use a film having a low etching rate for the insulating film 409 and a high etching rate for the insulating film 409. For example, when the insulating films 404 and 408 are silicon oxynitride and the insulating film 409 is a silicon oxide film, ammonium fluoride or chloride may be used as the wet etching chemical. In the case of dry etching, a halogenated hydrocarbon gas containing iodine or bromine may be used. The opening formed in this insulating film 409 is absolutely RK 4
This is for connecting to the n+ diffusion region 407 through the opening surrounded by 08, and high accuracy is not required for alignment.

In this way, the insulating film 409 in the opening is removed 5, and the insulating film 409 of the silicon oxide film 402 for the thin gate film is further removed.
(After removing the enclosed portion, a wiring 411 is formed of aluminum or the like as shown in FIG. 1I.

In this way, the previously transferred circuit forming pattern, i.e.
The n-diffusion region 407 and the wiring 411 are electrically connected through self-aligned openings that are automatically formed in the pattern of the conductive film 403 which becomes the gate electrode of the insulated gate field effect transistor.

FIG. 19 is a cross-sectional view showing the main manufacturing process of a semiconductor device according to the third embodiment of the invention. As shown in FIG. 2, as in the first embodiment shown in FIG. 1, an insulating element isolation region 202 is formed on the surface of a silicon semiconductor substrate 201. Gate 3203 of an insulated gate field effect transistor. Gate electrode 204, insulating film 205. An insulating film 206 is formed, and a thin conductive film is formed on a part of the insulating element isolation region 202 and insulating film 2.
05, 206 is formed in such a manner as to cover part of it. An insulating film 208 different from the insulating films 205 and 206 is a thin conductive film 2.
07 is formed with a window opening provided in the upper part, and wiring 209 is provided.

In this way, the insulating films 205, 206, and 207 are used as interlayer insulating films to connect the source/drain diffusion regions 210 and the wiring 209.
are electrically connected via a thin conductive film 207. Finally, a manufacturing method of an embodiment of a semiconductor element covered with a protective film 211 and having self-aligned openings will be described.

As shown in FIG. 12, a thick silicon oxide film is selectively formed on the surface of a P-type silicon substrate 201 by thermal oxidation to form an insulating element isolation region 202, and then a silicon oxide film 203 for a gate is formed. Conductive film 204. An insulating film 205 is formed.

Here, these film thicknesses may be the same as the values described in the case of the second embodiment.

Next, as shown in FIG. 13, the insulating film 205 is formed using the photoresist layer 506 as a mask using a known lithography technique. After etching the metal thin film 204, as shown in FIG.
It is formed in the same manner as in the embodiment.

Next, as shown in FIG.
Anisotropic dry etching is performed so that the insulating film 206 remains on the sidewalls of the wafer 05. After exposing the surface of the n+ diffusion region 210 in this way, as shown in FIG. 16, a thin conductive layer such as a polysilicon thin film layer with a thickness of 500 to 1000 A containing n-type emissive impurities or a thin film layer containing a high melting point metal is formed. sexual membrane 207
From the surface of the exposed nl diffusion region 210, on the insulating film 206 and the insulating film 205, and further on the insulating element isolation region 2.
It is formed by patterning so as to extend over 02. After this, as shown in FIG. 17, an insulating film 208 is deposited or applied over the entire surface, and as shown in FIG. 18, only the area on the thin conductive film 207 is selectively removed using the photoresist 511 as a mask to open a window. After that, wiring 209 is formed as shown in FIG.

In this embodiment as well, a self-aligned type circuit is automatically formed using the previously transferred circuit formation pattern, that is, the pattern of the insulating element isolation region 202 and the conductive film 204 that becomes the gate electrode of the insulated gate field effect transistor. The n+ diffusion region 210 and the wiring 209 are electrically connected through the opening.

Here, the thin conductive film 207 serves as an etching buffer when opening a window in the third insulating film 208 in the step shown in FIG.
02, the insulating film 205, and the surface of the insulating M2O6 from being etched. Furthermore, when aluminum is used for the wiring 209, the wiring 209
It also has a movement that allows the n+ diffusion region 210 to connect normally.

〔Effect of the invention〕

As explained above, the present invention can easily form a self-aligned hole in which the hole required for taking out the electrode can be automatically formed using the circuit formation pattern transferred in the previous process. This eliminates the need for an area margin that takes into account misalignment, and has the effect of facilitating higher integration of semiconductor integrated circuit devices.

[Brief explanation of the drawing]

Figure 1-a is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention, Figure 1-b is a cross-sectional view showing the main manufacturing process of the first embodiment of the present invention, and Figure 1-i is a cross-sectional view showing the main manufacturing process of the first embodiment of the present invention. 2 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention, FIG. 3 is a cross-sectional layer diagram of a conventional semiconductor device, and FIGS. 12 to 19 are cross-sectional views showing the main manufacturing steps of the third embodiment of the present invention. 101.201.301...Silicon semiconductor substrate. 102, 202.302... Insulating element isolation region. 103, 203. 303...Gate film. 104, 204.304...Gate electrode. '105.205...Insulating film, 108.20G...
・Insulating film. 107, 208... Insulating film, 207... Thin conductive film. 108, 209.307...Wiring. 109, 210.305...diffusion area, 306...
Interlayer insulation film. 110, 211.308...Protective film. 401...P-type silicon substrate. 402... Silicon oxide film, 403... Conductive film. 404... Insulating film, 405.50G... Photoresist layer. 406...Arsenic ion, 407...n+' diffusion region. 408... Insulating film, 409... Insulating film. 410, 511... Photoresist layer, 411... Wiring. Agent Patent Attorney Susumu Uchihara 1/Mine 1-cL Figure Half 2V Graduation 1-d (2) Mine IJ + Haruka 1-e
Note Half 1-L January Tsukimine 3zo

Claims (1)

[Claims] forming a conductive material layer on one main surface of the semiconductor substrate;
forming a first insulating film on the conductive material layer; selectively removing the first insulating film; and selectively removing the conductive material layer using the first insulating film as a mask. removing the conductive material layer, and then covering the side surfaces of the conductive material layer, the upper surface of the first insulating film, and the surface from which the conductive material layer has been selectively removed with a second insulating film; The second insulating film is uniformly removed to cover the side surfaces of the conductive material layer with the second insulating film, and the surface from which the conductive material layer is selectively removed is exposed. A method for manufacturing a semiconductor device.