JPH02156542A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a second conducting layer to be formed uniformly for stabilizing electrical characteristics by forming the second conducting layer selectively on the face of a first conducting layer exposed in an opening formed in a thick interlayer insulating film. CONSTITUTION:A first conducting layer 16 is provided on a doped regions 12, 15 serving as source and drain regions of a transistor. A second conducting layer 17 is formed selectively on the face of the first conducting layer 16 exposed in an opening 6, formed in a thick interlayer insulating film 5. Accordingly, the second conducting layer 17 can be formed uniformly and a semiconductor device with stable electrical characteristics can be obtained. Further, the doped regions 12, 15 can be protected by the first conducting layer 16 present thereon during formation of the contact hole 6. In this manner, the doped regions can be connected with a wiring layer through the uniform and electrically stable, conducting layer.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to a semiconductor device that improves the characteristics of a conductive layer that connects an impurity region and a wiring layer formed thereon. The present invention relates to a semiconductor device and its manufacturing method.

[Prior Art] FIG. 3 shows an example of a conventional MOS (MetaI).
Oxide Sem1 conductor) FET (
Field Effect Transistor
) is a cross-sectional view of. In this MOS FET, a plug 7 made of tungsten is used to connect a wiring layer 8 formed on an interlayer insulating film 5 and an impurity region 4 . Next, a method for manufacturing the MOS FET shown in FIG. 3 will be explained.

An oxide film (not shown) for element isolation is formed on the semiconductor substrate 1 using, for example, the LOCO9 method. Next, an insulating film 2 is formed in the element formation region of the semiconductor substrate 1 by thermal oxidation or CVD, and then, for example, carbon dioxide is formed on the insulating film 2.
For example, a polysilicon film is formed using the VD method, and then an insulating film is formed on the polysilicon film. Next, it is patterned into a predetermined shape using photolithography and etching. This forms the gate electrode 3 of the transistor.

Next, sidewalls are formed on the sidewalls of the gate electrode 3. Next, impurity ions are implanted using the gate electrode 3 as a mask, and are activated to form an impurity region 4. Next, a thick interlayer insulating film 5 is formed over the entire surface of the substrate, and a predetermined region of the interlayer insulating film 5 is removed using, for example, a dry etching method to form a contact hole 6.

Next, for example, tungsten is deposited in the contact hole 6 by a CVD method to form a plug 7. next,
A conductive layer is formed on the plug 7 and patterned into a predetermined shape. As a result, a wiring layer 8 electrically connected to the plug 7 is formed.

[Problems to be Solved by the Invention] The crystals of the plug 7 made of tungsten in the conventional MOS FET are formed in a columnar shape, so there is a problem that the film quality is not uniform and the electrical characteristics are unstable. Ta. This instability becomes more pronounced as the thickness of the interlayer insulating film increases, so it has not been possible to increase the thickness of the interlayer insulating film beyond a certain level.

Therefore, the main object of the present invention is to provide a semiconductor device and a method for manufacturing the same, in which an impurity region and a wiring layer are connected by a conductive layer that is uniform in film quality and electrically stable. .

[Means for Solving the Problems] A semiconductor device according to the present invention includes an element isolation region formed on the surface of a semiconductor substrate, a gate electrode formed on the semiconductor substrate surface with a space from the element isolation region, and an element isolation region formed on the surface of the semiconductor substrate. an impurity region formed on the surface of the semiconductor substrate between the region and the gate electrode; a first conductive layer formed at least partially in contact with the impurity region; and a first conductive layer formed on the first conductive layer.
a second conductive layer selectively formed on the exposed surface of the first conductive layer in the opening of the interlayer insulating film; It is composed of:

The method for manufacturing a semiconductor device according to the present invention includes the steps of forming an element isolation region in a predetermined region on the surface of a semiconductor substrate, and forming a gate insulating film and a gate electrode in a region surrounded by the element isolation region on the surface of the semiconductor substrate. and,
forming an impurity region between the gate electrode and the element isolation region; and coating the entire surface of the substrate with a conductive film and patterning to form a first conductive layer at least partially in contact with the impurity region. , a step of covering the entire surface of the substrate with an interlayer insulating film and forming an opening reaching the first conductive layer; and selectively applying a second conductive layer only to the exposed surface of the first conductive layer in the opening of the interlayer insulating film. forming a conductive layer.

[Function] In the present invention, the first conductive layer is provided on the impurity regions that are the source/drain regions of the transistor, and the first conductive layer is provided on the exposed surface of the first conductive layer in the opening provided in the thick interlayer insulating film. Since the second conductive layer was selectively formed,
The second conductive layer is uniformly formed, and a semiconductor device with stable electrical characteristics can be obtained.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a MOS FET according to an embodiment of the present invention. In FIG. 1, field oxide films 1 for element isolation are formed on a semiconductor substrate 1 at predetermined intervals.
0 is formed. In the element formation region between the field oxide films 10, a gate electrode 3 is formed via the gate insulating film 2, and on the surface of the semiconductor substrate 1 between the gate electrode 3 and the field oxide film 10, a relatively large Low concentration impurity diffusion layer 12
and a relatively high concentration impurity diffusion layer 15 are formed.

Such a structure is LDD (Lightly D
This is known as an open drain structure.

The low concentration impurity diffusion layer reduces the electric field strength near the drain and prevents hot electrons from being generated.

When the channel length is shortened, the electric field strength becomes stronger, but L
If the DD structure is adopted, the generation of hot electrons is prevented for the above-mentioned reasons, so the channel length can be shortened and it is suitable for miniaturization.

The first conductive layer 16 is in contact with the impurity diffusion layer 12.15,
and - a sidewall 14 whose one end extends over the field oxide film 10 and whose other end is formed on the sidewall of the gate electrode 3;
It is formed so as to extend onto the insulating film 11 formed on the gate electrode 3. A thick interlayer insulating film 5 is formed on the first conductive layer 16. The thickness of this interlayer insulating film 5 is, for example, 0. It is 5 to 3 μm. A second conductive layer 17 is formed in the opening 6 of the interlayer insulating film 5.
A wiring layer 18 is formed on the conductive layer 17 .

Figures 2A to 2G are shown in Figure 1.
FIG. 3 is a cross-sectional view for explaining the manufacturing method of ET step by step. Next, a manufacturing method according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2G.

Referring to FIG. 2A, impurity ions are implanted, for example, into the element isolation region of P-type semiconductor substrate 1. Referring to FIG. Next, a silicon oxide film (not shown) is formed on the entire surface of the semiconductor substrate 1 by thermal oxidation.
Then, a silicon nitride film (not shown) is formed on the silicon oxide film using a low pressure CVD method. next,
The silicon nitride film in the element isolation region is removed by dry etching, and then a field oxide film 10 made of a thick silicon oxide film is formed in the element isolation region using a thermal oxidation method. Through this step, an impurity region 101 for channel stop is formed under the field oxide film 10. The concentration of this impurity region is approximately 1016 to 10"
cm-”.

Next, referring to FIG. 2B, several tens to 200 gate insulating films 2 are formed over the entire surface of the substrate using the CVD method or thermal oxidation method.
After forming the doped polysilicon to a thickness of A, the doped polysilicon that will become the gate electrode 3 is heated to a thickness of approximately 1000 to 3000 A using the CVD method.
Form to a certain thickness. Doped polysilicon is n”+
Either p+ may be used. Next, an insulating film 11 such as a nitride film is deposited on the doped polysilicon film by using the CVD method.
After forming it to a thickness of 000 to 3000 Å, it is patterned into a predetermined shape by dry etching. As a result, a transfer gate 20 as shown in FIG. 2B is formed. Next, impurity ions are implanted using the gate electrode 3 as a mask, and heat treatment is performed to form a relatively low concentration impurity diffusion layer 12.

Next, referring to FIG. 2C, an insulating film 13 is formed on the entire surface of the substrate to a thickness of about 1000 to 3000 Å using the CVD method, and then anisotropic etching is performed to form sidewalls of the gate electrode 3. Wall 14 remains.

Next, referring to FIG. 2D, impurity ions are implanted using sidewall 14 and gate electrode 3 as masks, and heat treatment is performed to form relatively high concentration impurity diffusion layer 15 in a self-aligned manner.

Next, referring to FIG. 2E, a first conductive layer 16 such as doped polysilicon, metal, or silicide film is formed over the entire surface of the substrate. The film thickness will be approximately 500 to 2,000 people.

Next, a predetermined region of the first conductive layer 16 located on the gate electrode 3 is removed by etching. As a result, the first conductive layer 16 is formed over a wide range from above the gate electrode 13 to above the field oxide film 10.

Next, referring to the m2F diagram, an interlayer insulating film 5 is formed on the entire surface of the substrate using the CVD method to a thickness of 5,000 to 3,000 OA, and a contact hole 6 is formed using an anisotropic etching method.
form.

As described above, since the first conductive layer 16 is formed over a wide range, even if the formation position of the contact hole 6 is slightly shifted, it will not be removed from the first conductive layer 16.

That is, if the first conductive layer 16 is not present and the contact hole is formed out of position, a short circuit will occur between the gate electrode 3 and the second conductive layer 17 as shown in FIG. However, as in this embodiment, the first conductive layer 16
If you set , this will not happen.

Further, even if etching is performed somewhat excessively when forming the contact hole 6, the presence of the first conductive layer 16 protects the impurity diffusion layers 12 and 15 existing therebelow.

Next, referring to FIG. 2G, a second conductive layer 17 made of tungsten is selectively formed on the first conductive layer 16 in a self-aligned manner using, for example, a CVD method using a silane reduction method. . The second conductive layer 17 is used as a plug.

The second conductive layer 17 is not limited to tungsten.
Other metals such as O, TiSi2, etc. may also be used.
A silicide such as TaSi2 may be used. Since the crystals of the second conductive layer are uniformly formed due to the presence of the first conductive layer, the electrical characteristics are stable even if the interlayer insulating film is thick.

Next, a wiring layer 18 is formed on the second conductive layer 17, and the MO3FET shown in FIG. 1 is obtained.

Note that in the above embodiment, the LOCO8 method is used for element isolation, but a method using an electrostatic shielding electrode may also be used.

The method using an electrostatic shielding electrode does not require an impurity region as a channel stopper. Therefore, impurities do not seep out from this portion into the source/drain region or the channel, resulting in the effect that the threshold voltage of the transistor is stabilized.

Further, in the above embodiment, impurity ions are implanted into the exposed surface of the semiconductor substrate 1 to form the impurity diffusion layer 15, but the impurity ions are not limited to this, and may be implanted from above the first conductive layer 16.

Further, in the above embodiment, the second conductive layer 17 and the wiring layer 18 are formed separately, but they may be formed at the same time, and then the wiring is patterned.

In the above embodiments, a P-type substrate has been described, but a P-well may be used, and an N-type substrate or an N-well can be similarly applied. The gate of the transistor may have a polycide structure, or may be formed by a method in which impurity diffusion layers in the source and drain regions are implanted only once.

[Effects of the Invention] As described above, according to the present invention, the first conductive layer is provided on the impurity region that is the source/drain region of the transistor, and the first conductive layer is formed in the opening provided in the thick interlayer insulating film.
Since the second conductive layer is selectively formed on the exposed surface of the conductive layer, the second conductive layer is uniformly formed, and a semiconductor device with stable electrical characteristics can be obtained. Furthermore, since the first conductive layer is present on the impurity region, even if excessive etching is performed when forming a contact hole, the impurity region underneath is protected.

Furthermore, if the first conductive layer is provided over a wide area,
Even if the position of the contact hole is slightly shifted, contact with the impurity region can be made normally. Therefore, it is possible to manufacture semiconductor devices with high yield.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an MO3FET according to an embodiment of the present invention. FIGS. 28 to 2G are cross-sectional views for explaining the method for manufacturing the MO3FET shown in FIG. 1 step by step. FIGS. 3 and 4 are cross-sectional views showing conventional semiconductor devices. In the figure, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode, 5 is an interlayer insulating film, 10 is a field oxide film, 12 and 15 are impurity diffusion layers, 14 is a side wall, and 16 is a first conductive film. 17 is a second conductive layer, and 18 is a wiring layer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) an element isolation region formed on the surface of a semiconductor substrate; a gate electrode formed on the surface of the semiconductor substrate at a distance from the element isolation region; and the semiconductor between the element isolation region and the gate electrode. an impurity region formed on a substrate surface; a first conductive layer formed at least partially in contact with the impurity region; and an electrical connection between the first conductive layer and the first conductive layer formed on the first conductive layer. an interlayer insulating film having an opening for making a physical connection; and a second conductive layer selectively formed on the exposed surface of the first conductive layer in the opening of the interlayer insulating film.
Semiconductor equipment. (2) forming an element isolation region in a predetermined region on the surface of the semiconductor substrate; forming a gate insulating film and a gate electrode in a region surrounded by the element isolation region on the surface of the semiconductor substrate; and the gate electrode forming an impurity region between the substrate and the element isolation region; coating the entire surface of the substrate with a conductive film and patterning it to form a first conductive layer at least partially in contact with the impurity region; coating the entire surface of the substrate with an interlayer insulating film and forming an opening reaching the first conductive layer; and selectively applying a second conductive layer only to the exposed surface of the first conductive layer in the opening of the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: forming a conductive layer.