JP2001024065A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a gate electrode of each of MOS transistors is made of a metal or metallic compound, which can easily adjust threshold voltages of the transistors separately. SOLUTION: In the semiconductor device, a pMOS transistor and nMOS transistor are provided on an identical semiconductor substrate, and gate electrodes of the MOS transistors are made of a metal or metallic compound. A gate electrode 47 of the pMOS transistor and a gate electrode 42 of the nMOS transistor are made of materials having different work functions, respectively. The material of the gate electrode 47 of the pMOS transistor is larger in work function than that of the gate electrode 42 of the nMOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a gate electrode is formed by embedding a metal material, and more particularly, by embedding a metal material having a different work function into a gate electrode of a plurality of types of MOS transistors. The present invention relates to a semiconductor device and a method of manufacturing the same, which facilitate control of a threshold value between MOS transistors.

[0002]

2. Description of the Related Art MOS (Metal Oxide Semiconductor)
2. Description of the Related Art In a semiconductor device including a field-effect transistor (hereinafter, referred to as a MOSFET) and the like, the element size and the like continue to be miniaturized according to the so-called scaling law in semiconductor manufacturing. However, as the device size becomes smaller and smaller, problems such as deterioration of subthreshold region characteristics due to a short channel effect, influence of device delay time due to increase in parasitic resistance and parasitic capacitance effects, increase in power consumption, and the like. Has become apparent.

One of the problems associated with miniaturization is the limitation of using a silicon oxide film as a gate insulating film. That is, although thinning of the gate insulating film is one of the important technologies for improving the performance of the device, for example, when the gate insulating film is formed of a silicon oxide film having a thickness of 3 nm or less, the transistor by the direct tunnel current is used. Leakage current is generated, and practicality is impaired.

As one of measures for avoiding such inconvenience, a gate insulating film is formed of a material having a higher dielectric constant than a silicon oxide film, that is, a high dielectric material such as Ta ₂ O ₅ or SiN. While reducing the effective oxide film thickness,
A method for reducing a gate leak current has been proposed.

However, when a high dielectric film made of such a high dielectric constant material is used as a gate insulating film, for example, RTA (10
(00 ° C., 10 seconds), a high-temperature heat process of heating the semiconductor substrate at a high temperature causes the high-dielectric film to react with silicon or a silicon oxide film, thereby deteriorating the high-dielectric film, Problems such as gate leak and oxide film reliability occur.

Another problem associated with miniaturization is an increase in the delay time of the device due to the resistance component of the gate electrode. That is, although the gate resistance is conventionally reduced by a compound of silicon and a refractory metal such as tungsten silicide, titanium silicide, or cobalt silicide, the device of 0.13 μm or later has a gate sheet resistance of 5Ω / □ or less. Is required, it is necessary to use a metal film for part or all of the gate electrode.

When a metal is used for all of the gate electrodes, usually, a metal for the gate electrode is formed and then patterned to form a gate electrode. The metal film is patterned (processed) by RIE (reaction). In this case, it is difficult to obtain a sufficiently high selectivity between the metal film and the underlying gate insulating film, and it is difficult to process the gate electrode in a good state.

In the source and drain regions of the MOSFET, ions are implanted in a self-aligned manner using the gate as a mask, and then a high-temperature thermal process for activation is performed. The metal constituting the gate electrode reacts with the gate insulating film, and the reliability of the gate insulating film deteriorates.

In recent years, buried gate electrodes have been proposed in order to solve the above-described problems associated with the miniaturization of the element size. In order to form a buried gate electrode, first, a dummy gate pattern (hereinafter, referred to as a dummy gate pattern) is formed in a region where a gate electrode is to be formed on a semiconductor substrate. The active region is formed by self-alignment. Next, an interlayer insulating film is formed, and subsequently, a gate insulating film is formed at the bottom or at the bottom of the recess formed by selectively removing the dummy gate pattern.
Thereafter, a gate electrode material is buried in the recess, and CM
A buried gate electrode is formed by performing P method (chemical mechanical polishing method) or etch back.

Therefore, in such a process of manufacturing a buried gate electrode, the processing of the metal film for manufacturing the gate electrode is performed without using RIE, so that the gate electrode can be processed in a good state. After performing a high-temperature thermal process for activating the source and drain, a new gate insulating film and a buried gate electrode are manufactured. Therefore, the metal constituting the buried gate electrode reacts with the gate insulating film to form a gate. Inconvenience such as deterioration of reliability of the insulating film can be avoided.

An example in which a conventional method of forming a buried gate electrode is applied to a method of manufacturing a CMOS transistor will be described with reference to FIGS. In this example, the p-type MOS transistor manufacturing process and the n-type M
Since the manufacturing process of the OS transistor is almost the same, the manufacturing process of the p-type MOS transistor is omitted in FIGS. 7 to 9 and only the manufacturing process of the n-type MOS transistor is shown.

First, as shown in FIG. 7A, an element made of a silicon oxide film is formed on an n-type or p-type silicon substrate (not shown) by a trench method, a LOCOS (Local Oxidation of Si) method or the like. An isolation layer 1 is formed to define an active region and a field region. Next, a p-type semiconductor well 2 is formed in an active region to be an n-type MOS transistor on the silicon substrate, and an n-type semiconductor well (not shown) is formed in an active region to be a p-type MOS transistor on the silicon substrate.

Next, as shown in FIG. 7B, a silicon oxide film 3 is formed on the surface of the silicon substrate for protecting the underlayer by etching. Subsequently, polysilicon is deposited to a thickness of about 200 nm by a CVD method for forming a dummy gate pattern electrode, and a polysilicon film 4 is formed. Next, as shown in FIG. 7C, a photoresist pattern 5 is formed on the polysilicon film 4 by photolithography and development processing, and then the polysilicon film 4 is formed using the resist pattern 5 as a mask. RIE
Anisotropic etching is performed by (Reactivi Ion Etching) to form a dummy gate pattern 6 as shown in FIG.

Next, as shown in FIG. 7 (5), low concentration impurities are implanted into the diffusion region by an ion implantation method.
The low concentration diffusion region 7 in the DD structure is formed. For example, in the region of the n-type MOS Totanjisuta, arsenic ions are implanted to form the lightly doped regions 7 under conditions of implantation energy 10 keV, and a dose of 8 × 10 ¹⁴ pieces / cm ^2, also, p-type MOS transistor The region has an implantation energy of 10 keV and a dose of 4 × 10 ¹⁴ / cm ^2.
Then, boron difluoride (BF ₂ ⁺ ) is ion-implanted to form a low concentration diffusion region (not shown).

Next, as shown in FIG. 8 (6), RT
A is performed, for example, at 950 ° C. for 10 seconds to diffuse the impurities in the low concentration diffusion region 7. According to such an RTA, the impurities naturally diffuse in the lateral direction, so that the RTA
The later low concentration diffusion region 7 is partially extended to just below the dummy gate pattern 6.

Next, SiN or SiO ₂ is deposited and deposited on the silicon substrate by the CVD method, and then this film is etched back, as shown in FIG. A gate sidewall 8 serving as a mask is formed. Next, as shown in FIG. 8 (8), a high concentration impurity is implanted into the diffusion region by an ion implantation method to form a high concentration impurity region 9 serving as a source / drain region of the transistor. For example, the implantation energy of 50 ke
V, arsenic is ion-implanted under the conditions of a dose of 3 × 10 ¹⁵ / cm ² to form a high-concentration impurity region 9.
In the OS transistor region, the implantation energy is 20 k
Boron difluoride is ion-implanted under conditions of eV and a dose of 3 × 10 ¹⁵ / cm ² to form a high-concentration impurity region (not shown).

Next, as shown in FIG. 8 (9), RT
A is performed, for example, at 1000 ° C. for 10 seconds to activate the impurities in the high concentration diffusion region 9. Next, as shown in (10) of FIG. 8, an interlayer insulating film 10 is formed to cover the dummy gate pattern 6 and the sidewalls 8.
Here, when SiN is used as the sidewall 8 and SiO ₂ is used as the interlayer insulating film 10, the sidewall 8 not only functions as a mask for forming the source / drain, but also serves as a contact hole in the active region. ,
That is, it becomes an etching stop layer when forming a contact hole for connecting the source / drain region and the upper metal wiring, and prevents contact between the conductive material embedded in the contact hole and the side wall of the gate electrode.

Next, the interlayer insulating film 10 is formed by the CMP method.
Is polished to expose the upper surface of the dummy gate pattern 6 as shown in FIG. Next, the dummy gate pattern 6 is selectively etched by an etching method, such as RIE or wet etching, which can obtain a selectivity between the dummy gate pattern 6 and the interlayer insulating film 10, and the dummy gate pattern 6 is removed. Subsequently, the silicon oxide film 3 located under the dummy gate pattern 6 is removed,
As a result, the concave portion 11 is formed at the place where the dummy gate pattern 6 is formed, as shown in FIG.

Next, for example, Ta ₂ O is formed by CVD.
₅ is deposited, and an insulating film 12 is formed on the interlayer insulating film 10 so as to cover the bottom and side surfaces of the concave portion 11 as shown in FIG. Instead of forming the insulating film 12, a SiO ₂ film may be formed on the bottom surface of the concave portion 11, that is, on the silicon substrate surface by, for example, a thermal oxidation method.

Next, as shown in FIG.
A gate electrode material is formed on the insulating film 12 by a VD method, a sputtering method, or the like, and a gate electrode film 13 is formed. As the gate electrode material, W, Al, Cu, WN, T
A metal such as iN or Ta, a metal nitride, or polysilicon is used. Next, the interlayer insulating film 1 is formed by the CMP method.
The gate electrode film 13 and the insulating film 12 are polished and the gate electrode film 13 and the insulating film 12 are left only in the concave portion 11 as shown in FIG. An insulating film 12a is formed. Thereafter, an interlayer insulating film (not shown) is laminated, and further, a contact for connecting the wiring and the transistor portion is opened to complete a normal wiring process, thereby obtaining a semiconductor device.

[0021]

However, in such a conventional method, since the same gate electrode material is used for the nMOS region and the pMOS region in the MOSFET, for example, the threshold voltage of each MOSFET is reduced. Control must be performed, for example, by the concentration of impurities introduced into the silicon substrate. Therefore, it has been difficult to easily and easily adjust both the threshold voltages of the nMOS and the pMOS.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a plurality of MOs on the same substrate.
In a semiconductor device having an S transistor and a gate electrode of these MOS transistors formed of a material made of a metal or a metal compound, the threshold voltage of each transistor is separately and easily adjusted.
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

[0023]

Means for Solving the Problems Claim 1 of the present invention
In the described semiconductor device, a pMOS transistor and an nMOS transistor are provided on the same semiconductor substrate.
In a semiconductor device in which a gate electrode of an OS transistor is formed of a material made of a metal or a metal compound, pM
The gate electrode of the OS transistor and the gate electrode of the nMOS transistor are made of materials having different work functions.
The solution to the above problem is that the gate electrode of the pMOS transistor is formed of a material having a larger work function than the gate electrode of the OS transistor.

According to this semiconductor device, since the gate electrode of the pMOS transistor is formed of a material having a larger work function than the gate electrode of the nMOS transistor, threshold control of both the nMOS and the pMOS is easy. become.

According to a third aspect of the present invention, a first MOS transistor and a second MOS transistor of the same conductivity type are provided on the same semiconductor substrate, and the gate electrodes of these MOS transistors are made of a metal or a metal compound. In the formed semiconductor device, the first MOS transistor and the second MOS transistor have different threshold voltages because their gate electrodes are made of materials having different work functions. Means.

According to this semiconductor device, the first MOS transistor and the second MOS transistor have different threshold voltages because their gate electrodes are made of materials having different work functions. In addition, the threshold voltage can be easily adjusted by the material of the gate electrode without controlling the threshold voltage only by the concentration of the impurity introduced into the substrate as in the related art.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a gate pattern in each of a pMOS transistor formation region and an nMOS transistor formation region on a semiconductor substrate, and masking these gate patterns. Implanting impurities into each of the pMOS transistor formation region and the nMOS transistor formation region to form an electrically active region; and forming an electrically active region, and forming a sidewall made of an insulating film on a sidewall of the gate pattern. Forming, selectively removing the gate pattern after forming the sidewall, forming a gate insulating film at the bottom of a recess formed by removing the gate pattern, forming the nMOS transistor. Within the recess in the region, A first material made of a metal or a metal compound is buried to cover the gate insulating film to form a gate electrode, and a metal is formed in the recess in the pMOS transistor formation region by covering the gate insulating film in the recess. Alternatively, the present invention provides a means for solving the above-mentioned problem, comprising: embedding a second material made of a metal compound and having a higher work function than the first material to form a gate electrode.

According to this method of manufacturing a semiconductor device, pM
In the concave portion of the OS transistor formation region, a second metal or metal compound covering the gate insulating film in the concave portion is formed.
To form a gate electrode, and the second material has a higher work function than the first material embedded in the concave portion of the nMOS transistor formation region. nMO
Threshold control of S and pMOS becomes easy.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate pattern in each of the first MOS transistor formation region and the second MOS transistor formation region on the semiconductor substrate is provided.
A step of implanting impurities into each of the first MOS transistor formation region and the second MOS transistor formation region using these gate patterns as masks to form an electrically active region; A step of forming a sidewall made of an insulating film, a step of selectively removing the gate pattern after the formation of the sidewall, and a step of forming a gate insulating film at the bottom of a concave portion formed by removing the gate pattern Forming a first electrode made of a metal or a metal compound in the concave portion of the first MOS transistor formation region so as to cover a gate insulating film in the concave portion, thereby forming a gate electrode, and forming the second MOS transistor A metal is formed in the recess in the formation region by covering the gate insulating film in the recess. Rui embed different second work function material and the first material consists of a metal compound,
And a step of forming a gate electrode.

According to this method of manufacturing a semiconductor device, the second
Forming a gate electrode by burying a second material made of a metal or a metal compound in the concave portion of the MOS transistor formation region so as to cover the gate insulating film in the concave portion;
Since the second material has a work function different from that of the first material buried in the concave portion of the first MOS transistor formation region, the threshold voltage can be controlled only by the impurity concentration introduced into the substrate as in the conventional case. Without this, it can be easily adjusted by the material of the gate electrode.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
FIGS. 1 to 5 show a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of an embodiment when applied to a method for manufacturing a transistor.

In this example, first, as shown in FIG. 1A, an element isolation layer made of a silicon oxide film is formed on an n-type or p-type silicon substrate (not shown) by a trench method, a LOCOS method, or the like. 20 are formed to define an active region and a field region. Next, a p-type semiconductor well 21 is formed in an active region (hereinafter, referred to as an nMOS formation region) to be an n-type MOS transistor on the silicon substrate, and an active region (hereinafter, referred to as a p-type MOS transistor) on the silicon substrate is formed.
An n-type semiconductor well 22 is formed in a pMOS formation region.

Next, as shown in FIG. 1B, a silicon oxide film 23 is formed on the surface of the silicon substrate for protecting the underlayer by etching. Subsequently, polysilicon is deposited to a thickness of about 200 nm by a CVD method for forming a dummy gate pattern electrode, and a polysilicon film 24 is formed.

Next, as shown in FIG. 1C, a photoresist pattern 25 is formed on the polysilicon film 24 by photolithography and development processing.
Using the resist pattern 25 as a mask, the polysilicon film 4 is anisotropically etched by the RIE method to form a dummy gate pattern 26n serving as a gate pattern in the present invention in the nMOS formation region as shown in FIG. Then, a dummy gate pattern 26p is formed in the pMOS formation region in the same manner.

Next, as shown in FIG. 2 (5), a photoresist film 27 is formed by photolithography and development processing so as to cover the dummy gate pattern 26p and the pMOS formation region, and then by ion implantation. A low concentration impurity is implanted into the diffusion region in the nMOS formation region to form a low concentration diffusion region in the LDD structure. For example, implantation energy 10 keV, arsenic is ion-implanted under the conditions of a dose of 8 × 10 ¹⁴ pieces / cm ^2, the low concentration diffusion region 2 in the nMOS forming area
8 is formed. Thereafter, the photoresist film 27 is removed.

Next, as shown in FIG. 2 (6), a photoresist film 29 is formed so as to cover the dummy gate pattern 26n and the nMOS formation region by photolithography and development processing, and then by ion implantation. A low concentration impurity is implanted into the diffusion region in the pMOS formation region to form a low concentration diffusion region 30 in the LDD structure. For example, boron difluoride (BF ₂ ⁺ ) is ion-implanted under the conditions of an implantation energy of 10 keV and a dose of 4 × 10 ¹⁴ / cm ² to form the low concentration diffusion region 30 in the pMOS formation region. Thereafter, the photoresist film 29 is removed.

Next, SiN or SiO ₂ is deposited and deposited on the silicon substrate by the CVD method, and then this film is etched back to form dummy gate patterns 26n and 26p as shown in FIG. On each side wall, a side wall 31 serving as a mask for forming a source / drain is formed.

Next, as shown in FIG. 2D, a photoresist film 32 is formed by photolithography and development processing so as to cover the dummy gate pattern 26p, its side wall 31, and the pMOS formation region. Then, high-concentration impurities are implanted into the diffusion region in the nMOS formation region by ion implantation to form a high-concentration diffusion region 33 of the transistor. For example, arsenic is ion-implanted under the conditions of an implantation energy of 50 keV and a dose of 3 × 10 ¹⁵ / cm ² to form a high concentration diffusion region 33 in the nMOS formation region. Thereafter, the photoresist film 32 is removed.

Next, as shown in FIG. 3 (9), a photoresist film 34 is formed by photolithography and development processing so as to cover the dummy gate pattern 26n, its side wall 31, and the nMOS formation region. A high-concentration impurity is implanted into the diffusion region in the pMOS formation region by ion implantation to form a high-concentration diffusion region (not shown) of the transistor. For example, boron difluoride (BF ₂ ⁺ ) is ion-implanted under the conditions of an implantation energy of 20 keV and a dose of 3 × 10 ¹⁵ / cm ² to form a high concentration diffusion region in the pMOS formation region. Thereafter, the photoresist film 34 is removed. Next, RTA processing is performed at, for example, 1000 ° C. for 10 seconds, and n
The impurities in the high-concentration diffusion region 33 in the MOS formation region and the high-concentration diffusion region (not shown) in the pMOS formation region are both activated to form the source / drain regions 35.

Next, as shown in FIG. 3 (10), an interlayer insulating film 36 is formed to cover the dummy gate patterns 26n and 26p and the side walls 31 thereof. Here, when SiN is used for the side wall 31 and SiO ₂ is used for the interlayer insulating film 36, the side wall 31 not only functions as a mask for forming the source / drain, but also serves as a contact hole in the active region. In other words, it becomes an etching stop layer when forming a contact hole for connecting the source / drain region and the upper metal wiring, and prevents contact between the conductive material embedded in the contact hole and the side wall of the gate electrode. .

Next, the interlayer insulating film 36 is formed by the CMP method.
Is polished to expose the upper surfaces of the dummy gate patterns 26n and 26p, respectively, as shown in FIG. Next, as shown in FIG. 3 (12), a photoresist film 37 is formed by photolithography and development processing so as to cover the dummy gate pattern 26p, its side wall 31, and the pMOS formation region.

Next, the dummy gate pattern 26n is selectively etched by an etching method such as RIE or wet etching that can obtain a selectivity between the dummy gate pattern 26n and the interlayer insulating film 36, and the dummy gate pattern 26n is removed. . Subsequently, the silicon oxide film 23 under the dummy gate pattern 26n is removed, thereby forming a concave portion 38n at a position where the dummy gate pattern 26n is formed. Thereafter, the photoresist film 37 is removed.

Next, for example, Ta ₂ O is formed by CVD.
₅ is deposited and the interlayer insulating film 36 is covered with the bottom and side surfaces of the recess 38n as shown in FIG.
An insulating film 39 is formed thereon. Note that, instead of forming the insulating film 39, the bottom surface of the concave portion 38n is formed by, for example, a thermal oxidation method.
That is, a SiO ₂ film may be formed on the surface of the silicon substrate.

Next, by a CVD method, a sputtering method, or the like,
A conductive film material is formed as a gate electrode material on the insulating film 39, and a conductive film 40 is formed as shown in FIG. As this conductive film material, a material having a smaller work function than a conductive film material formed in a concave portion on the pMOS formation region side described later is used. Specifically, W, Al, C
A metal such as u, WN, TiN, Ta, TaN or a metal nitride is used, and in this example, TiN is used.

Here, the work function (φ) of each metal is W;
4.5 [eV], Al; 4.2 [eV], Cu; 4.6
[EV], Ti; 3.9 [eV], Ta; 4.1 [e
V]. Although the work function (φ) of these metal nitrides is not described, the same relation between these nitrides as the corresponding metal, that is, the work function (φ)
, The work function of these nitrides also increases in the order of WN>TaN> TiN. The conductive film 40 thus formed is
It also functions as a barrier film for preventing the reaction between the conductive layer formed thereafter and the insulating film 39.

Next, by a CVD method, a sputtering method, or the like,
A conductive layer material is formed on the conductive film 40 in a state where the inside of the concave portion 38n is buried, thereby forming a conductive layer 41. As the conductive layer material, W, Al, C
A metal such as u, WN, TiN, Ta, TaN or a metal nitride is used.
In order to reduce the resistance of the gate electrode obtained from the above, a metal having a lower resistance and a higher melting point is preferable, and W is used in this example.

Next, the interlayer insulating film 36 is formed by the CMP method.
The upper conductive layer 41, the conductive film 40, and the insulating film 39 are polished to leave the conductive layer 41, the conductive film 40, and the insulating film 12 only in the concave portion 38n as shown in FIG. A buried gate electrode made of the layer 41 and the conductive film 40 and a gate insulating film 39a are formed. Next, as shown in FIG. 4 (16), a photoresist film 43 is formed by photolithography and development processing so as to cover the dummy gate pattern 26n, its side wall 31, and the nMOS formation region.

Next, the dummy gate pattern 26p is selectively etched by an etching method, such as RIE or wet etching, capable of obtaining a selectivity between the dummy gate pattern 26p and the interlayer insulating film 36, and the dummy gate pattern 26p is removed. . Subsequently, the silicon oxide film 23 under the dummy gate pattern 26p is removed, thereby forming a concave portion 38p at a position where the dummy gate pattern 26p is formed. Thereafter, the photoresist film 43 is removed.

Then, for example, Ta ₂ O is formed by CVD.
₅ is deposited and the interlayer insulating film 36 is covered with the bottom and side surfaces of the recess 38p as shown in FIG.
An insulating film 44 is formed thereon. Note that, instead of forming the insulating film 44, the bottom surface of the concave portion 38n is formed by, for example, a thermal oxidation method.
That is, a SiO ₂ film may be formed on the surface of the silicon substrate.

Next, by a CVD method, a sputtering method, or the like,
A conductive film material is formed as a gate electrode material on the insulating film 44, and a conductive film 45 is formed as shown in FIG. As described above, as the conductive film material, a material having a larger work function than the conductive film material formed in the concave portion 38n on the nMOS formation region side is used. Specifically, a metal such as W, Al, Cu, WN, TiN, Ta, TaN or a metal nitride is used.
WN or TaN having a larger work function is used. The conductive film 45 formed in this manner also functions as a barrier film for preventing a reaction between a conductive layer formed later and the insulating film 44, similarly to the conductive film 40 on the nMOS formation region side. I have.

Next, by a CVD method, a sputtering method, or the like,
A conductive layer material is formed on the conductive film 45 in a state where the inside of the concave portion 38p is buried, so that a conductive layer 46 is formed. As the conductive layer material, a metal having a low resistance and a high melting point is used in the same manner as the conductive layer material on the nMOS formation region side.
The same material as the conductive layer material on the S formation region side is used. If the material of the conductive layer is the same in the nMOS formation region and the pMOS formation region in this way, the sheet resistance of the obtained gate electrode becomes substantially equal between the n-type and the p-type, and there is almost no variation. Therefore, in this example, pMOS
W is also used for the conductive layer material on the formation region side.

Next, the interlayer insulating film 44 is formed by the CMP method.
The upper conductive layer 46, the conductive film 45, and the insulating film 44 are polished to leave the conductive layer 46, the conductive film 45, and the insulating film 44 only in the recess 38p as shown in FIG. A buried gate electrode 47 including the layer 46 and the conductive film 45 and a gate insulating film 44a are formed. Thereafter, an interlayer insulating film (not shown) is laminated, and further, a contact for connecting the wiring and the transistor portion is opened, and the normal wiring process is completed. This is an example of the semiconductor device according to claim 1 of the present invention. Obtain a semiconductor device.

In the semiconductor device thus obtained, the conductive film 45 of the buried gate electrode 47 in the pMOS transistor has a larger work function than the conductive film 40 of the buried gate electrode 42 in the nMOS transistor. Since the work function of the conductive film that substantially determines the threshold voltage is different between the nMOS transistor and the pMOS transistor, the nMOS transistor and the pMOS
Adjustment of the threshold voltage between the transistor and the transistor becomes easier than before.

The conductive layer 4 of the buried gate electrode 42
1 and the conductive layer 46 of the buried gate electrode 47 are formed of the same metal material (W in this example), so that the sheet resistance of the buried gate electrode 42 and the sheet resistance of the buried gate electrode 47 can be made substantially equal. So that n
The characteristics can be improved by eliminating the variation between the MOS and the pMOS.

In this method of manufacturing a semiconductor device, the conductive film material buried in the recess 38p in the pMOS formation region has a lower work function than the conductive film material buried in the recess 38n in the nMOS formation region. Since the threshold voltage of the pMOS transistor is large, the threshold voltage of the pMOS transistor can be adjusted to be close to the threshold voltage of the nMOS transistor.
Adjustment of the threshold voltage with the transistor can be made easier than before.

In the above embodiment, the buried gate electrode 42 (47) is connected to the conductive film 40 (45) and the conductive layer 4 (45).
1 (46), the buried gate electrodes 42 and 47 are each formed of a single layer made of a metal or a metal compound as shown in FIG.
As compared with the buried gate electrode 42 of the transistor, pMO
The buried gate electrode 47 of the S transistor may be formed of a material having a higher work function. With such a configuration, the process can be simplified as compared with the embodiment shown in FIGS. Therefore, production costs can be reduced.

In the above embodiment, an example is shown in which the present invention is applied to a method of manufacturing a CMOS transistor having a pMOS transistor and an nMOS transistor on the same semiconductor substrate, but the present invention is not limited to this. Instead, the present invention can be applied to a case where there are a plurality of MOS transistors of the same conductivity type on the same semiconductor substrate.

That is, even if the MOS transistors of the same conductivity type have different usage purposes (applications) on a semiconductor integrated circuit (semiconductor device), the threshold voltage is made different depending on the usage purpose. Sometimes you want to. In such a case, conventionally, the adjustment was performed by changing the concentration of the impurity introduced into the semiconductor substrate (silicon substrate). However, the impurity concentration is greatly affected by a subsequent thermal process or the like. At present, it is not possible to easily adjust the value voltage.

Thus, according to the present invention, the MOS transistors (first MOS transistors) and the MOS transistors (second MOS transistors) having different usage purposes (applications) are formed by forming gate electrodes of materials having different work functions from each other. Therefore, the threshold voltage can be formed differently. Therefore, the threshold voltage can be easily adjusted by the material of the gate electrode without controlling the threshold voltage only by the concentration of the impurity introduced into the substrate as in the related art. it can.

[0060]

As described above, in the semiconductor device according to the first aspect of the present invention, the gate electrode of the pMOS transistor is formed of a material having a larger work function than the gate electrode of the nMOS transistor. Although the threshold voltage of the pMOS transistor is usually smaller than that of the nMOS transistor,
The threshold voltage of the transistor is adjusted so as to be close to the threshold voltage of the nMOS transistor. Therefore, the adjustment of the threshold voltage between the nMOS transistor and the pMOS transistor becomes easier than before. Further, as described above, the nMOS transistor and the pMO
Since the threshold voltage is adjusted between the transistor and the S transistor, it is particularly advantageous when the semiconductor device is applied to a semiconductor device requiring low Vth as a device for low power consumption.

According to a third aspect of the present invention, in the semiconductor device, the first MOS
Since the transistor and the second MOS transistor are formed with different threshold voltages because their gate electrodes are made of materials having different work functions, the threshold voltage can be controlled as in the related art. It can be easily adjusted depending on the material of the gate electrode without using only the concentration of the impurity introduced into the substrate. Therefore, the difference in the threshold voltage due to the different purpose of use (application) on the same semiconductor substrate. If there is a MOS transistor to be turned on, the adjustment can be easily performed.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A gate electrode is formed by burying a second material made of a metal or a metal compound in the concave portion of the pMOS transistor formation region so as to cover the gate insulating film in the concave portion and to form the second material in the nMOS transistor formation region. Since the p-type MOS transistor has a higher work function than the first material embedded in the recess, the p-MOS transistor usually has a lower threshold voltage than the n-MOS transistor. The threshold voltage of the pMOS transistor in the device can be easily adjusted to be close to the threshold voltage of the nMOS transistor.

The method for manufacturing a semiconductor device according to claim 7 is
A second material made of a metal or a metal compound is buried in the concave portion of the second MOS transistor formation region so as to cover the gate insulating film in the concave portion, thereby forming a gate electrode. Since the work function is different from that of the first material embedded in the concave portion of the region, the control of the threshold voltage is not performed only by the concentration of the impurity introduced into the substrate as in the related art, and the It can be easily adjusted depending on the material.

[Brief description of the drawings]

FIGS. 1 (1) to 1 (4) are cross-sectional views of essential parts for describing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIGS. 2 (5) to (8) are views showing one embodiment of a method for manufacturing a semiconductor device according to the present invention, and are main parts for sequentially explaining steps following (4) in FIG. It is a side sectional view.

FIGS. 3 (9) to (12) are views showing one embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG.
FIG. 8 is a side sectional view of a main part for sequentially describing steps subsequent to FIG.

4 (13) to (16) are views showing one embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG.
It is a principal part sectional view for demonstrating the process following 2) in order.

5 (17) to (19) are views showing one embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG.
It is a principal part side sectional view for demonstrating the process following 6) in order.

FIG. 6 is a side sectional view of a main part showing another embodiment of the semiconductor device of the present invention.

FIGS. 7 (1) to (5) are cross-sectional views of essential parts for explaining an example of a conventional method for manufacturing a semiconductor device in the order of steps.

FIGS. 8 (6) to (10) are views showing an example of a conventional method for manufacturing a semiconductor device, and are cross-sectional views of essential parts for sequentially describing steps following (5) in FIG. 7; is there.

9 (11) to (15) are views showing an example of a conventional method for manufacturing a semiconductor device, and are cross-sectional side views of essential parts for sequentially explaining steps following (10) in FIG. is there.

[Explanation of symbols]

26n, 26p: dummy gate pattern, 36: interlayer insulating film, 38n, 38p: concave portion, 40, 45: conductive film, 4
1, 46: conductive layer, 42, 47: buried gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/336 H01L 29/78 301P F term (Reference) 4M104 AA01 BB02 BB04 BB17 BB18 BB30 BB32 BB33 CC05 DD03 DD04 DD37 DD43 DD65 DD66 EE09 EE17 GG09 GG10 GG14 HH20 5F040 DA00 DB01 DB03 DC01 EC01 EC04 EC08 EC10 EC12 ED03 EF02 EK01 EK05 FA01 FA02 FA05 FA07 FB02 FC28 5F048 AA00 AA07 AC03 BA01 BB10 BB11 BG15 BG02 BG15 DA06

Claims (8)

[Claims] 1. A semiconductor device having a pMOS transistor and an nMOS transistor on the same semiconductor substrate, wherein a gate electrode of the MOS transistor is formed of a material made of a metal or a metal compound. Is made of materials having different work functions,
A semiconductor device, wherein a gate electrode of a pMOS transistor is formed of a material having a larger work function than a gate electrode of an nMOS transistor. 2. A gate electrode of the nMOS transistor, wherein a gate electrode of the pMOS transistor and a gate electrode of the nMOS transistor each include a conductive film in contact with a gate insulating film and a conductive layer embedded on the conductive film. 2. The semiconductor device according to claim 1, wherein the conductive film of the gate electrode of the pMOS transistor is formed of a material having a higher work function than the conductive film of (a). 3. A semiconductor device having a first MOS transistor and a second MOS transistor of the same conductivity type on the same semiconductor substrate, wherein the gate electrodes of these MOS transistors are formed of a material made of a metal or a metal compound. A semiconductor device, wherein the first MOS transistor and the second MOS transistor have different threshold voltages because their respective gate electrodes are made of materials having different work functions. 4. A gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor each include a conductive film in contact with a gate insulating film and a conductive layer embedded on the conductive film. 4. The semiconductor device according to claim 3, wherein the conductive film of the gate electrode of the transistor and the conductive film of the gate electrode of the second MOS transistor are formed of materials having different work functions. 5. A step of forming a gate pattern in each of a pMOS transistor formation region and an nMOS transistor formation region on a semiconductor substrate, and forming the pMOS transistor formation region and the nMOS transistor formation using these gate patterns as a mask. Implanting impurities into each of the regions to form an electrically active region; forming the electrically active region, forming a sidewall made of an insulating film on a side wall portion of the gate pattern after forming the electrically active region; A step of selectively removing the gate pattern; a step of forming a gate insulating film at a bottom of a concave portion formed by removing the gate pattern; and a step of forming a gate insulating film in the concave portion of the nMOS transistor forming region. Metal or metal covering the gate insulating film A gate material is formed by embedding a first material made of a compound, and a metal or a metal compound is formed in the recess of the pMOS transistor formation region by covering a gate insulating film in the recess. Forming a gate electrode by embedding a second material having a higher work function than the material. 6. The first material and the second material each include a conductive film material covering a gate insulating film in a recess and a conductive layer material provided on the conductive film material.
6. The method according to claim 5, wherein the conductive material of the second material is formed of a material having a higher work function than the conductive material of the first material. 7. A step of forming a gate pattern in each of the first MOS transistor forming region and the second MOS transistor forming region on the semiconductor substrate, and using the gate pattern as a mask to form the first MOS transistor forming region and the second MOS transistor forming region. Implanting an impurity into each of the second MOS transistor formation regions to form an electrically active region, forming an electrically active region, and forming a sidewall made of an insulating film on a side wall of the gate pattern after forming the electrically active region; After the wall is formed, a step of selectively removing the gate pattern; a step of forming a gate insulating film at the bottom of a recess formed by removing the gate pattern; and a step of forming a gate insulating film in the recess in the first MOS transistor formation region. To
A first material made of a metal or a metal compound is buried to cover the gate insulating film in the recess to form a gate electrode, and the gate insulating film in the recess is formed in the recess in the second MOS transistor formation region. And embedding a second material made of a metal or a metal compound and having a work function different from that of the first material to form a gate electrode, thereby forming a gate electrode. 8. The semiconductor device according to claim 1, wherein the first material and the second material each include a conductive film material covering the gate insulating film in the recess and a conductive layer material provided on the conductive film material.
8. The method according to claim 7, wherein the first conductive film material and the second conductive film material are formed of materials having different work functions from each other.