KR101100752B1 - A method for manufacturing a semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and the present invention provides a method for forming a sacrificial gate electrode using a silicon nitride film, and then performing a source / drain region forming process including a heat treatment process, and then removing the sacrificial gate electrode. A metal gate electrode is formed in the part. Therefore, in the present invention, it is possible to prevent boron ions from penetrating into the channel region through the gate oxide film by a subsequent heat treatment process, thereby improving reliability of the device.

Semiconductor element, silicide layer, sacrificial gate electrode, high dielectric film, ozone oxide film, metal film

Description

A manufacturing method of a semiconductor device {A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

1 to 15 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

102 semiconductor substrate 104 device isolation film

106: sacrificial oxide film 108: sacrificial electrode

110: NMOS sacrificial gate electrode 112: PMOS sacrificial gate electrode

114, 116: low concentration junction region

120, 122: high concentration junction region

118: spacer 124: metal layer

126 capping layer 128 first silicide layer

130: second silicide layer 132: insulating film

134, 144: ozone oxide film 136, 146: gate oxide film

138: first metal film 140: second metal film

142: NMOS gate electrode 148: third metal film

150: fourth metal film 152: PMOS gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing boron ions from penetrating into a channel region and improving reliability of the device.

Currently, logic devices have been driving down driving voltages for high integration, reduced power consumption, and high performance. Accordingly, in order to lower the gate oxide film thickness and improve short channel effects, the present invention is changed from a buried channel operation to a surface channel operation. For reference, the buried channel refers to a channel formed by implanting ions through a separate ion implantation process. In addition, the surface channel refers to a channel formed through a voltage applied to the gate electrode rather than implanting ions through an ion implantation process.

In order to implement a surface channel operation CMOS (Complementary Metal-Oxide-Semiconductor ) For element NMOS gate electrode 'n ^-' implanting impurities and, PMOS gate electrode, 'p ^-' by implanting impurities of the two to each other in polarity different It is common to form gate electrodes. However, in the case of the PMOS gate electrode, boron ions implanted in the gate electrode to penetrate the channel region through the gate oxide film by a subsequent heat treatment process to lower the resistance of the gate electrode. As such, when boron ions penetrate into the channel region, the threshold voltage is changed, thereby reducing the reliability of the semiconductor device.

As such, in order to improve penetration of boron ions into the channel region by a subsequent heat treatment process, a method of lowering the heat treatment temperature during the heat treatment process has been proposed. However, when the annealing temperature is lowered, the implanted ions do not diffuse sufficiently, and activation is not properly performed, resulting in an ion depletion region in the gate electrode. As a result, a problem arises in that the threshold voltage is increased to lower the driving capability.

On the other hand, when the thickness of the gate electrode is lowered to increase the doping efficiency, boron penetration increases in the PMOS gate electrode. In addition, in order to solve the problem that the leakage current is generated in the gate oxide film as the thickness of the integrated circuit gate oxide film of the device becomes thin, when the high dielectric material is applied as the gate oxide film, the silicon used as the substrate and the electrode in the subsequent heat treatment process The problem that silicon and the high dielectric react.

Accordingly, the present invention has been made in view of solving the above problems and has the following object.

First, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing boron ions from penetrating into a channel region.                         

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the threshold voltage of the device by forming a gate electrode having a reduced resistance and no ion depletion region.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving a leakage current induced in a gate oxide film.

The present invention also provides a method of manufacturing a semiconductor device capable of preventing a reaction that may occur between the high dielectric film and silicon when the gate oxide film is formed using the high dielectric film to improve the leakage current of the gate oxide film. There is another purpose.

According to an aspect of the present invention for achieving the above object, forming a device isolation film defining a semiconductor substrate as an NMOS region and a PMOS region, and forming a well in the semiconductor substrate of the NMOS region and the PMOS region, respectively Forming a sacrificial gate electrode on the semiconductor substrate of the NMOS region and the PMOS region, respectively, forming a first junction region on the semiconductor substrate exposed to both sides of the sacrificial gate electrode; Forming a spacer on both sidewalls of the sacrificial gate electrode, forming a second junction region on the semiconductor substrate exposed by both sidewalls of the spacer, and a step of an upper surface of the entire structure in which the second junction region is formed Forming a silicide layer on the second junction region by depositing a metal layer and performing a heat treatment process. Depositing an insulating film on the entire structure where the side layer is formed, and then performing a planarization process to expose an upper portion of the sacrificial gate electrode of the NMOS region and the PMOS region, and performing a first etching process to perform the etching of the NMOS region. Removing the sacrificial gate electrode, forming an NMOS gate electrode at a portion from which the sacrificial gate electrode is removed, and performing a second etching process to remove the sacrificial gate electrode of the PMOS region And forming a PMOS gate electrode at a portion from which the sacrificial gate electrode is removed in the PMOS region.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 to 15 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Meanwhile, hereinafter, like reference numerals refer to like elements performing the same function.

Referring to FIG. 1, after forming a device isolation layer 104 by performing a shallow trench isolation (STI) process to define the P-type semiconductor substrate 102 as an NMOS region and a PMOS region, 'p ⁻ ' impurities are formed in the NMOS region. implanting the boron (boron) to form a P- well (P-well) and, PMOS region has 'n ^-' by implanting phosphorus (phosphorous) impurity to form the N- well (N-well).

Then, optionally, 'p ^-' for the threshold voltage control of the NMOS region and the PMOS region and the impurity 'n ^-' then implanting impurities is subjected to a heat treatment step for the activation of the implanted impurity.

Referring to FIG. 2, a sacrificial gate oxide film 106 (hereinafter referred to as a sacrificial oxide film) is formed on an entire structure where P-wells and N-wells are formed, and then a sacrificial gate electrode 108 (hereinafter, referred to as a sacrificial oxide film). , A sacrificial electrode). For example, the sacrificial oxide film 106 may be formed by growing a thermal oxide film using only hydrogen and oxygen gas or oxygen gas on the entire surface of the semiconductor substrate 102. The sacrificial electrode 108 may be formed of a silicon nitride film. The reason why the sacrificial electrode 108 is formed of a silicon nitride film is to prevent boron from penetrating into the channel region during a subsequent heat treatment process (included in the source / drain region forming process).

Thereafter, an etching process using a photolithography process is performed to sequentially pattern the sacrificial electrode 108 and the sacrificial oxide film 106. As a result, the NMOS sacrificial gate electrode 110 is formed in the NMOS region, and the PMOS sacrificial gate electrode 112 is formed in the PMOS region.

Referring to FIG. 3, the photoresist pattern PR1 is formed only in the PMOS region so that the NMOS region is opened, and then an 'n ⁻ ' ion implantation process using the photoresist pattern PR1 is performed to form an NMOS region. A low concentration junction 114 is formed in the P-well, which is a shallow junction.

Referring to FIG. 4, after removing the photoresist pattern PR1, the photoresist pattern PR2 is formed only in the NMOS region so that the PMOS region is opened. Then, the photoresist pattern bit (PR2) using ^- to form the ion implantation process performed in the shallow junction regions in the N- well region of the PMOS lightly doped junction region (116) 'p'.

Referring to FIG. 5, an insulating film (not shown) is deposited by performing a chemical vapor deposition (CVD) process on the entire structure where the low concentration junction regions 114 and 116 are formed. Then, a spacer 118 is formed of silicon oxide on both sidewalls of the NMOS sacrificial gate electrode 110 and the PMOS sacrificial gate electrode 112 by performing an entire surface etching process such as etch back. For reference, when the spacer 118 is formed of a silicon nitride film, as the gate length decreases, the carrier moves in the channel region due to the tension of the silicon nitride film, thereby lowering the driving ability of the device. However, this problem can be solved by forming a low pressure silicon oxide film as in the present invention.

Referring to FIG. 6, the photoresist pattern PR3 is formed only in the PMOS region so that the NMOS region is opened, and then an 'n ⁺ ' ion implantation process using the photoresist pattern PR3 is performed to form the P-well of the NMOS region. The high concentration junction region 120 is formed in the deep junction (depth junction). At this time, the 'n ⁺ ' ion implantation process may be carried out with 40KeV to 60KeV ion implantation energy.

Referring to FIG. 7, after removing the photoresist pattern PR3, the photoresist pattern PR4 is formed only in the NMOS region so that the PMOS region is opened. Then, a 'p ⁺ ' ion implantation process using the photoresist pattern PR4 is performed to form a high concentration junction region 122, which is a deep junction region in the N-well of the PMOS region.

Through the above process, an NMOS source / drain region including a low concentration junction region 114 and a high concentration junction region 120 is formed in the P-well of the NMOS region, and a low concentration junction region 116 and the N-well of the PMOS region are formed. A PMOS source / drain region is formed, which is composed of a high concentration junction region 122.

Then, after performing a rapid thermal process (RTP) to diffuse the ions implanted in the source / drain regions of the PMOS region and the NMOS region, to remove impurities such as particles remaining on the surface of the entire structure. Surface treatment may also be performed.

Referring to FIG. 8, the metal layer 124 is deposited using nickel or cobalt on the entire structure where the NMOS source / drain region and the PMOS source / drain region are formed. For example, the metal layer 124 may be formed to a thickness of 50 mA to 200 mA in consideration of the junction leakage current.

Then, the capping layer 126 may be formed on the metal layer 124 to protect the metal layer 124. In this case, the capping layer 126 may be formed of a single layer of nickel, cobalt, titanium, or titanium nitride (TiN), or may be formed of a laminate in which at least two or more layers are stacked.

Referring to FIG. 9, a first heat treatment process may be performed on the upper portion of the entire structure where the capping layer 126 is formed by a rapid temperature annealing (RTA) method. The silicide layer 128 (hereinafter, referred to as a 'first silicide layer') is formed on the high concentration junction regions 120 and 122 between the NMOS region and the PMOS region by the first heat treatment process. At this time, the first heat treatment process may be carried out in a temperature range of 400 ℃ to 600 ℃.

Referring to FIG. 10, an unreacted material (ie, a metal layer and a capping layer) that remains unreacted after completion of the first heat treatment process is mixed with H ₂ SO ₄ and H ₂ O ₂ in a predetermined ratio or SC— Remove by performing a washing process using 1 (mixed solution of NH ₄ OH / H ₂ O ₂ / H ₂ O) and SC-2 (mixed solution of HCl / H ₂ O ₂ / H ₂ O). .

Then, the second heat treatment process is performed on the upper surface of the entire structure where the cleaning process is completed by the RTA method. The second silicide layer 130 is formed on the source / drain region by phase shifting the first silicide layer 128 using the second heat treatment process. Here, the second heat treatment step may be carried out in a temperature range of 700 ℃ to 800 ℃.

Referring to FIG. 11, after the second heat treatment process is completed, an insulating film 132 is deposited on the entire structure. In this case, the insulating film 132 may include a boron phosphorus silicate glass (BPSG) film, a spin on glass (SOG) film, a plasma enhanced TEOS (PE-TEOS) film, a high density plasma plasma (HDP) oxide film, and an un-doped silicate glass (USG) film. Film and the like.

Next, a planarization process is performed on the insulating layer 132 to expose the upper surfaces of the NMOS and PMOS sacrificial gate electrodes 110 and 112. In this case, the planarization process may be performed by a front surface etching process such as a chemical mechanical polishing (CMP) method or an etch back.

Referring to FIG. 12, the photoresist pattern PR5 is formed only in the PMOS region so that only the upper portion of the NMOS sacrificial gate electrode 110 is opened, and then an NMOS sacrificial gate electrode 110 is selectively removed by performing an etching process. In this case, the sacrificial electrode 108 made of a silicon nitride film may be removed by a wet etching method or a dry etching method. For example, the wet etching method may be performed using a phosphoric acid (H ₃ PO ₄ ) etching solution having an excellent etching selectivity with the silicon oxide film. On the other hand, the sacrificial oxide film 106 can be removed by a cleaning process using hydrofluoric acid.

Referring to FIG. 13, after removing the photoresist pattern PR5, the NMOS sacrificial gate electrode 110 is removed to form an ozone oxide layer 134 on the exposed upper surface of the semiconductor substrate 102. That is, the ozone oxide film 134 is formed on the upper surface of the semiconductor substrate 102 exposed between the spacers 118. At this time, the ozone oxide film 134 may be formed by a cleaning method using ozone water. The ozone oxide layer 134 improves electron / hole mobility, NBTI (Negative Bias Temperature Instability) reliability, and the gate oxide layer 136 and the semiconductor substrate 102 formed of a high dielectric insulating film through a subsequent process. Prevents reacting to each other Here, NBTI is a reliability item regarding the threshold voltage stability of the transistor.

Then, the gate oxide film 136 is deposited along the step on the upper surface of the entire structure where the ozone oxide film 134 is formed. In this case, the gate oxide layer 136 may be deposited using a high dielectric insulating layer. For example, the gate oxide film 136 may be formed of any one of Ta ₂ O ₅ , Al ₂ O ₃ , HfO _2, and HfSiON. As such, by forming the gate oxide layer 136 as a high dielectric insulating film, the electrical thickness is reduced, but the physical thickness is increased, thereby preventing leakage current.

Then, the first metal layer 138 is deposited on the gate oxide film 136. The first metal layer 138 is deposited using a metal film material of a work function belonging to the conduction band of silicon. For example, the first metal layer 138 may be formed of any one of TiN and Zr.

Next, in FIG. 12, the second metal layer 140 is disposed on the entire structure in which the first metal layer 138 is formed using a low resistance metal film material to completely fill the region where the NMOS sacrificial gate electrode 110 is removed. Form. For example, the second metal layer 140 may be formed of any one of W, Al, and Cu.

Then, the planarization process is performed to remove the second metal layer 140, the first metal layer 138, and the gate oxide layer 136 only at the portions where the NMOS sacrificial gate electrode 110 is removed. As a result, the NMOS gate electrode 142 is formed in the NMOS region.

Referring to FIG. 14, the photoresist pattern PR6 is formed only in the NMOS region so that only the upper portion of the PMOS sacrificial gate electrode 112 is opened, and then the PMOS sacrificial gate electrode 112 is selectively removed by performing an etching process. In this case, the sacrificial electrode 108 made of a silicon nitride film may be removed by a wet etching method or a dry etching method. For example, the wet etching method may be performed using a phosphoric acid (H ₃ PO ₄ ) etching solution having an excellent etching selectivity with the silicon oxide film. On the other hand, the sacrificial oxide film 106 can be removed by a cleaning process using hydrofluoric acid.

Referring to FIG. 15, after removing the photoresist pattern PR6, the PMOS sacrificial gate electrode 112 is removed to form an ozone oxide layer 144 on the exposed upper surface of the semiconductor substrate 102. That is, the ozone oxide film 144 is formed on the upper surface of the semiconductor substrate 102 exposed between the spacers 118. At this time, the ozone oxide film 144 may be formed by a cleaning method using ozone water. The ozone oxide film 144 improves electron / hole mobility, NBTI reliability, and a gate oxide film 146 and a semiconductor substrate formed of a high dielectric insulating film on the ozone oxide film 144 in a PMOS region through a subsequent process. Prevent 102 from reacting with each other.

Then, the gate oxide film 146 is deposited along the step on the upper surface of the entire structure where the ozone oxide film 144 is formed. In this case, the gate oxide film 146 may be deposited using a high dielectric insulating film. For example, the gate oxide film 146 may be formed of any one of Ta ₂ O ₅ , Al ₂ O ₃ , HfO _2, and HfSiON. As such, by forming the gate oxide film 146 as a high dielectric insulating film, the electrical thickness is reduced, but the physical thickness is increased, thereby preventing leakage current.

Then, a third metal layer 148 is deposited on the gate oxide film 146. The third metal layer 148 is deposited using a metal film material having a work function belonging to a valence band of silicon. For example, the third metal layer 148 may be formed of any one of TaN and Pt.

Then, in FIG. 14, the fourth metal layer 150 is disposed on the entire structure in which the third metal layer 148 is formed using a low resistance metal film material to completely fill the region where the PMOS sacrificial gate electrode 112 is removed. Form. For example, the fourth metal layer 150 may be formed of any one of W, Al, and Cu.

Then, the planarization process is performed to remove the fourth metal layer 150, the third metal layer 148, and the gate oxide layer 146 only at the portions where the PMOS sacrificial gate electrode 112 is removed. As a result, the PMOS gate electrode 152 is formed in the PMOS region.

As described above with reference to FIGS. 13 and 15, in the preferred embodiment of the present invention, the NMOS gate electrode and the PMOS gate electrode are formed of a metal layer instead of the polysilicon layer. The metal layer has a lower resistance than the polysilicon layer. Accordingly, when a polysilicon layer is used, an additional doping process is required, but when a metal layer is used, a doping process is not necessary, and thus, an additional heat treatment process is not required. In addition, since the doping process is not performed, boron penetration generated in the PMOS can be prevented.

However, when the metal layer is used as the gate electrode, a metal film having a work function belonging to the midband gap of silicon should be used. Therefore, in the preferred embodiment of the present invention, the first metal layer 138 is formed of TiN having the work function of the conduction band (4.2 eV to 4.5 eV), and the third metal layer 148 is formed of one of the balance bands. It is formed from TaN having a function (4.7eV to 4.8eV). Here, since the work function varies depending on the interface state of the gate oxide film and the semiconductor substrate, it is possible to manufacture a P-type device capable of surface channel operation by adjusting the state of the semiconductor substrate. And, the surface channel is easy to adjust the threshold voltage.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

 As described above, according to the present invention, the following effects can be obtained.

First, in the present invention, after forming a sacrificial gate electrode using a silicon nitride film, and then performing a source / drain region forming process including a heat treatment process, the sacrificial gate electrode is removed and a metal gate electrode is formed thereon. As in the present invention, the boron ions are prevented from penetrating into the channel region by the heat treatment process, thereby improving the reliability of the device.

In addition, in the present invention, by forming an ozone oxide film between the gate oxide film and the semiconductor substrate, the electron / hole mobility is improved, the NBTI (Negative Bias Temperature Instability) reliability is improved, and the gate oxide film and the semiconductor substrate react with each other through a subsequent process. It is possible to prevent the deterioration of the device and to lower the reliability of the device due to the reaction.

In the present invention, the NMOS gate electrode is formed of a metal film having a work function belonging to a conduction band, and the PMOS gate electrode is formed of a metal film having a work function belonging to a valence band. By forming, it is possible to implement a metal gate device capable of surface channel operation.

In the present invention, the boron ions in the electrode penetrate into the channel region when the subsequent thermal process temperature is increased to sufficiently activate the impurity implanted in the prior art in which the gate electrode is formed of a metal material to form the gate electrode using a polysilicon film. This can solve the problem of lowering the reliability of the device, such as changing the threshold voltage. That is, in the present invention, it is difficult to sufficiently activate the implanted impurities, thereby solving the problem of increasing the threshold voltage due to an increase in the electrical thickness due to the reduction of the activated ions in the polysilicon film.

In addition, in the present invention, by forming a gate oxide film using a high dielectric film, the electrical thickness is reduced, but the physical thickness is increased, thereby preventing leakage current.

In addition, according to the present invention, by forming a spacer using a low-pressure silicon oxide film having a low stress, as the gate length decreases, the mobility degradation of carriers in the channel region due to the tension of the silicon nitride film may be prevented from occurring.

Claims (10)

(a) forming a device isolation film defining a semiconductor substrate as an NMOS region and a PMOS region: (b) forming wells in the semiconductor substrate of the NMOS region and the PMOS region, respectively; (c) forming a sacrificial gate electrode on the semiconductor substrate of the NMOS region and the PMOS region, respectively; (d) forming a first junction region in the semiconductor substrate exposed to both sides of the sacrificial gate electrode; (e) forming spacers on both sidewalls of the sacrificial gate electrode; (f) forming a second junction region in the semiconductor substrate exposed by both sidewalls of the spacer; (g) forming a silicide layer on the second junction region by depositing a metal layer along a step of an upper surface of the entire structure where the second junction region is formed and then performing a heat treatment process; (h) exposing an upper portion of the sacrificial gate electrode of the NMOS region and the PMOS region by depositing an insulating film on the entire structure on which the silicide layer is formed and then performing a planarization process; (i) performing a first etching process to remove the sacrificial gate electrode in the NMOS region; (j) forming an NMOS gate electrode at a portion of the NMOS region from which the sacrificial gate electrode is removed; (k) performing a second etching process to remove the sacrificial gate electrode in the PMOS region; And (l) forming a PMOS gate electrode at a portion of the PMOS region from which the sacrificial gate electrode is removed; (J) or (l) step, (j-1) forming an ozone oxide film on the exposed semiconductor substrate by removing the sacrificial gate electrode; (j-2) forming a gate oxide film along a step of an upper surface of the entire structure on which the ozone oxide film is formed; (j-3) forming a first metal film along a step of an upper surface of the entire structure on which the gate oxide film is formed; (j-4) forming a second metal film on the entire structure where the first metal film is formed so as to fill the portion where the sacrificial gate electrode is removed; And (j-5) performing a planarization process to planarize an upper portion of the entire structure on which the second metal film is formed to form the NMOS gate electrode or the PMOS gate electrode. The method of claim 1, wherein step (c) comprises: (c-1) forming a thermal oxide film on the semiconductor substrate by using hydrogen and oxygen gas or oxygen gas; (c-2) forming a sacrificial electrode on the thermal oxide film using a silicon nitride film; And (c-3) patterning the sacrificial electrode and the thermal oxide film. delete The method of claim 1, The gate oxide film is a semiconductor device manufacturing method is formed of any one of Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ and HfSiON. The method of claim 1, And the first metal film is formed of any one of a metal film material of a work function belonging to the conduction band and a metal film material of the work function belonging to the balance band. The method of claim 5, The metal film material of the work function belonging to the conduction band is TiN or Zr. The method of claim 5, The metal film material of the work function belonging to the balance band is TaN or Pt. The method of claim 1, The NMOS gate electrode includes a metal film material having a work function belonging to a conduction band. The method of claim 1, And the PMOS gate electrode includes a metal film material having a work function belonging to a balance band. The method of claim 1, The second metal film is a method of manufacturing a semiconductor device formed of any one of W, Al, Cu.

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