KR100915165B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor deviceInfo
- Publication number
- KR100915165B1 KR100915165B1 KR1020070139075A KR20070139075A KR100915165B1 KR 100915165 B1 KR100915165 B1 KR 100915165B1 KR 1020070139075 A KR1020070139075 A KR 1020070139075A KR 20070139075 A KR20070139075 A KR 20070139075A KR 100915165 B1 KR100915165 B1 KR 100915165B1
- Authority
- KR
- South Korea
- Prior art keywords
- ion implantation
- epitaxial layer
- semiconductor device
- impurity doping
- region
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 45
- 238000005468 ion implantation Methods 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 239000002019 doping agent Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 63
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 125000004429 atom Chemical group 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005108 dry cleaning Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001639 boron compounds Chemical class 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 에피택셜층 내에 불순물의 분포를 고르게 할 수 있고, 셀영역의 콘택저항을 감소시킬 수 있는 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명은 셀 영역의 에피택셜층에 이온주입깊이가 서로 다른 복수회의 이온주입으로 불순물 도핑을 진행하여 에피택셜층 내의 도펀트 분포를 균일하게 할 수 있는 효과 및 셀영역의 콘택저항을 감소시킴으로써 소자특성을 개선할 수 있는 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device which can evenly distribute impurities in the epitaxial layer and reduce the contact resistance of the cell region. The present invention provides an ion implantation depth in the epitaxial layer of the cell region. There is an effect that the doping of the dopant in the epitaxial layer can be uniform by doping impurity doping with a plurality of different ion implantations, and the device characteristics can be improved by reducing the contact resistance of the cell region.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 콘택 제조방법에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a contact of a semiconductor device.
반도체 소자의 디자인 룰(Design rule)이 감소하면서 단채널효과(Short Channel Effect) 및 이로 인한 문턱전압(Threshold Voltage) 감소 등의 소자특성이 열화되는 문제가 발생하고 있다. As design rules of semiconductor devices are reduced, device characteristics such as short channel effects and resulting threshold voltages are deteriorated.
단채널효과를 개선하기 위해 셀영역 및 주변영역의 기판 상에 일정두께의 에피택셜층을 형성하는 엘리베이티드 소스/드레인(Elevated Source/Drain) 공정이 적용되고 있다. 엘리베이티드 소스/드레인을 형성하게 되면, 단채널효과를 개선하고, 얕은 접합(Shallow Junction)을 얻을 수 있다.In order to improve the short channel effect, an elevated source / drain process for forming an epitaxial layer having a predetermined thickness on the substrate in the cell region and the peripheral region is applied. Forming elevated sources / drains improves short channel effects and results in shallow junctions.
통상, 에피택셜층을 형성하기 위한 선택적 에피택셜 성장(Selective Epitaxial Growth)은 800℃이상의 고온공정으로 두번 이상 진행하게 되면 열부담(Thermal budget)에 의해 기판에 무리가 가게 되기 때문에, 에피택셜층은 셀영역과 주변영역을 동시에 형성하고 있다. 또한, 주변영역의 NMOS영역과 PMOS영역에 각각 서로 다른 불순물을 도핑하기 때문에 도핑되지 않은 에피택셜층을 형성하고 있다. In general, the selective epitaxial growth for forming the epitaxial layer is difficult to hit the substrate due to thermal budget when the epitaxial growth is performed twice or more in a high temperature process of 800 ° C. or more. The cell region and the peripheral region are formed at the same time. In addition, an undoped epitaxial layer is formed by doping different impurities in the NMOS region and the PMOS region in the peripheral region.
그러나, 셀영역의 경우 도핑되지 않은 에피택셜층을 형성하고, 후속 불순물 도핑공정을 실시하게 되면, 에피택셜층 내에 도핑된 불순물의 분포(Distribution)가 균일하지 않고, 불순물의 활성화(Activation) 역시 부족하여 콘택저항(Contact Resistance, Rc)이 높아지게 되고, 이로 인해 소자특성을 만족시키기 못하는 문제점이 있다.However, in the case of a cell region, when an undoped epitaxial layer is formed and a subsequent impurity doping process is performed, the distribution of doped impurities in the epitaxial layer is not uniform and the activation of impurities is also insufficient. As a result, contact resistance (Rc) becomes high, which causes a problem of failing to satisfy device characteristics.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 에피택셜층 내에 불순물의 분포를 고르게 할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device which can evenly distribute impurities in an epitaxial layer.
또한, 본 발명은 셀영역의 콘택저항을 감소시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.In addition, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the contact resistance of the cell region.
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 셀영역과 주변영역을 갖는 기판 상에 게이트패턴을 형성하는 단계; 상기 게이트패턴 사이의 기판에 도핑되지 않은 에피택셜층을 형성하는 단계; 상기 셀영역을 오픈시키는 제1감광막패턴을 형성하는 단계; 상기 셀영역의 에피택셜층 내에 균일한 도핑농도를 갖도록 이온주입깊이가 서로 다른 복수의 이온주입을 통해 제1불순물 도핑을 수행하는 단계; 상기 제1감광막패턴을 제거하는 단계; 상기 주변영역을 오픈시키는 제2감광막패턴을 형성하는 단계; 상기 주변영역에 제2불순물 도핑을 수행하는 단계; 상기 제2감광막패턴을 제거하는 단계를 포함하는 것을 특징으로 한다. A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate pattern on a substrate having a cell region and a peripheral region; Forming an undoped epitaxial layer on the substrate between the gate patterns; Forming a first photoresist pattern for opening the cell region; Performing a first impurity doping through a plurality of ion implantation having different ion implantation depths so as to have a uniform doping concentration in the epitaxial layer of the cell region; Removing the first photoresist pattern; Forming a second photoresist pattern for opening the peripheral region; Performing a second impurity doping to the peripheral region; And removing the second photoresist pattern.
특히, 제1불순물 도핑은, 이온주입깊이가 서로 다른 이온주입을 2회~4회 진행하되, 2회 진행하는 경우 각 이온주입깊이는 상기 에피택셜층 두께의 1/3지점, 2/3지점인 것을 특징으로 한다.In particular, in the first impurity doping, the ion implantation depth is performed two to four times with different ion implantation depths, and in the case of the second impurity doping, each ion implantation depth is 1/3 point or 2/3 point of the thickness of the epitaxial layer. It is characterized by that.
또한, 제1불순물 도핑 수행 단계에서, 각 이온주입은 3keV∼100keV의 에너지, 1.0×1013atoms/㎠∼1.0×1017atoms/㎠의 도즈로 진행하며, 에피택셜층 두께의 1/3지점으로 이온주입하는 경우 3keV∼50keV의 에너지, 2/3지점으로 이온주입하는 경우 51keV∼100keV의 에너지로 진행하는 것을 특징으로 한다.Further, in the first impurity doping step, each ion implantation proceeds with a dose of 3keV to 100keV energy and a dose of 1.0 × 10 13 atoms / cm 2 to 1.0 × 10 17 atoms / cm 2, one third of the thickness of the epitaxial layer. In the case of ion implantation, the energy of 3keV to 50keV, and the ion implantation to the 2/3 point, the energy of 51keV to 100keV.
또한, 에피택셜층은 500℃∼900℃의 온도에서 100Å∼1000Å의 두께로 형성하고, 에피택셜층은 에피택셜실리콘층, 에피택셜저마늄층 및 에피택셜실리콘저마늄층으로 이루어진 그룹 중에서 선택된 어느 하나인 것을 특징으로 한다.The epitaxial layer is formed to a thickness of 100 kPa to 1000 kPa at a temperature of 500 ° C to 900 ° C, and the epitaxial layer is any one selected from the group consisting of an epitaxial silicon layer, an epitaxial germanium layer and an epitaxial silicon germanium layer. It is characterized by.
그리고, 주변영역은 NMOS영역과 PMOS영역을 갖고, 제2불순물 도핑은 NMOS영역은 N형 불순물을 도핑하고, PMOS영역에는 P형 불순물을 도핑하는 것을 특징으로 한다.The peripheral region has an NMOS region and a PMOS region, and the second impurity doping is characterized in that the NMOS region is doped with N-type impurities, and the PMOS region is doped with P-type impurities.
상술한 본 발명의 반도체 소자의 제조방법은 셀영역의 에피택셜층에 이온주입깊이가 서로 다른 복수회의 이온주입을 통해 불순물 도핑을 진행하여, 에피택셜층 내의 도펀트 분포를 균일하게 할 수 있는 효과가 있다.The semiconductor device manufacturing method of the present invention described above has an effect of uniformly distributing the dopant in the epitaxial layer by performing impurity doping through a plurality of ion implantations having different ion implantation depths in the epitaxial layer of the cell region. have.
따라서, 셀영역의 콘택저항을 감소시킴으로써 소자특성을 개선할 수 있는 효과가 있다.Therefore, the device characteristics can be improved by reducing the contact resistance of the cell region.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 나타내는 공정 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 기판 12 : 게이트패턴11 substrate 12 gate pattern
13 : 스페이서 14 : 제1에피택셜층13 spacer 14 first epitaxial layer
15 : 제2에피택셜층 16 : 제1감광막패턴15: second epitaxial layer 16: first photosensitive film pattern
17 : 제2감광막패턴 18 : 층간절연막17 second photosensitive film pattern 18 interlayer insulating film
19 : 마스크패턴 20 : 랜딩 플러그 콘택19: mask pattern 20: landing plug contact
이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 나타내는 공정 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a에 도시된 바와 같이, 셀영역과 주변영역을 갖는 기판(11) 상에 게이트패턴(12)을 형성한다. 기판(11)은 DRAM공정이 진행되는 반도체 기판일 수 있고, 주변영역은 NMOS영역과 PMOS영역을 가질 수 있다. 게이트패턴(12)은 제1전극(12A), 제2전극(12B) 및 게이트하드마스크(12C)의 적층구조 일 수 있고, 제1전극(12A)은 폴리실리콘일 수 있고, 제2전극은 텅스텐 또는 텅스텐실리사이드일 수 있다.As shown in FIG. 1A, a gate pattern 12 is formed on a substrate 11 having a cell region and a peripheral region. The substrate 11 may be a semiconductor substrate undergoing a DRAM process, and the peripheral region may have an NMOS region and a PMOS region. The gate pattern 12 may be a stacked structure of the first electrode 12A, the second electrode 12B, and the gate hard mask 12C, the first electrode 12A may be polysilicon, and the second electrode may be Tungsten or tungsten silicide.
이어서, 게이트패턴(12)의 측벽에 스페이서(13)를 형성한다. 스페이서(13)는 후속 공정에서 게이트패턴(12)의 측벽을 보호하기 위한 것으로, 게이트패턴(12)을 포함하는 기판(12) 전면에 절연막을 형성한 후, 전면식각을 실시하여 게이트패턴(12)의 측벽에 잔류시킬 수 있다. 절연막은 질화막일 수 있고, 산화막 및 질화막의 적층구조일 수 있으며, 산화막/질화막/산화막의 다층구조일 수 있다.Subsequently, spacers 13 are formed on sidewalls of the gate pattern 12. The spacer 13 is to protect the sidewall of the gate pattern 12 in a subsequent process. After forming an insulating film on the entire surface of the substrate 12 including the gate pattern 12, the spacer 13 is etched to form a gate pattern 12. ) May be left on the sidewalls. The insulating film may be a nitride film, a stacked structure of an oxide film and a nitride film, and may be a multilayer structure of an oxide film / nitride film / oxide film.
이어서, 기판(11)에 전처리 공정을 진행할 수 있다. 이는, 에피택셜층을 형성하기 전에 기판(11) 표면의 자연산화막 등을 제거하기 위한 것으로, 습식 또는 건식세정으로 진행하거나, 습식 및 건식세정을 혼합하여 진행할 수 있다. Subsequently, the pretreatment process may be performed on the substrate 11. This is to remove the native oxide film or the like on the surface of the substrate 11 before forming the epitaxial layer, and may proceed by wet or dry cleaning, or by mixing wet and dry cleaning.
전처리 공정을 습식세정으로 진행하는 경우 HF 용액 계열을 이용하여 진행할 수 있고, 건식세정으로 진행하는 경우 수소, 수소 및 질소의 혼합가스, CF계 가스, NF계 가스 및 NH계 가스로 이루어진 그룹 중에서 선택된 어느 하나로 진행할 수 있다. 또한, 전처리 공정은 30℃∼900℃의 온도에서 진행할 수 있다.When the pretreatment process is carried out by wet cleaning, it can be carried out using a HF solution series, and when the dry cleaning is carried out, it is selected from the group consisting of a mixed gas of hydrogen, hydrogen and nitrogen, CF gas, NF gas and NH gas. You can proceed to either. In addition, a pretreatment process can advance at the temperature of 30 degreeC-900 degreeC.
이어서, 게이트패턴(12) 사이의 기판(11) 상에 제1 및 제2에피택셜층(14, 15)을 동시에 형성한다. 제1 및 제2에피택셜층(14, 15)은 에피택셜실리콘층, 에피택셜저마늄층 및 에피택셜실리콘저마늄층으로 이루어진 그룹 중에서 선택된 어느 하나일 수 있으며, 선택적 에피택셜 성장(Selective Epitaxial Growth)방법으로, 도핑되지 않은(Undoped) 에피택셜층으로 형성할 수 있다. 특히, 제1 및 제2에피택셜층(14, 15)은 단채널 효과(Short Channel Effect)를 개선시키기 위한 엘리베이티드 소스/드레인(Elevated Source/Drain)일 수 있다.Subsequently, first and second epitaxial layers 14 and 15 are simultaneously formed on the substrate 11 between the gate patterns 12. The first and second epitaxial layers 14 and 15 may be any one selected from the group consisting of an epitaxial silicon layer, an epitaxial germanium layer, and an epitaxial silicon germanium layer, and a selective epitaxial growth method. As an example, an undoped epitaxial layer may be formed. In particular, the first and second epitaxial layers 14 and 15 may be elevated sources / drains to improve short channel effects.
제1 및 제2에피택셜층(14, 15)은 LPCVD(Low Pressure Chemical Vapor Deposition), VLPCVD(Very Low Pressure CVD), PECVD(Plasma Enhanced CVD), UHVCVD(Ultrahigh Vacuum CVD), RTCVD(Rapid Thermal CVD), APCVD(Atomsphere Pressure CVD) 및 MBE(Molecular Beam Epitaxy)로 이루어진 그룹 중에서 선택된 어느 하나의 장비에서, 500℃∼900℃의 온도로, 100Å∼1000Å의 두께로 형성할 수 있다.The first and second epitaxial layers 14 and 15 may include low pressure chemical vapor deposition (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced CVD (PECVD), ultrahigh vacuum CVD (UHVCVD), and rapid thermal CVD (RTCVD). ), APCVD (Atomsphere Pressure CVD) and MBE (Molecular Beam Epitaxy) in any one of the equipment selected from, the temperature of 500 ℃ to 900 ℃, it can be formed to a thickness of 100 Pa ~ 1000 Pa.
도 1b에 도시된 바와 같이, 셀영역을 오픈시키는 제1감광막패턴(16)을 형성한다. 제1감광막패턴(16)은 제1 및 제2에피택셜층(14, 15)을 포함하는 기판 전면에 게이트패턴(12)을 충분히 덮도록 감광막을 코팅하고, 노광 및 현상으로 셀영역이 오픈되도록 패터닝하여 형성할 수 있다. 제1감광막패턴(16)에 의해 주변영역의 제2에피택셜층(15)은 보호되고, 셀영역의 제1에피택셜층(14)만 선택적으로 오픈된다.As shown in FIG. 1B, a first photoresist pattern 16 for opening a cell region is formed. The first photoresist pattern 16 is coated with a photoresist such that the gate pattern 12 is sufficiently covered on the entire surface of the substrate including the first and second epitaxial layers 14 and 15, and the cell region is opened by exposure and development. It can be formed by patterning. The second epitaxial layer 15 in the peripheral region is protected by the first photoresist pattern 16, and only the first epitaxial layer 14 in the cell region is selectively opened.
이어서, 제1에피택셜층(14)에 이온주입깊이(Range Ion Projection)가 서로 다른 복수회의 이온주입을 통해 제1불순물 도핑을 수행한다. 제1불순물 도핑은 이온주입깊이가 서로 다르도록 2회∼4회 이온주입을 실시하여 수행할 수 있으며, 본 발명의 실시예에서는 제1불순물 도핑을 2회의 이온주입으로 실시하는 공정에 대해 설명하기로 한다. 또한, 설명의 편의를 위해 도 1b 및 도 1c로 나누어 설명하기로 한다.Subsequently, the first impurity doping is performed on the first epitaxial layer 14 through a plurality of ion implantations having different ion implantation depths. The first impurity doping may be performed by performing ion implantation twice to four times so that the ion implantation depths are different from each other, and in the embodiment of the present invention, the first impurity doping is performed by performing ion implantation twice. Shall be. In addition, for convenience of description, the description will be made by dividing into FIGS. 1B and 1C.
먼저, 제1에피택셜층(14)에 1차 불순물 도핑을 진행한다. 1차 불순물 도핑은 제1에피택셜층(14)의 총 두께 T의 1/3지점인 T1을 이온주입깊이(Rp)로 하여 이온주입하는 것에 의해 달성된다. 1차 불순물 도핑시 이온주입은 3keV∼50keV의 에너지로 진행할 수 있고, 1.0×1013atoms/㎠∼1.0×1017atoms/㎠의 도즈로 진행할 수 있다. 또한, 1차 불순물 도핑은 인(P) 또는 비소(As)로 진행할 수 있다.First, primary impurity doping is performed on the first epitaxial layer 14. Primary impurity doping is achieved by ion implantation using T 1 , which is one third of the total thickness T of the first epitaxial layer 14 as the ion implantation depth Rp. During primary impurity doping, ion implantation may proceed with an energy of 3 keV to 50 keV and proceed to a dose of 1.0 × 10 13 atoms / cm 2 to 1.0 × 10 17 atoms / cm 2. In addition, the primary impurity doping may proceed with phosphorus (P) or arsenic (As).
이때, 주변영역은 제1감광막패턴에 의해 보호되어 있으므로 불순물이 도핑되지 않는다.At this time, since the peripheral region is protected by the first photoresist pattern, impurities are not doped.
도 1c에 도시된 바와 같이, 제1에피택셜층(14)에 2차 불순물 도핑을 진행한다. 2차 불순물 도핑은 제1에피택셜층(14)의 총 두께 T의 2/3지점인 T2를 이온주입깊이(Rp)로 하여 이온주입하는 것에 의해 달성된다. 2차 불순물 도핑은 51keV∼100keV 에너지의 이온주입으로 진행할 수 있고, 1.0×1013atoms/㎠∼1.0×1017atoms/㎠의 도즈로 진행할 수 있다. 또한, 2차 불순물 도핑은 인(P) 또는 비소(As)로 진행할 수 있다.As shown in FIG. 1C, secondary impurity doping is performed on the first epitaxial layer 14. Secondary impurity doping is achieved by ion implantation with T 2 , which is 2/3 of the total thickness T of the first epitaxial layer 14 as the ion implantation depth Rp. Secondary impurity doping may proceed with ion implantation of 51 keV to 100 keV energy, and may proceed with a dose of 1.0 × 10 13 atoms / cm 2 to 1.0 × 10 17 atoms / cm 2. In addition, the secondary impurity doping may proceed with phosphorus (P) or arsenic (As).
위와 같이, 제1에피택셜층(14)에 서로 다른 깊이로 이온주입을 복수회 진행하여 제1불순물 도핑을 수행함으로써, 제1에피택셜층(14)에 불순물의 분포를 고르게 할 수 있다. 즉, 한번의 이온주입을 진행하는 경우, 이온주입깊이의 타겟이 되는 부분에만 불순물이 집중되어 후속 열공정을 진행하여 활성화를 한다고 하여도 한계가 있으나, 이온주입깊이를 서로 다르게 2회 이상 이온주입을 진행하는 경우 불순물이 집중되는 지역이 적어도 두 곳 이상이 되기 때문에 불순물의 분포를 고르게 할 수 있다. 또한, 동일한 도즈로 2회 이상 진행하게 되면, 한번의 이온주입을 진행하는 경우보다 도핑되는 총 도즈량이 2배 이상이 되기 때문에 제1에피택셜층(14) 내의 불순물의 도즈 증가로 콘택저항이 감소된다. 따라서, 셀영역의 콘택저항 감소로 반도체 소자의 신뢰성 및 수율 등의 소자특성을 개선할 수 있다.As described above, the first impurity doping is performed by plural times implanting ions into the first epitaxial layer 14 at different depths to uniformly distribute impurities in the first epitaxial layer 14. In other words, when one ion implantation is performed, impurities are concentrated only in the target portion of the ion implantation depth, and there is a limit even if activation is performed by subsequent thermal process. However, the ion implantation depth is differently ionized twice or more. In case of proceeding, since the concentration of impurities is at least two or more places, the distribution of impurities can be uniform. In addition, if the same dose is performed two or more times, the contact resistance decreases due to an increase in the dose of impurities in the first epitaxial layer 14 since the total dose to be doped is two times or more than the case of one ion implantation. do. Therefore, device characteristics such as reliability and yield of semiconductor devices can be improved by reducing contact resistance of the cell region.
도 1d에 도시된 바와 같이, 제1감광막패턴(16)을 제거한다. 제1감광막패턴(16)은 건식식각으로 제거할 수 있고, 건식식각은 산소스트립일 수 있다.As shown in FIG. 1D, the first photoresist pattern 16 is removed. The first photoresist pattern 16 may be removed by dry etching, and the dry etching may be an oxygen strip.
이어서, 주변영역을 오픈시키는 제2감광막패턴(16)을 형성한다. 제2감광막패턴(16)은 제1 및 제2에피택셜층(14, 15)을 포함하는 전체구조 상에 게이트패턴(12) 사이를 충분히 매립하도록 감광막을 코팅하고, 노광 및 현상으로 주변영역이 오픈되도록 패터닝하여 형성할 수 있다. Subsequently, a second photosensitive film pattern 16 is formed to open the peripheral area. The second photoresist pattern 16 coats the photoresist layer so as to sufficiently fill the space between the gate patterns 12 on the entire structure including the first and second epitaxial layers 14 and 15. It can be formed by patterning to open.
이어서, 제2에피택셜층(15)에 제2불순물도핑을 진행한다. 제2불순물도핑은 1회의 이온주입으로 수행할 수 있으며, 주변영역이 NMOS영역인 경우 인(P) 또는 비소(As)를 사용하여 도핑할 수 있고, 주변영역이 PMOS영역인 경우 붕소(B) 또는 붕소화합물(BF+, BF2 등)을 사용하여 도핑할 수 있다.Subsequently, a second impurity doping is performed on the second epitaxial layer 15. The second impurity doping may be performed by one ion implantation, and may be doped using phosphorus (P) or arsenic (As) when the peripheral region is an NMOS region, and boron (B) when the peripheral region is a PMOS region. Or doped with a boron compound (BF +, BF 2, etc.).
도 1e에 도시된 바와 같이, 제2감광막패턴(17)을 제거한다. 제2감광막패턴(17)은 건식식각으로 제거할 수 있고, 건식식각은 산소스트립일 수 있다.As shown in FIG. 1E, the second photoresist layer pattern 17 is removed. The second photoresist pattern 17 may be removed by dry etching, and the dry etching may be an oxygen strip.
이어서, 제1 및 제2에피택셜층(14, 15) 상에 게이트패턴(12) 사이를 매립하는 절연층(18)을 형성한다. 절연층(18)은 게이트패턴(12) 사이 및 상부층과의 절연을 위한 것으로, 게이트패턴(12) 사이를 충분히 매립하도록 산화막을 형성하고, 게이트패턴(12)의 상부가 드러나는 타겟으로 평탄화하여 형성할 수 있다.Subsequently, an insulating layer 18 is formed on the first and second epitaxial layers 14 and 15 to fill the gaps between the gate patterns 12. The insulating layer 18 is for insulating between the gate pattern 12 and the upper layer. The insulating layer 18 is formed by forming an oxide film so as to sufficiently fill the gate pattern 12, and planarizing it with a target that exposes the upper portion of the gate pattern 12. can do.
이어서, 절연층(18) 상에 마스크패턴(19)을 형성한다. 마스크패턴(19)은 랜딩 플러그 콘택홀 영역이 오픈되도록 패터닝할 수 있으며, 감광막패턴 또는 하드마스크패턴과 감광막패턴의 적층구조로 형성할 수 있다.Subsequently, a mask pattern 19 is formed on the insulating layer 18. The mask pattern 19 may be patterned so that the landing plug contact hole region is opened, and the mask pattern 19 may be formed in a stacked structure of a photoresist pattern or a hard mask pattern and a photoresist pattern.
이어서, 마스크패턴(19)을 식각배리어로 절연층(18)을 식각하여 게이트패턴(12) 사이에 제1에피택셜층(14)을 오픈시키는 랜딩 플러그 콘택홀(20)을 형성한다. 절연층(18)의 식각은 자기정렬콘택식각(Self Aligned Contact Etch)으로 진행할 수 있다.Subsequently, the insulating layer 18 is etched using the mask pattern 19 as an etch barrier to form a landing plug contact hole 20 that opens the first epitaxial layer 14 between the gate patterns 12. The etching of the insulating layer 18 may be performed by self aligned contact etching.
도 1f에 도시된 바와 같이, 랜딩 플러그 콘택홀(20)에 도전물질을 매립하여 랜딩 플러그 콘택(21)을 형성한다. 도전물질은 에피택셜실리콘, 폴리실리콘 및 금속물질로 이루어진 그룹 중에서 선택된 어느 하나일 수 있으며, 랜딩 플러그 콘택홀(20)에 충분히 매립되도록 도전물질을 매립하고 평탄화하여 랜딩 플러그 콘택(21)을 형성할 수 있다. 이때, 평탄화는 화학적기계적연마(Chemical Mechanical Polishing) 또는 에치백(Etch Back) 공정으로 진행할 수 있다.As illustrated in FIG. 1F, a conductive material is embedded in the landing plug contact hole 20 to form the landing plug contact 21. The conductive material may be any one selected from the group consisting of epitaxial silicon, polysilicon, and a metal material. The conductive material may be embedded and planarized to sufficiently fill the landing plug contact hole 20 to form the landing plug contact 21. Can be. In this case, the planarization may be performed by chemical mechanical polishing or etching back.
도전물질이 에피택셜실리콘 또는 폴리실리콘인 경우, 1.0×1018atoms/㎤∼1.0×1021atoms/㎤의 도즈로 도핑된 에피택셜실리콘 또는 폴리실리콘으로 형성할 수 있다.When the conductive material is epitaxial silicon or polysilicon, it may be formed of epitaxial silicon or polysilicon doped with a dose of 1.0 × 10 18 atoms / cm 3 to 1.0 × 10 21 atoms / cm 3.
도전물질을 금속물질로 형성하는 경우, 제1금속층, 제2금속층 및 제3금속층으로 형성할 수 있다. 제1금속층은 Ti, Co 및 Ni로 이루어진 그룹 중에서 선택된 어느 하나일 수 있으며, 제1금속층은 후속 열공정에 의해 제1에피택셜층(14)과 반응하여 금속실리사이드를 형성할 수 있다. 제2금속층은 배리어금속(Barrier Metal)으로 티타늄질화막(TiN) 또는 텅스텐질화막(WN)일 수 있으며, 제3금속층은 텅스텐일 수 있다.When the conductive material is formed of a metal material, the conductive material may be formed of the first metal layer, the second metal layer, and the third metal layer. The first metal layer may be any one selected from the group consisting of Ti, Co, and Ni, and the first metal layer may react with the first epitaxial layer 14 to form metal silicide by a subsequent thermal process. The second metal layer may be a barrier metal, and may be a titanium nitride layer (TiN) or a tungsten nitride layer (WN), and the third metal layer may be tungsten.
본 실시에에서는 게이트패턴 사이의 콘택 제조방법에 대해 설명하고 있으나, 본 실시예는 콘택 제조 방법 이외에 도핑되지 않은 에피택셜층을 형성하고, 후속 이온주입으로 도핑을 수행하는 공정에 응용될 수 있다. In the present embodiment, a method for manufacturing a contact between gate patterns has been described. However, the present embodiment may be applied to a process of forming an undoped epitaxial layer in addition to the contact manufacturing method and performing doping by subsequent ion implantation.
이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
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| JP2001035931A (en) * | 1999-06-18 | 2001-02-09 | Hyundai Electronics Ind Co Ltd | Manufacture of semiconductor element |
| JP2001068671A (en) * | 1999-06-29 | 2001-03-16 | Hyundai Electronics Ind Co Ltd | Manufacture of transistor having elevated source and drain regions |
| JP2006179947A (en) * | 2006-02-13 | 2006-07-06 | Renesas Technology Corp | Method for mnufacturing semiconductor integrated circuit device |
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| KR20010003652A (en) * | 1999-06-24 | 2001-01-15 | 김영환 | Method of fabricating semiconductor device including elevated source/drain |
| JP2001068671A (en) * | 1999-06-29 | 2001-03-16 | Hyundai Electronics Ind Co Ltd | Manufacture of transistor having elevated source and drain regions |
| JP2006179947A (en) * | 2006-02-13 | 2006-07-06 | Renesas Technology Corp | Method for mnufacturing semiconductor integrated circuit device |
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| KR101738894B1 (en) * | 2010-11-04 | 2017-05-24 | 삼성전자 주식회사 | Method of fabricating gate and method of manufacturing semiconductor device using thereof |
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