CN116779615B - Integrated semiconductor device and manufacturing method thereof - Google Patents
Integrated semiconductor device and manufacturing method thereof Download PDFInfo
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- CN116779615B CN116779615B CN202311061702.6A CN202311061702A CN116779615B CN 116779615 B CN116779615 B CN 116779615B CN 202311061702 A CN202311061702 A CN 202311061702A CN 116779615 B CN116779615 B CN 116779615B
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Abstract
The application discloses an integrated semiconductor device and a manufacturing method thereof, which belong to the technical field of semiconductors, wherein the integrated semiconductor device comprises: a substrate, wherein the substrate comprises a first area and a second area; the grid dielectric layer is arranged on the substrate; the metal silicide grid electrodes are arranged on the grid dielectric layer, and doped ions are arranged at the interface of the metal silicide grid electrodes and the grid dielectric layer; the first heavily doped region is arranged on two sides of the metal silicide grid electrode in the first region; and the second heavily doped region is arranged on two sides of the metal silicide gate on the second region, and the doping types of the first heavily doped region and the second heavily doped region are opposite. The integrated semiconductor device and the manufacturing method thereof provided by the application simplify the manufacturing process and improve the performance of the integrated semiconductor device.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to an integrated semiconductor device and a manufacturing method thereof.
Background
Integrated semiconductor devices are manufactured by integrating multiple types of devices together, for example, different types of transistors are manufactured on the same substrate, and the different transistors are isolated by a shallow trench isolation structure. By manufacturing different semiconductor devices on the same substrate, the manufacturing efficiency of the semiconductor devices can be improved, and the integration level of the semiconductor devices can be improved. However, in the manufacturing process of different semiconductor devices, the threshold voltages of the semiconductor devices are different, so that the use of a high-frequency circuit and a low-power-consumption circuit needs to be satisfied, different areas need to be manufactured separately, but the threshold voltages are not easy to control, the manufacturing process is complex, and the production cost is increased.
Disclosure of Invention
The application aims to provide an integrated semiconductor device and a manufacturing method thereof, which can simplify the manufacturing process of the integrated semiconductor device, reduce the production cost of enterprises, control the threshold voltage of the integrated semiconductor device and improve the performance of the integrated semiconductor device.
In order to solve the above technical problems, the present application provides an integrated semiconductor device, at least comprising:
a substrate, wherein the substrate comprises a first area and a second area;
the grid dielectric layer is arranged on the substrate;
the metal silicide grid electrodes are arranged on the grid dielectric layer, and doped ions are arranged at the interface of the metal silicide grid electrodes and the grid dielectric layer;
the first heavily doped region is arranged on two sides of the metal silicide grid electrode in the first region; and
and the second heavily doped region is arranged on two sides of the metal silicide gate on the second region, and the doping types of the first heavily doped region and the second heavily doped region are opposite.
In an embodiment of the present application, the metal silicide gate includes a first low-voltage metal silicide gate, a first medium-voltage metal silicide gate, and a first high-voltage metal silicide gate disposed on the first region.
In an embodiment of the present application, the doping ion types of the first low-voltage metal silicide gate, the first medium-voltage metal silicide gate and the first high-voltage metal silicide gate are P-type, and the doping ion concentration in the first low-voltage metal silicide gate is greater than the doping ion concentration in the first medium-voltage metal silicide gate, and the doping ion concentration in the first medium-voltage metal silicide gate is greater than the doping ion concentration in the first high-voltage metal silicide gate.
In an embodiment of the present application, the metal silicide gate includes a second low-voltage metal silicide gate, a second medium-voltage metal silicide gate, and a second high-voltage metal silicide gate disposed on the second region.
In an embodiment of the present application, the doping ion types of the second low-voltage metal silicide gate, the second medium-voltage metal silicide gate and the second high-voltage metal silicide gate are N-type, and the doping ion concentration in the second low-voltage metal silicide gate is greater than the doping ion concentration in the second medium-voltage metal silicide gate, and the doping ion concentration in the second medium-voltage metal silicide gate is greater than the doping ion concentration in the second high-voltage metal silicide gate.
The application also provides a manufacturing method of the integrated semiconductor device, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first area and a second area;
forming a gate dielectric layer on the substrate;
forming a plurality of metal silicide gates on the gate dielectric layer, and forming doping ions at the interface of the metal silicide gates and the gate dielectric layer;
forming a first heavily doped region on two sides of the metal silicide gate on the first region; and
and forming second heavily doped regions on two sides of the metal silicide gate on the second region, wherein the doping types of the first heavily doped regions and the second heavily doped regions are opposite.
In an embodiment of the present application, the manufacturing method further includes the following steps:
forming a gate material layer on the gate dielectric layer;
performing first ion implantation on the grid material layer to form a first gradient doping region;
forming a first photoresist layer on the gate material layer, wherein the first photoresist layer exposes a low-voltage region of the first region and a high-voltage region of the second region;
performing ion implantation for the second time to form an intermediate doped region;
trimming the first photoresist layer, removing part of the photoresist layer on the side surface of the first photoresist layer, and exposing the intermediate doped region and the intermediate voltage regions on the first region and the second region;
and performing third ion implantation to form a second gradient doped region and a third gradient doped region.
In an embodiment of the present application, the doping ions of the first graded doping region, the second graded doping region and the third graded doping region are P-type.
In an embodiment of the present application, the manufacturing method further includes the following steps:
etching the gate material layer to form a plurality of gate structures on the first region and the second region;
performing first source-drain doped ion implantation on the first region to form a first heavily doped region, and simultaneously implanting the first source-drain doped ions into the gate structure on the first region, wherein the types of the doped ions of the first source-drain doped ions are the same as those of the doped ions of the gradient doped region;
and performing second source-drain doped ion implantation on the second region to form a second heavily doped region, wherein the second source-drain doped ion is implanted into the gate structure on the second region, the type of the second source-drain doped ion is opposite to that of the gradient doped region, and the implantation concentration of the second source-drain doped ion is larger than that of the third gradient doped region.
In an embodiment of the present application, the manufacturing method further includes:
after forming the first heavily doped region and the second heavily doped region, thinning the gate structure;
forming a metal layer on the thinned gate structure;
and annealing the metal layer, wherein the metal layer reacts with silicon in the gate structure to form a metal silicide gate, and doping ions in the gate structure are gathered at the interface of the metal silicide gate and the gate dielectric layer.
In summary, the present application provides an integrated semiconductor device and a method for manufacturing the same, and by improving the structure and the method for manufacturing the integrated semiconductor device, the unexpected technical effect of the present application is that at least one photoresist process can be saved, at least three masks can be saved, the manufacturing process can be simplified, and the production cost can be saved. The ion implantation concentration controllability of the grid structures in different areas is high, and the threshold voltage of the transistor can be flexibly controlled. The number of source-drain doped ions in the gate structure can be controlled to adjust the doping concentration of the gate structure so that the doping concentration in the gate structure is smaller than that of the heavily doped region. The work function of the grid can be controlled, semiconductor devices with different threshold voltages can be obtained, the manufacturing method is high in controllability, the method is simple, the production efficiency can be improved, and the production cost of enterprises can be reduced.
Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a substrate distribution in an embodiment.
FIG. 2 is a schematic diagram of a shallow trench isolation structure according to an embodiment.
FIG. 3 is a diagram of well sector area in one embodiment.
Fig. 4 is a schematic diagram of a gate dielectric layer and a gate material layer in an embodiment.
FIG. 5 is a schematic diagram illustrating formation of a first graded doped region in an embodiment.
FIG. 6 is a schematic illustration of forming an intermediate doped region in one embodiment.
Fig. 7 is a schematic distribution diagram of a first graded doped region, a second graded doped region, and a third graded doped region in an embodiment.
FIG. 8 is a schematic diagram illustrating a distribution of a plurality of gate structures according to an embodiment.
Fig. 9 is a schematic diagram of a sidewall structure in an embodiment.
FIG. 10 is a schematic diagram of a heavily doped region in an embodiment.
FIG. 11 is a schematic diagram of a thinned gate structure according to an embodiment.
FIG. 12 is a schematic diagram of a dielectric layer and a metal layer according to an embodiment.
Fig. 13 is a schematic view of a semiconductor integrated device in an embodiment.
Description of the reference numerals:
10. a substrate; 100. a first region; 200. a second region; 11. a pad oxide layer; 12. pad nitriding layer; 13. patterning the photoresist layer; 131. an opening; 14. shallow trench isolation structures; 15. a well region; 16. a gate dielectric layer; 17. a gate material layer; 171. a first graded doped region; 1711. an intermediate doped region; 172. a second graded doped region; 173. a third graded doped region; 18. a first photoresist layer; 19. a side wall structure; 20. a first heavily doped region; 21. a second heavily doped region; 22. a dielectric layer; 23. a metal layer; 101. a first low voltage gate structure; 102. a first medium voltage gate structure; 103. a first high voltage gate structure; 201. a second low voltage gate structure; 202. a second medium voltage gate structure; 203. a second high voltage gate structure; 101a, a first low voltage metal silicide gate; 102a, a first medium voltage metal silicide gate; 103a, a first high voltage metal silicide gate; 201a, a second low voltage metal silicide gate; 202a, a second medium voltage metal silicide gate; 203a, a second high voltage metal silicide gate.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
The application provides an integrated semiconductor device and a manufacturing method thereof, which can prepare semiconductor devices with different functions in different areas of the same substrate, each semiconductor device has excellent performance, and can simultaneously meet the use requirements of a high-frequency circuit and a low-power-consumption circuit. The manufacturing method of the integrated semiconductor device provided by the application is simple, has high controllability, can reduce the production cost, and can be used for manufacturing semiconductor devices with different requirements.
Referring to fig. 1, in one embodiment of the present application, a substrate 10 is provided first, and the substrate 10 may be any material suitable for forming, such as a silicon wafer, a germanium substrate, silicon germanium, silicon on insulator or silicon on insulator stack. The application is not limited to the type and thickness of the substrate 10, and in this embodiment, the substrate 10 is, for example, a silicon wafer, and the substrate 10 is, for example, a P-type silicon wafer. The substrate 10 includes, for example, a first region 100 and a second region 200. The first region 100 is provided with a plurality of P-type metal oxide semiconductor field effect transistors (Positive Channel Metal Oxide Semiconductor, PMOS) for example, and the operating voltages of the plurality of PMOS transistors are different, the second region 200 is provided with a plurality of N-type metal oxide semiconductor field effect transistors (Negative Channel Metal Oxide Semiconductor, NMOS) for example, and the operating voltages of the plurality of NMOS transistors are different, that is, the same substrate 10 is provided with transistors with different types and operating voltages at the same time, and the adjacent transistors are isolated by a shallow trench isolation structure. The integrated semiconductor device is prepared in different areas of the same substrate, so that the production efficiency can be improved, and the production cost can be reduced.
Referring to fig. 1, in an embodiment of the present application, a pad oxide layer 11 is formed on a substrate 10, and the pad oxide layer 11 is made of a dense silicon oxide, for example, and the pad oxide layer 11 may be prepared by a thermal oxidation method, an In-situ vapor deposition method (In-Situ Steam Generation, ISSG), a chemical vapor deposition method (Chemical Vapor Deposition, CVD), or the like. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, a silicon nitride layer, and the pad nitride layer 12 is formed by, for example, chemical vapor deposition or the like. In the process of forming the shallow trench isolation structure, the pad oxide layer 11 can improve the stress between the substrate 10 and the pad nitride layer 12, and can protect the substrate 10 from being damaged by high-energy ions when the well region is formed by ion implantation. A patterned photoresist layer 13 is formed on the pad nitride layer 12, a plurality of openings 131 are disposed on the patterned photoresist layer 13, the openings 131 are used to define the locations of the shallow trench isolation structures, and the openings 131 expose the pad nitride layer 12.
Referring to fig. 1 to 2, after forming the patterned photoresist layer 13, in an embodiment of the present application, the patterned photoresist layer 13 is used as a mask, for example, dry etching is used to etch in the direction of the substrate 10, so as to remove the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the opening 131, thereby forming a shallow trench. Wherein the etching gas comprises, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), etc. After the shallow trench is formed, a liner oxide layer (not shown) is formed in the shallow trench, for example, by a thermal oxidation method, so as to repair etching damage in the process of forming the shallow trench and reduce leakage of the integrated semiconductor device. In shallow trenches, e.g. by high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor depositionHigh Aspect Ratio Process CVD, HARP-CVD) and the like, and the isolation medium is, for example, an insulating substance such as silicon oxide. After the isolation medium is deposited, for example, after the isolation medium and the pad nitride layer 12 are planarized by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process, the pad nitride layer 12 is removed to form the shallow trench isolation structure 14, and a step is formed between the shallow trench isolation structure 14 and the pad oxide layers on both sides, wherein the height of the step is, for example, 5nm to 15nm, and is specifically selected according to the manufacturing requirement.
Referring to fig. 2, in an embodiment of the present application, after the shallow trench isolation structure 14 is formed, the shallow trench isolation structure 14 divides the first region 100 and the second region 200. Regions between adjacent shallow trench isolation structures 14 are defined as a high voltage region (High Voltage threshold, HVt), a medium voltage region (Standard Voltage threshold, SVt), and a low voltage region (Low Voltage threshold, LVt) to form a high voltage transistor, a medium voltage transistor, and a low voltage transistor. In the first region 100, from the interface between the first region 100 and the second region 200, a high-pressure region, a medium-pressure region, and a low-pressure region are sequentially formed, that is, the high-pressure region in the first region 100 is close to the interface between the first region 100 and the second region 200. In the second region 200, from the interface of the first region 100 and the second region 200, a low pressure region, a medium pressure region, and a high pressure region are sequentially provided, that is, the low pressure region in the second region 200 is close to the interface of the first region 100 and the second region 200.
Referring to fig. 2 to 3, in an embodiment of the present application, after forming the shallow trench isolation structure 14, a photoresist layer (not shown) is formed on the substrate 10, and the photoresist layer covers the second region 200. The substrate 10 is ion-implanted to form a well region 15. In the present embodiment, a doped region having a higher concentration than the substrate 10 is implanted with a high implantation energy, that is, the well region 15 is formed in the first region 100, wherein the well region 15 is, for example, an N-type well, and the doped ions are N-type impurities such As phosphorus (P), arsenic (As), or antimony (Sb) for forming a PMOS transistor on the first region 100. The depth of the well region 15 and the depth of the shallow trench isolation structure 14 are not limited, and may be greater than, less than, or equal to the depth of the shallow trench isolation structure 14. In the second region 200, the P-type doping of the substrate 10 is maintained to form an NMOS transistor on the second region 200, so that the one-time photoresist and ion implantation process can be reduced, and the production efficiency can be improved. After forming the well region 15, a rapid thermal annealing process (Rapid Thermal Anneal, RTA) is performed on the well region 15 and the substrate 10. In this embodiment, the annealing temperature is, for example, 1000 ℃ to 1400 ℃, the annealing time is, for example, 0.5h to 3h, and the annealing process is performed under a stable gas atmosphere, for example, under a nitrogen atmosphere. Through the annealing process, the avalanche breakdown resistance of the integrated semiconductor device is improved.
Referring to fig. 3 to 4, in an embodiment of the application, after forming the well region 15, the pad oxide layer 11 is removed. In this embodiment, for example, wet etching is used to remove the pad oxide layer 11, and wet etching liquid is, for example, dilute hydrofluoric acid or BOE, and etching is performed at normal temperature. In other embodiments, other etching methods may be used, and the etching method may be selected according to specific manufacturing requirements. After removing the pad oxide layer 11, a gate dielectric layer 16 is formed on the substrate 10, and the thickness of the gate dielectric layer 16 is, for example, 3nm to 10nm. In the present embodiment, the gate dielectric layer 16 is, for example, a silicon oxide layer, and the gate dielectric layer 16 is, for example, formed by a thermal oxidation method or an in-situ vapor growth method, so as to improve the quality of the gate dielectric layer 16. A gate material layer 17 is formed on the gate dielectric layer 16, and the thickness of the gate material layer 17 is, for example, 80nm to 100nm. In the present embodiment, the gate material layer 17 is, for example, polysilicon, and the gate material layer 17 is formed, for example, by chemical vapor deposition, wherein the polysilicon is undoped polysilicon.
Referring to fig. 4 to 5, in an embodiment of the application, after forming the gate material layer 17, a first ion implantation is performed on the entire gate material layer 17 to form the first graded doped region 171. Wherein the first ion implantation is performed by using P-type ion such as boron (B) or gallium (Ga), and the ion concentration of the first ion implantation is 5×10 14 atoms/cm 2 ~1×10 15 atoms/cm 2 . In the present embodiment, in the first graded doped region 171, the dopant ions are in the gateAnd the electrode material layers are uniformly distributed.
Referring to fig. 5 to 6, in an embodiment of the present application, after forming the first graded doped region 171, a first photoresist layer 18 is formed on the gate material layer 17, the first photoresist layer 18 is exposed and developed, and the first photoresist layer 18 exposes the low voltage region LVt of the first region 100 and the high voltage region HVt of the second region 200. A second ion implantation is performed using the first photoresist layer 18 as a mask to form an intermediate doped region 1711, and the direction of the arrow in fig. 6 is the ion implantation direction. The ion concentration of the second ion implantation may be the same as or different from that of the first ion implantation, and is specifically determined according to the threshold voltage of the transistor. In the present embodiment, the ion concentration of the second ion implantation is, for example, 5×10 14 atoms/cm 2 ~1×10 15 atoms/cm 2 And in the intermediate doped region 1711, the ions of the first implant and the ions of the second implant are uniformly distributed in the layer of gate material.
Referring to fig. 6 to fig. 7, in an embodiment of the application, after forming the intermediate doped region 1711, the first photoresist layer 18 is trimmed or re-exposed to remove a portion of the photoresist layer on the side surface of the first photoresist layer 18, so as to enlarge the opening area of the first photoresist layer 18. After trimming, the first photoresist layer 18 exposes the intermediate doped region 1711 and the intermediate voltage region SVt over the first region 100 and the second region 200. With the trimmed first photoresist layer 18 as a mask, a third ion implantation is performed to form a second graded doped region 172 and a third graded doped region 173, and the arrow direction in fig. 7 is the ion implantation direction. The ion concentration of the third ion implantation may be the same as or different from the ion concentration of the second ion implantation or the ion concentration of the first ion implantation, and is specifically determined according to the threshold voltage of the transistor. In the present embodiment, the ion concentration of the third ion implantation is, for example, 5×10 14 atoms/cm 2 ~1×10 15 atoms/cm 2 The ions of the third ion implantation are uniformly distributed in the gate material layer. In the process of carrying out the third time of ionDuring implantation, the first photoresist layer 18 on the first region 100 and the second region 200 is trimmed at the same time, and three regions with doping concentrations are formed in the first region 100 and the second region 200, so that one photoresist process can be saved, at least three photomasks can be saved, the manufacturing process can be simplified, and the production cost can be saved compared with the process of independently forming the doping regions with different concentrations in different regions.
Referring to fig. 7, in an embodiment of the present application, after the third ion implantation, the ion concentration in the first graded doped region 171 is the ion concentration of the first ion implantation, the ion concentration in the second graded doped region 172 is the sum of the ion concentrations of the first ion implantation and the second ion implantation, and the ion concentration in the third graded doped region 173 is the sum of the ion concentrations of the first ion implantation, the second ion implantation and the third ion implantation, i.e., the ion concentration of the third graded doped region 173 is greater than the ion concentration of the second graded doped region 172, and the ion concentration of the second graded doped region 172 is greater than the ion concentration of the first graded doped region 171. By carrying out ion implantation in multiple times, the ion implantation concentration controllability of different areas is high, and the threshold voltage of the transistor can be flexibly controlled. After the third ion implantation, the first photoresist layer 18 is removed by ashing or wet etching or the like.
Referring to fig. 7 to 8, in an embodiment of the present application, after ion implantation is performed on the gate material layer, a photoresist layer (not shown) is formed on the gate material layer to locate the gate structure. And removing part of the gate material layer and part of the gate dielectric layer 16 exposed by the photoresist layer by using the photoresist layer as a mask, for example, wet etching, dry etching or a combination of wet etching and dry etching, and the like, so as to form a plurality of gate structures. Wherein, on the first region 100, a portion of the third graded doped region 173 is reserved to form the first low-voltage gate structure 101, a portion of the second graded doped region 172 is reserved to form the first medium-voltage gate structure 102, a portion of the first graded doped region 171 is reserved to form the first high-voltage gate structure 103, on the second region 200, a portion of the first graded doped region 171 is reserved to form the second low-voltage gate structure 201, a portion of the second graded doped region 172 is reserved to form the second medium-voltage gate structure 202, and a portion of the third graded doped region 173 is reserved to form the second high-voltage gate structure 203. And a low voltage gate structure is formed on the low voltage region LVt, a medium voltage gate structure is formed on the medium voltage region SVt, and a high voltage gate structure is formed on the high voltage region HVt for forming transistors of different threshold voltages.
Referring to fig. 8 to 9, in an embodiment of the application, after forming the gate structure, sidewall structures 19 are formed on two sides of the gate structure, wherein the sidewall structures 19 are, for example, a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall structure 19 includes, for example, a stack of silicon oxide and silicon nitride to ensure stability of the sidewall structure. Specifically, a sidewall dielectric layer (not shown) is formed on the substrate 10, where the sidewall dielectric layer covers the gate structure, the substrate 10 and the shallow trench isolation structure 14, and the material of the sidewall dielectric layer is, for example, a stack of silicon oxide and silicon nitride. After forming the sidewall dielectric layer, for example, an etching process such as dry etching may be used to remove the sidewall dielectric layer on the gate structure and part of the substrate 10, and part of the sidewall dielectric layers on two sides of the gate structure are reserved to form the sidewall structure 19, where the height of the sidewall structure 19 is the same as that of the gate structure. In this embodiment, the shape of the sidewall structure 19 is, for example, circular arc, and in other embodiments, any shape of the sidewall structure 19 may be selected.
Referring to fig. 9 to 10, in an embodiment of the present application, after the sidewall structure 19 is formed, heavy doping is formed in the substrate 10 at both sides of the gate structure. Specifically, a first patterned photoresist layer (not shown) is formed on the substrate 10, the first patterned photoresist layer covers the second region 200, the first region 100 is completely exposed, and first source-drain doped ion implantation is performed, so that first heavily doped regions 20 are formed in the well regions 15 on both sides of the gate structure on the first region 100. Wherein the first source/drain doped ions are P-type ions such as boron or gallium, and the implantation amount of the first source/drain doped ions is 2×10 15 atoms/cm 2 ~3×10 15 atoms/cm 2 The depth of the first heavily doped region 20 is, for example, 5nm to 50nm. During the first source/drain doping ion implantation, first source/drain doping ions are simultaneously implanted into the gate structure, and the first sourceThe drain dopant ions are of the same type as the ions in the gate structure, and thus the gate structure is doped P-type in the first region 100. And the ion doping concentration in the first low voltage gate structure 101 is greater than the ion doping concentration in the first medium voltage gate structure 102, and the ion doping concentration in the first medium voltage gate structure 102 is greater than the ion doping concentration in the first high voltage gate structure 103.
Referring to fig. 10, in an embodiment of the present application, after forming the first heavily doped region 20, the first patterned photoresist layer on the substrate 10 is removed, a second patterned photoresist layer (not shown) covering the first region 100 is reformed, the second region 200 is completely exposed, and second source-drain doped ion implantation is performed to form second heavily doped regions 21 in the substrate 10 on both sides of the gate structure on the second region 200. Wherein the second source/drain doped ion is N-type ion such as phosphorus, arsenic or antimony, and the implantation amount of the second source/drain doped ion is 5×10 15 atoms/cm 2 ~6×10 15 atoms/cm 2 The depth of the second heavily doped region 21 is, for example, 5nm to 50nm, and then the second patterned photoresist layer is removed. And when the second source-drain doping ions are implanted, the second source-drain doping ions are implanted into the gate structure at the same time, and the ion types of the second source-drain doping ions and the gate structure are opposite, so that part of the second source-drain doping ions are neutralized. The second source-drain doped ions are implanted at a concentration greater than the doping concentration of the third graded doped region, so that the doping type of the gate structure is N-type in the second region 200, and the ion doping concentration in the second low-voltage gate structure 201 is greater than the ion doping concentration in the second medium-voltage gate structure 202, and the ion doping concentration in the second medium-voltage gate structure 202 is greater than the ion doping concentration in the second high-voltage gate structure 203.
Referring to fig. 10 to 11, in an embodiment of the present application, after forming the heavily doped region, the gate structure and the sidewall structure 19 are thinned by a planarization process. In this embodiment, the planarization process is performed, for example, by chemical mechanical polishing, and the thickness of the gate structure removed is, for example, 10nm to 30nm. Then, the substrate 10 is annealed to activate the heavily doped region and the doped ions in the gate structure, in this embodiment, a rapid annealing manner such as spike annealing is used, and the annealing temperature is 1000 ℃ to 1200 ℃. And activating source and drain doping ions of the heavily doped region through annealing treatment, and meanwhile, uniformly distributing ions in the grid structure. The quantity of the source and drain doping ions in the residual gate structure can be controlled by controlling the thickness of the thinning gate structure so as to adjust the doping concentration of the gate structure, and the concentration of the source and drain doping ions in the gate structure can be smaller than the doping concentration of the source and drain doping ions in the heavy doping region.
Referring to fig. 11 to 12, in an embodiment of the present application, after thinning and annealing the gate structures, a dielectric layer 22 is formed on the substrate 10 and the sidewall structure 19 between the gate structures, wherein the dielectric layer 22 is an insulating material such as silicon dioxide, or may be a low dielectric constant material such as silicon carbide nitride (SiCN). Specifically, the dielectric layer 22 is formed, for example, by chemical vapor deposition, and after deposition, a planarization process is performed to ensure that the top of the dielectric layer 22 is flush with the top of the gate structure. Then, a metal layer 23 is formed on the dielectric layer 22 and the gate structure, and the metal layer 23 is, for example, a titanium layer (Ti), a cobalt layer (Co), a nickel layer (Ni), or the like, and is, for example, a nickel layer.
Referring to fig. 12 to 13, in an embodiment of the present application, after forming the metal layer 23, the substrate 10 is annealed at a temperature of, for example, 300 ℃ to 350 ℃ for, for example, 35s to 45s, and during the annealing process, the metal in the metal layer 23 diffuses into the gate structure and reacts with the polysilicon in the gate structure to form metal silicide, so as to form a metal silicide gate. After annealing, unreacted metal layer 23 and dielectric layer 22 are removed. In this embodiment, the metal silicide gate is NiSi, for example. The first low-voltage gate structure 101 forms a first low-voltage metal silicide gate 101a, the first medium-voltage gate structure 102 forms a first medium-voltage metal silicide gate 102a, and the first high-voltage gate structure 103 forms a first high-voltage metal silicide gate 103a. The second low voltage gate structure 201 forms a second low voltage metal silicide gate 201a, the second medium voltage gate structure 202 forms a second medium voltage metal silicide gate 202a, and the second high voltage gate structure 203 forms a second high voltage metal silicide gate 203a. When forming the metal silicide gate, the metal in the metal layer 23 only reacts with the polysilicon in the gate structure and does not react with the dopant ions, so that the dopant ions are pressed by the metal silicide to accumulate downwards and finally accumulate at the interface between the metal silicide gate and the gate dielectric layer 16. In this embodiment, the gate work function of the first low-voltage metal silicide gate 101a is, for example, 5.0ev to 5.1ev, the gate work function of the first medium-voltage metal silicide gate 102a is, for example, 4.9ev to 5.0ev, and the gate work function of the first high-voltage metal silicide gate 103a is, for example, 4.8ev to 4.9ev. The gate work function of the second low-voltage metal silicide gate 201a is, for example, 4.1ev to 4.2ev, the gate work function of the second medium-voltage metal silicide gate 202a is, for example, 4.2ev to 4.3ev, and the gate work function of the second high-voltage metal silicide gate 203a is, for example, 4.3ev to 4.4ev. The difference in threshold voltages of the high-voltage MOS transistor, the medium-voltage MOS transistor, and the low-voltage MOS transistor is formed due to the difference in concentration of dopant ions accumulated at the interface of the metal silicide gate and the gate dielectric layer 16. The work function of the grid is controlled by controlling the concentration of doping ions in the grid structure in different transistors, so that semiconductor devices with different threshold voltages are obtained.
In summary, the present application provides an integrated semiconductor device and a method for fabricating the same, and by improving the structure and the method for fabricating the same, the unexpected technical effects of the present application are that the first photoresist layer on the first region and the second region is trimmed simultaneously during multiple ion implantation, and multiple regions with doping concentrations are formed in the first region and the second region, and at least one photoresist process can be saved, at least three masks can be saved, the fabrication process can be simplified, and the production cost can be saved. By carrying out ion implantation in multiple times, the ion implantation concentration controllability of the grid structures in different areas is high, and the threshold voltage of the transistor can be flexibly controlled. The number of source and drain doping ions in the residual gate structure can be controlled by thinning the gate structure so as to adjust the doping concentration of the gate structure. The concentration of doping ions in the grid structure is controlled in different transistors, so that the work function of the grid is controlled, semiconductor devices with different threshold voltages are obtained, the manufacturing method is high in controllability and simple, the production efficiency can be improved, and the production cost of enterprises is reduced.
The embodiments of the application disclosed above are intended only to help illustrate the application. The examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (8)
1. An integrated semiconductor device, comprising:
a substrate, wherein the substrate comprises a first area and a second area;
the grid dielectric layer is arranged on the substrate;
the metal silicide grid electrodes are arranged on the grid dielectric layer, and doped ions are arranged at the interface of the metal silicide grid electrodes and the grid dielectric layer;
the first heavily doped region is arranged on two sides of the metal silicide grid electrode in the first region; and
the second heavily doped region is arranged on two sides of the metal silicide gate on the second region, and the doping types of the first heavily doped region and the second heavily doped region are opposite;
wherein the metal silicide gate comprises a first low-voltage metal silicide gate, a first medium-voltage metal silicide gate and a first high-voltage metal silicide gate which are arranged on the first region;
the doping ion types of the first low-voltage metal silicide gate, the first medium-voltage metal silicide gate and the first high-voltage metal silicide gate are P-type, the doping ion concentration in the first low-voltage metal silicide gate is larger than that in the first medium-voltage metal silicide gate, and the doping ion concentration in the first medium-voltage metal silicide gate is larger than that in the first high-voltage metal silicide gate.
2. The integrated semiconductor device of claim 1, wherein the metal silicide gate comprises a second low voltage metal silicide gate, a second medium voltage metal silicide gate, and a second high voltage metal silicide gate disposed on the second region.
3. The integrated semiconductor device of claim 2, wherein the doping ion types of the second low-voltage metal silicide gate, the second medium-voltage metal silicide gate, and the second high-voltage metal silicide gate are N-type, and the doping ion concentration in the second low-voltage metal silicide gate is greater than the doping ion concentration in the second medium-voltage metal silicide gate, the doping ion concentration in the second medium-voltage metal silicide gate being greater than the doping ion concentration in the second high-voltage metal silicide gate.
4. A method of fabricating an integrated semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area;
forming a gate dielectric layer on the substrate;
forming a plurality of metal silicide gates on the gate dielectric layer, and forming doping ions at the interface of the metal silicide gates and the gate dielectric layer;
forming a first heavily doped region on two sides of the metal silicide gate on the first region; and
forming second heavily doped regions on two sides of the metal silicide gate on the second region, wherein the doping types of the first heavily doped regions and the second heavily doped regions are opposite;
wherein the metal silicide gate comprises a first low-voltage metal silicide gate, a first medium-voltage metal silicide gate and a first high-voltage metal silicide gate which are arranged on the first region;
the doping ion types of the first low-voltage metal silicide gate, the first medium-voltage metal silicide gate and the first high-voltage metal silicide gate are P-type, the doping ion concentration in the first low-voltage metal silicide gate is larger than that in the first medium-voltage metal silicide gate, and the doping ion concentration in the first medium-voltage metal silicide gate is larger than that in the first high-voltage metal silicide gate.
5. The method of manufacturing an integrated semiconductor device according to claim 4, further comprising the steps of:
forming a gate material layer on the gate dielectric layer;
performing first ion implantation on the grid material layer to form a first gradient doping region;
forming a first photoresist layer on the gate material layer, wherein the first photoresist layer exposes a low-voltage region of the first region and a high-voltage region of the second region;
performing ion implantation for the second time to form an intermediate doped region;
trimming the first photoresist layer, removing part of the photoresist layer on the side surface of the first photoresist layer, and exposing the intermediate doped region and the intermediate voltage regions on the first region and the second region;
and performing third ion implantation to form a second gradient doped region and a third gradient doped region.
6. The method of claim 5, wherein the first graded doped region, the second graded doped region, and the third graded doped region have P-type dopant ions.
7. The method of manufacturing an integrated semiconductor device according to claim 6, further comprising the steps of:
etching the gate material layer to form a plurality of gate structures on the first region and the second region;
performing first source-drain doped ion implantation on the first region to form a first heavily doped region, and simultaneously implanting the first source-drain doped ions into the gate structure on the first region, wherein the types of the doped ions of the first source-drain doped ions are the same as those of the doped ions of the gradient doped region;
and performing second source-drain doped ion implantation on the second region to form a second heavily doped region, wherein the second source-drain doped ion is implanted into the gate structure on the second region, the type of the second source-drain doped ion is opposite to that of the gradient doped region, and the implantation concentration of the second source-drain doped ion is larger than that of the third gradient doped region.
8. The method of fabricating an integrated semiconductor device of claim 7, further comprising:
after forming the first heavily doped region and the second heavily doped region, thinning the gate structure;
forming a metal layer on the thinned gate structure;
and annealing the metal layer, wherein the metal layer reacts with silicon in the gate structure to form a metal silicide gate, and doping ions in the gate structure are gathered at the interface of the metal silicide gate and the gate dielectric layer.
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