CN116013775A - Grid manufacturing method - Google Patents
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- CN116013775A CN116013775A CN202211740162.XA CN202211740162A CN116013775A CN 116013775 A CN116013775 A CN 116013775A CN 202211740162 A CN202211740162 A CN 202211740162A CN 116013775 A CN116013775 A CN 116013775A
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Abstract
The invention provides a gate manufacturing method, which comprises the following steps: providing a semiconductor substrate, and sequentially forming a gate dielectric layer, a polysilicon layer and a silicon oxide mask layer on the semiconductor substrate; etching the polysilicon layer and the gate dielectric layer to form a false gate structure isolated by a trench, wherein the trench exposes the semiconductor substrate; forming an interlayer dielectric layer with a preset thickness in the groove, wherein the top surface of the interlayer dielectric layer is lower than the top surface of the dummy gate structure and higher than the top surface of the polysilicon layer; modifying the interlayer dielectric layer by adopting an ion implantation process; removing the silicon oxide mask layer and the polysilicon layer; and forming a metal gate on the gate dielectric layer. According to the invention, only the silicon monoxide hard mask layer is formed on the polysilicon layer, so that the depth-to-width ratio of the groove is reduced, and the groove is filled; and the interlayer dielectric layer is modified by adopting an ion implantation process and is used as a stop layer for etching the dummy gate structure, the height of the polysilicon layer is compensated by the height of the modified interlayer dielectric layer, the height of the gate can be adjusted, and the method has the advantage of flexible and adjustable gate height.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a grid manufacturing method.
Background
With the miniaturization and integration development of semiconductor devices, the circuit line width and line spacing of the devices have been smaller and smaller, but the depth of the trenches or the vias has not been significantly reduced, resulting in larger and larger depth ratios of the features such as the trenches or the vias. As shown in fig. 1, in the standard gate structure manufacturing process, a mask including a silicon oxide mask layer 4 and a silicon nitride mask layer 18 is used to etch the gate morphology, a SiGe layer 8 is embedded in the source/drain region of the P-channel field effect transistor, and a SiP layer 19 is embedded in the source/drain region of the N-channel field effect transistor. In the above scheme, the multi-layer hard mask makes the depth-width ratio of the trench high, and besides the process window for challenging gate etching, the process for filling the silicon oxide interlayer is also a great challenge.
In addition, when the gate is formed in the prior art, the polysilicon layer 3 in the dummy gate structure is etched and then filled with metal, and the height of the metal gate depends on the height of polysilicon, i.e. the height of the gate is not adjustable after the height of the polysilicon is determined, which has a certain limitation in the preparation of the device structure.
Therefore, how to provide a gate manufacturing method, which can reduce the aspect ratio of the trench to facilitate gap filling and control the gate height, is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a method for manufacturing a gate, which is used to solve the problems in the prior art that the trench depth-width ratio is high, which is not beneficial to gap filling, and the gate height is not adjustable after the polysilicon height is determined.
To achieve the above and other related objects, the present invention provides a method for manufacturing a gate structure, comprising the steps of:
s1: providing a semiconductor substrate, and sequentially forming a gate dielectric layer and a polysilicon layer on the semiconductor substrate;
s2: forming a silicon oxide mask layer on the polysilicon layer, patterning, and etching the polysilicon layer and the gate dielectric layer by taking the patterned silicon oxide mask layer as a mask to form a false gate structure isolated by a groove, wherein the groove exposes the semiconductor substrate;
s3: forming an interlayer dielectric layer with a preset thickness in the groove, wherein the top surface of the interlayer dielectric layer is lower than the top surface of the dummy gate structure and higher than the top surface of the polysilicon layer;
s4: modifying the interlayer dielectric layer by adopting an ion implantation process;
s5: removing the silicon oxide mask layer and the polysilicon layer;
s6: and depositing a metal layer on the gate dielectric layer to form a metal gate.
Optionally, before executing step S3, the method further includes the following steps:
forming a side wall protection layer on the side wall of the dummy gate structure;
and forming a grinding stop layer on the surface of the false gate structure, wherein the grinding stop layer extends to the exposed surface of the semiconductor substrate.
Optionally, in step S1, the semiconductor substrate includes a first conductivity type channel field effect transistor region and a second conductivity type channel field effect transistor region; in step S4, the interlayer dielectric layer in the first conduction type channel field effect transistor region is subjected to ion implantation with implantation energy of 2-6 keV and implantation dosage of e 15-e 16 cm -2 The implant element comprises silicon.
Optionally, in step S4, a first photoresist layer is formed on the structure after the interlayer dielectric layer is formed before the ion implantation, and the first photoresist layer is patterned to expose the first conductivity type channel field effect transistor region.
Optionally, in step S1, the first conductivity type channel field effect transistor is a P-channel field effect transistor, and the second conductivity type channel field effect transistor is an N-channel field effect transistor; in step S2, after the trench is formed, a step of embedding a SiGe layer in the semiconductor substrate exposed by the P-channel field effect transistor region and a step of embedding a SiP layer in the semiconductor substrate exposed by the N-channel field effect transistor region are further included.
Optionally, in step S5, the step of removing the silicon oxide mask layer and the polysilicon layer includes:
s50: removing the structure above the polysilicon layer in the second conductivity type channel field effect tube region:
s51: removing the structure above the interlayer dielectric layer in the first conduction type channel field effect tube region;
s52: removing the silicon oxide mask layer above the polysilicon layer in the first conductivity type channel field effect tube region;
s53: and removing the polysilicon layer in the first conductive type channel field effect transistor region and the second conductive type channel field effect transistor region.
Optionally, in step S50, a second photoresist layer is formed on the structure after the ion implantation is completed before removing the structure above the polysilicon layer in the second conductivity type channel field effect transistor region, and the second photoresist layer is patterned to expose the second conductivity type channel field effect transistor region.
Optionally, before forming the second photoresist layer, forming a first bottom anti-reflection layer on the structure after the ion implantation is completed, and forming the second photoresist layer on the first bottom anti-reflection layer.
Optionally, in step S51, before removing the structure above the interlayer dielectric layer in the first conductivity type channel field effect transistor region, a third photoresist layer is formed on the structure after step S50 is completed, and the third photoresist layer is patterned to expose the first conductivity type channel field effect transistor region.
Optionally, before forming the third photoresist layer, a second bottom anti-reflection layer is formed on the structure after step S50 is completed, and the third photoresist layer is formed on the second bottom anti-reflection layer.
As described above, in the gate manufacturing method of the present invention, only the silicon oxide mask layer is formed on the polysilicon layer, which reduces the aspect ratio of the trench and facilitates the gap filling of the trench; and the interlayer dielectric layer is modified by adopting an ion implantation process and is used as a stop layer for etching the dummy gate structure, the height of the polysilicon layer is compensated by the height of the modified interlayer dielectric layer, the height of the gate can be adjusted, and the method has the advantage of flexible and adjustable gate height.
Drawings
Fig. 1 is a schematic diagram of a prior art gate fabrication using a silicon nitride mask layer and a silicon oxide mask layer.
Fig. 2 is a flow chart of a gate manufacturing method according to a first embodiment of the invention.
Fig. 3 is a schematic diagram illustrating a gate dielectric layer and a polysilicon layer formed on a semiconductor substrate according to a first embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a method for forming a silicon oxide mask layer on a polysilicon layer and etching to form a dummy gate structure according to a first embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating formation of a polish stop layer according to a first embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating formation of an interlayer dielectric material layer according to a first embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating removal of an interlayer dielectric material layer above a polish stop layer according to a first embodiment of the present invention.
Fig. 8 is a schematic diagram illustrating an interlayer dielectric layer formed by etching an interlayer dielectric material layer according to a first embodiment of the present invention.
Fig. 9 is a schematic diagram showing a P-channel field effect transistor region formed by patterning a first photoresist layer according to a first embodiment of the present invention.
Fig. 10 is a schematic diagram illustrating modification of an interlayer dielectric layer of a P-channel field effect transistor region according to a first embodiment of the present invention.
FIG. 11 is a schematic diagram illustrating the removal of the first photoresist layer according to the first embodiment of the invention.
FIG. 12 is a schematic diagram showing a first bottom anti-reflective layer and a second photoresist layer formed and patterning the second photoresist layer to expose an N-channel field effect transistor region according to a first embodiment of the present invention.
Fig. 13 is a schematic diagram showing a structure of removing the upper portion of the polysilicon layer of the N-channel fet region in accordance with the first embodiment of the present invention.
FIG. 14 is a schematic diagram showing the removal of the first bottom anti-reflective layer and the second photoresist layer according to the first embodiment of the invention.
Fig. 15 is a schematic diagram showing forming a second bottom anti-reflection layer and a third photoresist layer and patterning the third photoresist layer to expose a P-channel field effect transistor region according to a first embodiment of the present invention.
Fig. 16 is a schematic diagram showing a structure of removing the upper portion of the interlayer dielectric layer of the P-channel field effect transistor region according to the first embodiment of the present invention.
Fig. 17 is a schematic diagram of removing a silicon oxide mask layer of a P-channel field effect transistor region according to a first embodiment of the present invention.
FIG. 18 is a schematic diagram showing the removal of the second bottom anti-reflective layer and the third photoresist layer according to the first embodiment of the invention.
Fig. 19 is a schematic view showing removal of polysilicon layers in a P-channel fet region and an N-channel fet region in accordance with a first embodiment of the present invention.
Fig. 20 is a schematic diagram illustrating a metal gate formed on a gate dielectric layer according to a first embodiment of the present invention.
Description of element reference numerals
1. Semiconductor substrate
2. Gate dielectric layer
3. Polysilicon layer
4. Silicon oxide mask layer
5. Groove(s)
6. False gate structure
7. Side wall protection layer
8 SiGe layer
9. Polishing stop layer
10. Interlayer dielectric material layer
11. Interlayer dielectric layer
12. First photoresist layer
13. Second photoresist layer
14. First bottom anti-reflection layer
15. Third photoresist layer
16. Second bottom anti-reflection layer
17. Metal grid
18. Silicon nitride mask layer
19 SiP layer
I first conductivity type channel field effect transistor region
II second conductivity type channel field effect transistor region
S1 to S6 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 20. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The present embodiment provides a method for manufacturing a gate, please refer to fig. 2, which is a flowchart of the method, comprising the following steps:
s1: providing a semiconductor substrate, and sequentially forming a gate dielectric layer and a polysilicon layer on the semiconductor substrate;
s2: forming a silicon oxide mask layer on the polysilicon layer, patterning, and etching the polysilicon layer and the gate dielectric layer by taking the patterned silicon oxide mask layer as a mask to form a false gate structure isolated by a groove, wherein the groove exposes the semiconductor substrate;
s3: forming an interlayer dielectric layer with a preset thickness in the groove, wherein the top surface of the interlayer dielectric layer is lower than the top surface of the dummy gate structure and higher than the top surface of the polysilicon layer;
s4: modifying the interlayer dielectric layer by adopting an ion implantation process;
s5: removing the silicon oxide mask layer and the polysilicon layer;
s6: and depositing a metal layer on the gate dielectric layer to form a metal gate.
First, referring to fig. 3, step S1 is performed: a semiconductor substrate 1 is provided, and a gate dielectric layer 2 and a polysilicon layer 3 are sequentially formed on the semiconductor substrate 1.
As an example, the semiconductor substrate 1 is not particularly limited, and may be a silicon substrate, a germanium substrate, a silicon on insulator, a germanium on insulator, or the like, and may also be silicon germanium, gallium arsenide, or the like, and the present embodiment employs a silicon substrate.
As an example, the semiconductor substrate 1 includes a first conductivity type channel field effect transistor region i and a second conductivity type channel field effect transistor region ii, and further includes a step (not shown) of forming a source region, a drain region, and a channel region in the first conductivity type channel field effect transistor region and forming a source region, a drain region, and a channel region in the second conductivity type channel field effect transistor region, before forming the gate dielectric layer 2 and the polysilicon layer 3.
As an example, the first conductivity type channel fet is a P-channel fet (pFET) and the second conductivity type channel fet is an N-channel fet (nFET).
As an example, the gate dielectric layer 2 is a silicon oxide layer.
Next, referring to fig. 4, step S2 is performed: and forming a silicon oxide mask layer 4 on the polysilicon layer 3 and patterning, etching the polysilicon layer 3 and the gate dielectric layer 2 by taking the patterned silicon oxide mask layer 4 as a mask to form a dummy gate structure 6 isolated by a groove 5, wherein the groove 5 exposes the semiconductor substrate 1.
As an example, after the dummy gate structure 6 is formed, a step of forming a sidewall protection layer 7 on a sidewall of the dummy gate structure 6 is further included, where a material of the sidewall protection layer 7 includes silicon oxygen carbon nitride (SiOCN).
As an example, in the first conductivity type channel field effect tube region, the semiconductor substrate 1 corresponding to the trench 5 is a source region or a drain region of a P-channel field effect tube, in the second conductivity type channel field effect tube region, the semiconductor substrate 1 corresponding to the trench 5 is a source region or a drain region of an N-channel field effect tube, in order to improve device performance, the SiGe layer 8 is embedded in the source region and the drain region of the P-channel field effect tube to provide compressive stress to the channel, to improve hole mobility, and the SiP layer (not shown) is embedded in the source region and the drain region of the N-channel field effect tube to provide tensile stress to the channel, to improve carrier mobility.
As an example, before the SiGe layer and the SiP layer are embedded, a groove is formed before etching the region to be embedded, then the SiGe layer and the SiP layer are embedded in the groove, and the groove etching amount of the SiGe embedded region is greater than that of the SiP embedded region, so that the consumption amount of the silicon oxide mask layer 4 of the P-channel field effect transistor region is greater than that of the silicon oxide mask layer 4 of the N-channel field effect transistor region.
As an example, referring to fig. 5, a polish stop layer 9 is formed on the surface of the dummy gate structure 6, the polish stop layer 9 extends to the exposed surface of the semiconductor substrate 1, and the material of the polish stop layer 9 includes silicon nitride.
Next, referring to fig. 6 to 8, step S3 is performed: an interlayer dielectric layer 11 with a preset thickness is formed in the groove 5, and the top surface of the interlayer dielectric layer 11 is lower than the top surface of the dummy gate structure 6 and higher than the top surface of the polysilicon layer 3.
As an example, the gap filling process is adopted to form the interlayer dielectric material layer 10 in the trench 5, and the material of the interlayer dielectric material layer 10 includes silicon oxide, because in this embodiment, only a silicon oxide mask layer is adopted, compared with the existing process adopting two hard mask layers of silicon nitride and silicon oxide, the aspect ratio of the trench 5 can be reduced, which is beneficial to gap filling of the trench 5 and reduces the filling difficulty.
As an example, as shown in fig. 6, in the process of forming the interlayer dielectric material layer 10 in the trench 5, the interlayer dielectric material layer 10 is inevitably formed on the upper surface of the dummy gate structure 6, and the material of the interlayer dielectric material layer 10 includes silicon oxide.
As an example, as shown in fig. 7, a chemical mechanical polishing process is used, where the polishing stop layer 9 is used as a stop layer, to remove the interlayer dielectric material layer 10 above the dummy gate structure 6, and of course, an etching process may also be used to remove the interlayer dielectric material layer 10 above the dummy gate structure 6.
As an example, as shown in fig. 8, the interlayer dielectric material layer 10 is etched back by using a dry etching process to form the interlayer dielectric layer 11 with a predetermined thickness, and in other embodiments, the interlayer dielectric material layer 10 may be etched back by using a wet etching process.
Next, referring to fig. 9 and 10, step S4 is performed: and modifying the interlayer dielectric layer 11 by adopting an ion implantation process.
As an example, as shown in fig. 9, a first photoresist layer 12 is formed on the structure after the interlayer dielectric layer 11 is formed, and the first photoresist layer 12 is patterned to expose the first conductive type channel field effect transistor region.
As an example, as shown in FIG. 10, the energy is 2 to 6keV and the dose is e15 to e16 cm -2 The implantation element is silicon, and the ion implantation is performed on the interlayer dielectric layer 10 of the first conduction type channel field effect transistor region to modify the interlayer dielectric layer.
As an example, as shown in fig. 11, after the ion implantation process is completed, the step of removing the first photoresist layer 12 is further included, and the first photoresist layer 12 is removed by an ashing process in this embodiment.
Next, referring to fig. 12 to 19, step S5 is performed: and removing the silicon oxide mask layer 2 and the polysilicon layer 3.
As an example, as shown in fig. 12, a second photoresist layer 13 is formed on the structure after the ion implantation is completed, and the second photoresist layer 12 is patterned to expose the second conductive type channel fet region.
As an example, before forming the second photoresist layer 13, a first bottom anti-reflective coating (BARC) 14 is formed on the structure after the ion implantation, and a planarization process is performed, so that the filling capability of the BARC is good, a gap can be well filled to achieve the purpose of planarization, and then the second photoresist layer 13 is formed on the first bottom anti-reflective coating 14.
As an example, the first bottom anti-reflective layer 14 is an organic bottom anti-reflective layer.
As an example, as shown in fig. 13, the polysilicon layer 3 is used as a stop layer, and a dry etching process is used to remove the structure above the polysilicon layer 3 in the second conductivity type channel field effect tube region, and in other embodiments, a wet etching process or a mechanical polishing process may be used to remove the structure above the polysilicon layer 3 in the second conductivity type channel field effect tube region.
As an example, as shown in fig. 14, the second photoresist layer 13 and the first bottom anti-reflection layer 14 are removed using an ashing process.
As an example, as shown in fig. 15, a third photoresist layer 15 is formed on the structure after the first bottom anti-reflection layer 14 and the second photoresist layer 13 are removed, and the third photoresist layer 15 is patterned to expose the first conductivity type channel field effect transistor region, and similarly, a second bottom anti-reflection layer 16 is formed before the third photoresist layer 15 is formed for planarization.
As an example, as shown in fig. 16, the modified interlayer dielectric layer 11 is used as a stop layer, and a dry etching process is used to remove the structure above the interlayer dielectric layer 11, and in other embodiments, a wet etching process or a mechanical polishing process may be used to remove the structure above the interlayer dielectric layer 11.
As an example, as shown in fig. 17, the silicon oxide mask layer 4 above the polysilicon layer 3 in the first conductivity type channel field effect tube region is removed using a dry etching process.
As an example, as shown in fig. 18, the third photoresist layer 15 and the second bottom anti-reflection layer 16 are removed using an ashing process.
As an example, as shown in fig. 19, the polysilicon layer 3 in the first conductivity type channel field effect transistor region and the second conductivity type channel field effect transistor region is removed using a dry etching process.
Next, referring to fig. 20, step S5 is performed: a metal layer is deposited on the gate dielectric layer 2 to form a metal gate 17.
As an example, the material of the metal layer may be any suitable gate metal material, and tungsten is used in this embodiment.
As an example, the gate height of the N-channel field effect transistor is equal to the height of the polysilicon layer 3, the gate height of the P-channel field effect transistor is higher than the height of the polysilicon layer 2, in step S3, the gate height is compensated by adjusting the height of the interlayer dielectric layer 11, for example, the thickness of the polysilicon layer is 500nm, when the gate height of 600nm is required, the interlayer dielectric layer is made higher than the polysilicon layer by 100nm, in step S4, the interlayer dielectric layer is modified, the loss of the interlayer dielectric layer is prevented as a stop layer when the silicon oxide mask layer above the polysilicon layer is etched, and the gate height is adjusted.
In this embodiment, the first conductivity type channel field effect transistor is a P-channel field effect transistor, the second conductivity type channel field effect transistor is an N-channel field effect transistor, and in other embodiments, the first conductivity type channel field effect transistor is an N-channel field effect transistor, and the second conductivity type channel field effect transistor is a P-channel field effect transistor, that is, the gate height of the N-channel field effect transistor is compensated.
Compared with the prior art that the gate is formed by etching the filling metal of the polysilicon layer, the height of the gate is not adjustable after the polysilicon layer is formed, the method has the advantage of flexibly manufacturing the gate height by carrying out ion implantation modification on the interlayer dielectric layer and compensating the height of the gate by the height of the interlayer dielectric layer after the polysilicon layer is formed.
Example two
The difference between the gate manufacturing method and the first embodiment is that:
in step S4, the interlayer dielectric layer 11 of the first conductivity type channel field effect transistor region and the second conductivity type channel field effect transistor region is modified by an ion implantation process.
In step S5, the structure above the interlayer dielectric layer 11 of the first conductivity type channel field effect transistor region and the second conductivity type channel field effect transistor region is removed by taking the modified interlayer dielectric layer 11 as a stop layer, and then the silicon oxide mask layer and the polysilicon layer of the first conductivity type channel field effect transistor region and the second conductivity type channel field effect transistor region are etched and removed.
In this embodiment, the gate heights of the P-channel field effect transistor and the N-channel field effect transistor are compensated to regulate the gate heights of the P-channel field effect transistor and the N-channel field effect transistor.
Example III
The difference between the gate manufacturing method and the first embodiment is that:
in step S1, the semiconductor substrate 1 includes only one of the first conductivity type channel field effect transistor region or the second conductivity type channel field effect transistor region;
in step S4, the interlayer dielectric layer 11 on the semiconductor substrate 1 is modified;
in step S5, the structure above the interlayer dielectric layer 11 of the first conductivity type channel field effect transistor region or the second conductivity type channel field effect transistor region is removed by taking the modified interlayer dielectric layer 11 as a stop layer, and then the silicon oxide mask layer and the polysilicon layer of the first conductivity type channel field effect transistor region or the second conductivity type channel field effect transistor region are etched and removed.
That is, in this embodiment, the semiconductor substrate includes only one of the P-channel field effect transistor and the N-channel field effect transistor, and the gate height thereof is compensated and controlled.
In summary, in the gate manufacturing method of the present invention, only the silicon oxide mask layer is formed on the polysilicon layer, which reduces the aspect ratio of the trench and facilitates the gap filling of the trench; and the interlayer dielectric layer is modified by adopting an ion implantation process and is used as a stop layer for etching the dummy gate structure, the height of the polysilicon layer is compensated by the height of the modified interlayer dielectric layer, the height of the gate can be adjusted, and the method has the advantage of flexible and adjustable gate height. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The grid manufacturing method is characterized by comprising the following steps of:
s1: providing a semiconductor substrate, and sequentially forming a gate dielectric layer and a polysilicon layer on the semiconductor substrate;
s2: forming a silicon oxide mask layer on the polysilicon layer, patterning, and etching the polysilicon layer and the gate dielectric layer by taking the patterned silicon oxide mask layer as a mask to form a false gate structure isolated by a groove, wherein the groove exposes the semiconductor substrate;
s3: forming an interlayer dielectric layer with a preset thickness in the groove, wherein the top surface of the interlayer dielectric layer is lower than the top surface of the dummy gate structure and higher than the top surface of the polysilicon layer;
s4: modifying the interlayer dielectric layer by adopting an ion implantation process;
s5: removing the silicon oxide mask layer and the polysilicon layer;
s6: and depositing a metal layer on the gate dielectric layer to form a metal gate.
2. The method for manufacturing a gate according to claim 1, wherein: before executing step S3, the method further comprises the following steps:
forming a side wall protection layer on the side wall of the dummy gate structure;
and forming a grinding stop layer on the surface of the false gate structure, wherein the grinding stop layer extends to the exposed surface of the semiconductor substrate.
3. The method for manufacturing a gate according to claim 1, wherein: in step S1, the semiconductor substrate includes a first conductivity type channel field effect transistor region and a second conductivity type channel field effect transistor region; in step S4, the interlayer dielectric layer in the first conduction type channel field effect transistor region is subjected to ion implantation with implantation energy of 2-6 keV and implantation dosage of e 15-e 16 cm -2 The implant element comprises silicon.
4. A method of fabricating a gate as claimed in claim 3, wherein: in step S4, a first photoresist layer is formed on the structure after the interlayer dielectric layer is formed before the ion implantation, and the first photoresist layer is patterned to expose the first conductivity type channel field effect transistor region.
5. A method of fabricating a gate as claimed in claim 3, wherein: in step S1, the first conductivity type channel field effect transistor is a P-channel field effect transistor, and the second conductivity type channel field effect transistor is an N-channel field effect transistor; in step S2, after the trench is formed, a step of embedding a SiGe layer in the semiconductor substrate exposed by the P-channel field effect transistor region and a step of embedding a SiP layer in the semiconductor substrate exposed by the N-channel field effect transistor region are further included.
6. The method of fabricating a gate electrode according to claim 3, wherein in step S5, the step of removing the silicon oxide mask layer and the polysilicon layer comprises:
s50: removing the structure above the polysilicon layer in the second conductivity type channel field effect tube region;
s51: removing the structure above the interlayer dielectric layer in the first conduction type channel field effect tube region;
s52: removing the silicon oxide mask layer above the polysilicon layer in the first conductivity type channel field effect tube region;
s53: and removing the polysilicon layer in the first conductive type channel field effect transistor region and the second conductive type channel field effect transistor region.
7. The method for manufacturing a gate according to claim 6, wherein: in step S50, before removing the structure above the polysilicon layer in the second conductivity type channel field effect transistor region, a second photoresist layer is formed on the structure after ion implantation is completed, and the second photoresist layer is patterned to expose the second conductivity type channel field effect transistor region.
8. The method for manufacturing a gate according to claim 7, wherein: and before forming the second photoresist layer, forming a first bottom anti-reflection layer on the structure after ion implantation, and forming the second photoresist layer on the first bottom anti-reflection layer.
9. The method for manufacturing a gate according to claim 6, wherein: in step S51, before removing the structure above the interlayer dielectric layer in the first conductivity type channel field effect transistor region, a third photoresist layer is formed on the structure after the step S50 is completed, and the third photoresist layer is patterned to expose the first conductivity type channel field effect transistor region.
10. The method for manufacturing a gate according to claim 9, wherein: and before forming the third photoresist layer, forming a second bottom anti-reflection layer on the structure after the step S50 is completed, and forming the third photoresist layer on the second bottom anti-reflection layer.
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