CN112366179A - Semiconductor device structure and preparation method - Google Patents
Semiconductor device structure and preparation method Download PDFInfo
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- CN112366179A CN112366179A CN202011102126.1A CN202011102126A CN112366179A CN 112366179 A CN112366179 A CN 112366179A CN 202011102126 A CN202011102126 A CN 202011102126A CN 112366179 A CN112366179 A CN 112366179A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 230000004888 barrier function Effects 0.000 claims abstract description 71
- 238000005468 ion implantation Methods 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 17
- 230000000903 blocking effect Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 75
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 9
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000009826 distribution Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 257
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 239000002184 metal Substances 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 239000000470 constituent Substances 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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Abstract
The invention provides a semiconductor device structure and a preparation method, wherein the preparation method comprises the following steps: providing a semiconductor substrate with a gate oxide layer formed on the surface; forming a patterned gate layer and a barrier layer covering the top of the gate layer above the gate oxide layer; and performing first ion implantation on the semiconductor substrate to form a first doped region in the semiconductor substrate, wherein the blocking layer is configured to block ions from entering a region of the semiconductor substrate below the gate layer during the first ion implantation. According to the invention, the barrier layer for ion implantation is introduced at the top of the gate layer, so that ions during high-energy ion implantation can not be implanted into a channel region below the gate layer under the condition that the characteristic size of a semiconductor manufacturing process is reduced and the gate layer is thin; in addition, the invention also effectively integrates the high-voltage device region and the low-voltage device region in the same device structure.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device structure and a method for fabricating the same.
Background
In order to improve the performance of phase change memory (PCRAM) and 3D NAND integrated circuit devices, the number of devices on a unit area of a wafer is continuously increased, the characteristic size of a semiconductor manufacturing process is continuously reduced, and the line width and the thickness of a gate polycrystalline silicon layer in a semiconductor device are also reduced; there is also a need to integrate High Voltage (HV) devices and Low Voltage (LV) devices simultaneously in the same device, depending on device design requirements.
Currently, in MOS circuits having a High Voltage (HV) device region, a high voltage lowly doped drain region (HV LDD region) is generally formed by ion implantation. And when the high-voltage low-doped drain region is implanted, the grid polycrystalline silicon layer of the high-voltage region is used as an ion implantation barrier layer, so that the self-alignment process of the high-voltage low-doped drain ion implantation is realized.
However, since the thickness of the gate polysilicon layer is continuously reduced along with the reduction of the feature size, in the advanced MOS process, the thin gate polysilicon layer cannot serve as an ion implantation blocking layer, and when high-energy high-voltage low-doped drain ions are implanted, high-energy ions pass through the gate polysilicon layer and enter the gate oxide layer and the channel region below the gate polysilicon layer, thereby affecting the performance of the device. Furthermore, how to effectively integrate High Voltage (HV) and Low Voltage (LV) device regions in the same device structure is also an urgent requirement of related device designs.
Therefore, there is a need for a new semiconductor device structure and fabrication method that solves the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device structure and a manufacturing method thereof, which are used to solve the problem that the thin gate polysilicon layer in the prior art cannot effectively block the high-energy ion implantation into the channel region.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device structure, comprising the steps of:
providing a semiconductor substrate with a gate oxide layer formed on the surface;
forming a patterned gate layer and a barrier layer covering the top of the gate layer above the gate oxide layer;
and performing first ion implantation on the semiconductor substrate to form a first doped region in the semiconductor substrate, wherein the blocking layer is configured to block ions from entering a region of the semiconductor substrate below the gate layer during the first ion implantation.
As an alternative of the invention, the gate layer comprises a polysilicon layer and the barrier layer comprises a silicon nitride layer.
As an alternative of the present invention, the process of forming the gate layer and the barrier layer comprises the steps of:
sequentially depositing a grid material layer and a blocking material layer above the semiconductor substrate;
forming a patterned photoresist layer over the barrier material layer by a photolithography process;
and forming the patterned gate layer and the barrier layer by using the photoresist layer as an etching mask through a dry etching process.
As an alternative of the present invention, an amorphous carbon layer and an anti-reflection layer are further formed between the barrier material layer and the photoresist layer; and a stress buffer layer is also formed between the grid layer and the barrier layer.
As an alternative of the present invention, after the first ion implantation, a process of performing an annealing process on the first doped region is further included.
As an alternative of the present invention, the semiconductor substrate is divided into a high-voltage device region and a low-voltage device region, the first doped region is formed in the high-voltage device region, the gate layer and the barrier layer are distributed in the high-voltage device region and the low-voltage device region, and the gate oxide layer is distributed below the gate layer in the high-voltage device region and the low-voltage device region; after the first doping area is formed, a process of forming a second doping area in the low-voltage device area is further included; the process of forming the second doped region comprises the following steps:
removing the barrier layer;
and in the low-voltage device area, the grid layer is used as a barrier layer for ion implantation, second ion implantation is carried out on the semiconductor substrate, a second doped area is formed in the semiconductor substrate, and the distribution area of the second doped area does not include the area of the semiconductor substrate below the grid layer.
As an alternative of the present invention, before performing the second ion implantation, a process of forming a sidewall layer on a sidewall of the gate layer is further included.
As an alternative of the present invention, the thickness of the gate oxide layer in the high-voltage device region is thicker than the thickness of the gate oxide layer in the low-voltage device region.
As an alternative of the present invention, a well region is further formed in the semiconductor substrate provided with the gate oxide layer formed on the surface thereof; after the second doping region is formed, a process of forming a source region and a drain region in the semiconductor substrate is also included.
The present invention also provides a semiconductor device structure, comprising:
a semiconductor substrate with a gate oxide layer formed on the surface;
the patterned grid layer is positioned above the grid oxide layer, and the barrier layer covers the top of the grid layer;
a first doped region formed in the semiconductor substrate, a distribution region of the first doped region excluding a region of the semiconductor substrate below the gate layer.
As an alternative of the invention, the gate layer comprises a polysilicon layer and the barrier layer comprises a silicon nitride layer.
As an alternative of the present invention, a stress buffer layer is further formed between the gate layer and the barrier layer.
As described above, the present invention provides a semiconductor device structure and a manufacturing method, which have the following beneficial effects:
according to the invention, the barrier layer for ion implantation is introduced at the top of the gate layer, so that ions during high-energy ion implantation can not be implanted into a channel region below the gate layer under the condition that the characteristic size of a semiconductor manufacturing process is reduced and the gate layer is thin; in addition, the invention also effectively integrates the high-voltage device region and the low-voltage device region in the same device structure.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor device structure according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a film structure before etching a gate layer and a barrier layer according to a first embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a high-voltage device region after etching a gate layer and a barrier layer according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a low-voltage device region after etching a gate layer and a barrier layer according to a first embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a high-voltage device region after a thermal oxide layer is formed in the high-voltage device region according to a first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a low-voltage device region after a thermal oxide layer is formed in accordance with a first embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a high-voltage device region provided in the first embodiment of the present invention during the first ion implantation.
Fig. 8 is a schematic cross-sectional view of a low-voltage device region provided in a first embodiment of the present invention during a first ion implantation.
Fig. 9 is a schematic cross-sectional view of a high-voltage device region provided in the first embodiment of the present invention after the first ion implantation.
Fig. 10 is a schematic cross-sectional view of a low-voltage device region provided in a first embodiment of the present invention after a first ion implantation.
Fig. 11 is a schematic cross-sectional view of a high-voltage device region provided in the first embodiment of the invention after removing the barrier layer.
Fig. 12 is a schematic cross-sectional view of a low-voltage device region provided in a first embodiment of the invention after removing the barrier layer.
Fig. 13 is a schematic cross-sectional view of a high-voltage device region after forming a sidewall layer according to an embodiment of the invention.
Fig. 14 is a schematic cross-sectional view of a low-voltage device region after forming a sidewall layer according to an embodiment of the invention.
Fig. 15 is a schematic cross-sectional view of a low-voltage device region provided in a first embodiment of the present invention after a second ion implantation.
Description of the element reference numerals
101 semiconductor substrate
102 gate oxide layer
103 gate layer
103a layer of gate material
104 barrier layer
104a layer of barrier material
105 first doped region
105a photoresist layer
106 photoresist layer
107 amorphous carbon layer
108 anti-reflection layer
109 stress buffer layer
110 hot oxygen layer
111 second doped region
112 side wall layer
S1-S3 Steps 1) -3)
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 15. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 15, the present embodiment provides a method for manufacturing a semiconductor device structure, which includes: the method comprises the following steps:
1) providing a semiconductor substrate 101 with a gate oxide layer 102 formed on the surface;
2) forming a patterned gate layer 103 and a barrier layer 104 covering the top of the gate layer 103 above the gate oxide layer 102;
3) performing a first ion implantation on the semiconductor substrate 101 to form a first doped region 105 in the semiconductor substrate 101, wherein the blocking layer 104 is configured to block ions from entering a region of the semiconductor substrate 101 below the gate layer 102 during the first ion implantation.
In step 1), referring to step S1 of fig. 1 and fig. 2 to 4, the semiconductor substrate 101 having the gate oxide layer 102 formed on the surface thereof is provided. Optionally, the semiconductor substrate 101 includes a silicon substrate.
As an example, as shown in fig. 3 and 4, the semiconductor substrate 101 may be further divided into a High Voltage (HV) device region and a Low Voltage (LV) device region according to device design requirements. Fig. 3 shows the case of the high-voltage device region, and fig. 4 shows the case of the low-voltage device region. Optionally, the high voltage device region and the low voltage device region are separated by a shallow trench isolation structure, which is not shown in fig. 3 or fig. 4. Due to different device requirements, the thickness of the gate oxide layer 102 in the high-voltage device region is different from that in the low-voltage device region, and the thickness of the gate oxide layer 102 in the high-voltage device region is thicker than that of the gate oxide layer 102 in the low-voltage device region. Optionally, the thickness of the gate oxide layer 102 in the high voltage device region is about
On the other hand, the thickness of the gate oxide layer 102 in the low-voltage device region is about several tens of
As can be seen from fig. 3 and 4, in the high-voltage device region, the gate oxide layer 102 is distributed on the entire surface of the semiconductor substrate 101, and in the low-voltage device region, the gate oxide layer 102 is distributed only under the gate layer 103, because the gate oxide layer 102 of the low-voltage device region is thin (about tens of thickness)
) And is consumed in the processes of gate etching, subsequent cleaning and the like.
As an example, a well region, which may be formed by furnace tube diffusion or ion implantation and is not shown in fig. 2, is further formed in the semiconductor substrate 101 on which the gate oxide layer 102 is formed.
In step 2), referring to step S2 of fig. 1 and fig. 2 to 4, a patterned gate layer 103 and a barrier layer 104 covering the top of the gate layer 103 are formed over the gate oxide layer 102.
As an example, the gate layer 103 includes a polysilicon layer, and the barrier layer 104 includes a silicon nitride layer. Optionally, the gate layer 103 has a thickness of about
On the other hand, the barrier layer 104 may have a thickness of about several hundred
For example 300 to
For semiconductor process with increasingly smaller feature sizes, the thickness of the gate layer 103 is further reduced to about 45nm with the line width reduction
From side to side and even thinnerDegree of the disease. The gate layer 103 with an excessively thin thickness cannot effectively act as an ion implantation barrier layer in the high-energy ion implantation process, and the barrier layer 104 is introduced to effectively block the high-energy ion implantation, so that ions outside the design are prevented from entering a gate oxide layer and a device channel region below the gate to influence the device performance. The material and thickness of the barrier layer 104 may also be adjusted accordingly according to the gate process and the ion implantation conditions.
As an example, as shown in fig. 2 to 4, the process of forming the gate layer 103 and the barrier layer 104 includes the following steps:
sequentially depositing a gate material layer 103a and a barrier material layer 104a over the semiconductor substrate 101;
forming a patterned photoresist layer 106 over the barrier material layer 104a by a photolithography process;
and forming the patterned gate layer 103 and the patterned barrier layer 104 by using the photoresist layer 106 as an etching mask through a dry etching process.
As an example, as shown in fig. 3, after the patterned gate layer 103 and the patterned barrier layer 104 are formed in the high-voltage device region by a dry etching process; as shown in fig. 4, after the patterned gate layer 103 and the patterned barrier layer 104 are formed by a dry etching process in the low-voltage device region.
As an example, as shown in fig. 2, an amorphous carbon layer 107 and an anti-reflective layer 108 are further formed between the barrier material layer 104a and the photoresist layer 106; a stress buffer layer 109 is further formed between the gate material layer 103a and the barrier material layer 104 a. Optionally, the anti-reflection layer 108 is a silicon oxynitride layer for playing a role of anti-reflection in the photolithography process; the stress buffer layer 109 is a silicon dioxide layer, and is used for solving the adhesion problem between the silicon nitride layer and the polysilicon layer due to stress.
As an example, in the dry etching process, the patterned amorphous carbon layer 107 may be etched by using the patterned photoresist layer 106 as an etching mask, and then the patterned amorphous carbon layer 107 may also be used as an etching mask to etch the gate layer 103 and the barrier layer 104. This is because the amorphous carbon layer 107 has a higher etching selectivity when etching silicon nitride and polysilicon than the photoresist layer 106, which can prevent the occurrence of insufficient photoresist during etching silicon nitride and polysilicon.
Optionally, the photoresist layer 106 has a thickness of about
On the other hand, the thickness of the anti-reflection layer 108 and the amorphous carbon layer 107 is about several hundreds of
The stress buffer layer 109 has a thickness of about several tens of a
The composition and thickness of each layer can also be adjusted according to the actual conditions of the process.
In step 3), please refer to step S3 of fig. 1 and fig. 5 to 10, a first ion implantation is performed on the semiconductor substrate 101 to form a first doped region 105 in the semiconductor substrate 101, and the blocking layer 104 is configured to block ions from entering a region of the semiconductor substrate 101 below the gate layer 102 during the first ion implantation.
As an example, as shown in fig. 5 and 6, after the gate layer 103 and the barrier layer 104 are formed by etching in step 2), a thermal oxide layer 110 is formed by thermal oxidation on the gate layer 103 made of a silicon material and the semiconductor substrate 101 in the low-voltage device region through a furnace process, and the thickness of the thermal oxide layer is about several tens of thicknesses
The thermal oxide layer 110 is also formed on the surface of the barrier layer 104 made of silicon nitride, but is relatively thin (less than)
). It is noted that, in the present embodiment, the thermal oxide layer 110, the stress buffer layer 109 and the gate oxide layer 102 are formedThe constituent materials are silicon dioxide and thus have no apparent boundaries in actual devices.
As an example, as shown in fig. 7, a first doping region 105 is formed in the semiconductor substrate 101 of the high-voltage device region by first ion implantation as shown by an arrow direction, and due to the blocking effect of the gate layer 103 and the blocking layer 104, a formation region of the first doping region 105 does not include a region of the semiconductor substrate 101 below the gate layer 102. Optionally, the first ion implantation forms a high voltage low doped drain region (HV LDD region) of the semiconductor device. In the low-voltage device region, as shown in fig. 8, the first doped region 105 is formed only in the high-voltage device region by ion implantation through the photoresist layer 105 a. Optionally, after the first ion implantation, a process of performing an annealing process on the first doped region 105 is further included. The injected ions are diffused and activated by repairing the crystal lattice damage through an annealing process, the annealing process comprises furnace tube annealing or laser annealing and other process methods, and the injected region is expanded in a certain transverse direction after the annealing process.
As an example, as shown in fig. 9 and 10, it is the case of the high voltage device region and the low voltage device region after the first ion implantation and annealing process. Wherein the first doped region 105 has been formed in the high voltage device region, and the photoresist layer 105a is also removed in the low voltage device region. In fig. 9 and 10, the thinner layer 110 of hot oxygen (less than that of the barrier layer 104) at the surface of the barrier layer 104 is also washed away by a dilute hydrofluoric acid solution
) The gate layer 103 and the thicker thermal oxide layer 110 of the semiconductor substrate 101 in the low-voltage device region remain to have a thickness of about several tens of a
As an example, as shown in fig. 11 to 15, after the first doping region 105 is formed, a process of forming a second doping region 111 in the low-voltage device region is further included; the process of forming the second doped region 111 includes the following steps:
removing the barrier layer 104;
and in the low-voltage device area, performing second ion implantation on the semiconductor substrate 101 by using the gate layer 103 as a barrier layer of the ion implantation, and forming a second doped area 111 in the semiconductor substrate 101, wherein the distribution area of the second doped area 111 does not include the area of the semiconductor substrate 101 below the gate layer 103.
As an example, as shown in fig. 9 to 12, the barrier layer 104 made of a silicon nitride material is removed by a phosphoric acid wet etching process in the high-voltage device region and the low-voltage device region.
As an example, as shown in fig. 13 and 14, before the second ion implantation, a process of forming a sidewall layer 112 on a sidewall of the gate layer 103 is further included. Optionally, the sidewall layer 112 is made of a silicon nitride material. The method for forming the sidewall layer 112 includes: a silicon nitride material layer is uniformly deposited on the semiconductor substrate 101, including the gate layer 103 and the sidewall, by a silicon nitride deposition process, the silicon nitride layers on the semiconductor substrate 101 and the gate layer 103 are removed by an anisotropic silicon nitride dry etching process, and the silicon nitride layer on the sidewall of the gate layer 103 is retained, thereby forming the sidewall layer 112.
As an example, as shown in fig. 15, a second doped region 111 is formed in the semiconductor substrate 101 of the low-voltage device region by a second ion implantation. The gate layer 103 and the sidewall layer 112 serve as a barrier layer for ion implantation in the second ion implantation process, and prevent ions outside the design from entering the channel layer below the gate layer 103. By introducing the sidewall layer 112, the shielding range of both sides of the gate layer 103 is expanded, and the implantation coverage area of the second ion implantation is adjusted. The sidewall layer 112 can also enhance electrical isolation between the gate layer 103 and a subsequently formed contact hole structure. After the second ion implantation process, a step of performing an annealing process on the second doped region 111 is also included. Compared with the first ion implantation process, the implantation energy of the second ion implantation is lower, the ion implantation can be effectively blocked by the gate layer 103, and the formed second doped region 111 is shallower than the first doped region 105. Optionally, the second ion implantation forms a low voltage low doped drain region (LV LDD region) of the semiconductor device. In the process of performing the second ion implantation on the low-voltage device region, the second ion implantation may also be performed simultaneously in the high-voltage device region, or the second ion implantation may also be blocked by a photoresist. In this embodiment, through two ion implantation processes with different energies, respective LDD regions are formed in the high voltage device region and the low voltage device region, and the high voltage device process and the low voltage device process are effectively integrated in the same device process. In addition, the preparation method of the embodiment can also be used in other process technologies such as a 3D NAND CMOS wafer, and the like, and is also used for solving the problem that the gate structure in the existing process cannot effectively block the implantation of high-energy high-voltage low-doped drain ions. It should be further noted that, in the present embodiment, the blocking layer 104 is introduced to block the high-voltage low-doped drain ion implantation, but in other embodiments of the present invention, the blocked ion implantation process is not limited to the high-voltage low-doped drain ion implantation, and may be any other high-energy implantation process with a thinner gate layer.
As an example, after the second doping region is formed, a process of forming a source region and a drain region in the semiconductor substrate is further included. Optionally, the source region and the drain region are formed by an ion implantation process, and a self-aligned metal silicide layer (salicide) is formed in the source region and the drain region. In addition, after the process, the structures such as an interlayer dielectric layer, a contact hole structure, a metal wiring layer and the like can be further formed by adopting a conventional back-end process so as to realize the electrical connection between the high-voltage device area and the low-voltage device area.
Example two
Referring to fig. 3 and 7, the present embodiment provides a semiconductor device structure, including:
a semiconductor substrate 101 having a gate oxide layer 102 formed on a surface thereof;
a patterned gate layer 103 located above the gate oxide layer 102 and a barrier layer 104 covering the top of the gate layer 103;
a first doped region formed in the semiconductor substrate, a distribution region of the first doped region excluding a region of the semiconductor substrate below the gate layer.
As shown in fig. 3, the gate oxide layer 102 is located on the surface of the semiconductor substrate 101. Alternatively, shown in fig. 3 is a high voltage device region of a semiconductor device. And the gate layer 103 and the barrier layer 104 are patterned by dry etching. As shown in fig. 7, the first doping region 105 is formed by high-energy ion implantation, and the distribution region of the first doping region 105 does not include the region of the semiconductor substrate 101 below the gate layer 103. In the semiconductor device structure provided by this embodiment, the blocking layer 104 is introduced to effectively block high-energy ion implantation, and prevent ions outside the design from entering the gate oxide layer 102 and the channel region below the gate layer 103.
As an example, the gate layer 103 includes a polysilicon layer, and the barrier layer 104 includes a silicon nitride layer. Optionally, the gate oxide layer 102 has a thickness of about
On the other hand, the thickness of the gate layer 103 is about
On the other hand, the barrier layer 104 may have a thickness of about several hundred
For example 300 to
By introducing the barrier layer 104, high-energy ion implantation can be effectively blocked, and ions outside the design are prevented from entering a gate oxide layer and a device channel region below the grid electrode to influence the device performance. The material and thickness of the barrier layer 104 may also be adjusted accordingly according to the gate process and the ion implantation conditions.
As an example, a stress buffer layer 109 is further formed between the gate layer 103 and the barrier layer 104. The stress buffer layer 109 is a silicon dioxide layer, and is used to solve the adhesion problem between the barrier layer 104 made of silicon nitride and the gate layer 103 made of polysilicon due to stress.
In summary, the present invention provides a semiconductor device structure and a method for manufacturing the same, wherein the method for manufacturing the semiconductor device structure comprises the following steps: providing a semiconductor substrate with a gate oxide layer formed on the surface; forming a patterned gate layer and a barrier layer covering the top of the gate layer above the gate oxide layer; and performing first ion implantation on the semiconductor substrate to form a first doped region in the semiconductor substrate, wherein the blocking layer is configured to block ions from entering a region of the semiconductor substrate below the gate layer during the first ion implantation. According to the invention, the barrier layer for ion implantation is introduced at the top of the gate layer, so that ions during high-energy ion implantation can not be implanted into a channel region below the gate layer under the condition that the characteristic size of a semiconductor manufacturing process is reduced and the gate layer is thin; in addition, the invention also effectively integrates the high-voltage device region and the low-voltage device region in the same device structure.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. A method for preparing a semiconductor device structure is characterized by comprising the following steps:
providing a semiconductor substrate with a gate oxide layer formed on the surface;
forming a patterned gate layer and a barrier layer covering the top of the gate layer above the gate oxide layer;
and performing first ion implantation on the semiconductor substrate to form a first doped region in the semiconductor substrate, wherein the blocking layer is configured to block ions from entering a region of the semiconductor substrate below the gate layer during the first ion implantation.
2. The method of manufacturing a semiconductor device structure of claim 1, wherein: the gate layer comprises a polysilicon layer and the barrier layer comprises a silicon nitride layer.
3. The method of manufacturing a semiconductor device structure of claim 1, wherein: the process of forming the gate layer and the barrier layer includes the steps of:
sequentially depositing a grid material layer and a blocking material layer above the semiconductor substrate;
forming a patterned photoresist layer over the barrier material layer by a photolithography process;
and forming the patterned gate layer and the barrier layer by using the photoresist layer as an etching mask through a dry etching process.
4. A method of fabricating a semiconductor device structure according to claim 3, characterized in that: an amorphous carbon layer and an anti-reflection layer are further formed between the barrier material layer and the photoresist layer; and a stress buffer layer is also formed between the grid layer and the barrier layer.
5. The method of manufacturing a semiconductor device structure of claim 1, wherein: and after the first ion implantation, the method further comprises the process of carrying out an annealing process on the first doped region.
6. The method of manufacturing a semiconductor device structure of claim 1, wherein: the semiconductor substrate is divided into a high-voltage device area and a low-voltage device area, the first doped area is formed in the high-voltage device area, the gate layer and the barrier layer are distributed in the high-voltage device area and the low-voltage device area, and the gate oxide layer is distributed below the gate layer in the high-voltage device area and the low-voltage device area; after the first doping area is formed, a process of forming a second doping area in the low-voltage device area is further included; the process of forming the second doped region comprises the following steps:
removing the barrier layer;
and in the low-voltage device area, the grid layer is used as a barrier layer for ion implantation, second ion implantation is carried out on the semiconductor substrate, a second doped area is formed in the semiconductor substrate, and the distribution area of the second doped area does not include the area of the semiconductor substrate below the grid layer.
7. The method of manufacturing a semiconductor device structure of claim 6, wherein: before the second ion implantation, a process of forming a sidewall layer on a sidewall of the gate layer is further included.
8. The method of manufacturing a semiconductor device structure of claim 6, wherein: the thickness of the gate oxide layer in the high-voltage device area is thicker than that of the gate oxide layer in the low-voltage device area.
9. The method of manufacturing a semiconductor device structure of claim 6, wherein: a well region is also formed in the semiconductor substrate on which the gate oxide layer is formed on the provided surface; after the second doping region is formed, a process of forming a source region and a drain region in the semiconductor substrate is also included.
10. A semiconductor device structure, comprising:
a semiconductor substrate with a gate oxide layer formed on the surface;
the patterned grid layer is positioned above the grid oxide layer, and the barrier layer covers the top of the grid layer;
a first doped region formed in the semiconductor substrate, a distribution region of the first doped region excluding a region of the semiconductor substrate below the gate layer.
11. The semiconductor device structure of claim 10, wherein: the gate layer comprises a polysilicon layer and the barrier layer comprises a silicon nitride layer.
12. The semiconductor device structure of claim 10, wherein: a stress buffer layer is also formed between the gate layer and the barrier layer.
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