CN101079450A - Fin channel dual-bar multi-function field effect transistor and its making method - Google Patents
Fin channel dual-bar multi-function field effect transistor and its making method Download PDFInfo
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Abstract
The invention provides a fin type channel dual-grid multifunctional field effect transistor and preparing method in metallic oxide semi-conductor field effect transistor technique field of the grand scale integration. The flied effect transistor is based on SOI underlay, the cross section of channel is rectangular fin along the vertical direction of the channel and forms the fin channel; a side of the channel is the grid oxide and the front grip, the other side is the tunnel oxide layer as the silicon nitride trap layer, the barrier oxide layer and the back grip of the charge storage layer and forms dual-grid structure; two edges of the fin channel are connected with the common n+ source and n+ leakage, the front grid aligns the back grid, the n+ source and the n+ leakage are covered less; the device achieves the channel section, the source section and the leakage section on the insulating layer based on SOI underlay. The invention is provided with high-effective MOSFET logical device function, the function of high-speed storage and the function of no condenser type DRAM.
Description
Technical field
The invention belongs to mos field effect transistor (the MetalOxide Semiconductor Field Effect Transistor-MOSFET) technical field in the very lagre scale integrated circuit (VLSIC) (ULSI), be specifically related to a kind of fin channel dual-bar multi-function field effect transistor and preparation method thereof.
Background technology
Along with the extensive use and the high speed development of very lagre scale integrated circuit (VLSIC), based on MOSFET, System on Chip/SoC (System OnChip-SOC) technology more and more causes people's great interest.System on Chip/SoC will realize in the whole system that the unit of difference in functionality or module are integrated on one or the few several integrated circuit (IC) chip of trying one's best, and make each chip can realize multiple function.The SOC technology can overcome the variety of issue (as the reliability of the time-delay between the chip, printed circuit board (PCB)) of the integrated appearance of plate level of multicore sheet, is improving systematic function, reduces power consumption, is being easy to have outstanding advantage aspect the assembling.
The device cell of the integrated multiple difference in functionality of development need while of SOC technology or module are on same chip, for example a kind of SOC technology that is suitable for performance application may need integrated: the high performance MOSFET logical device and based on the flash memory (Flash Memory can be called for short flash memory) of MOSFET structure and DRAM (dynamic RAM) respectively as Fig. 1 (a) and (b) with (c) shown in.But,, make that the unit of integrated two kinds of functions has increased manufacturing cost and realized difficulty on a chip because these three kinds of device cells have different structures and preparation technology.Simultaneously, chip area does not have advantage with respect to the chip area sum on each individual chips.Therefore, do not increase integration density, increased the cost of unit chip area though existing SOC technology has improved systematic function.
At this point, based on MOSFET, from device architecture and preparation method thereof, people have proposed to be suitable for the notion of the multifunction device (multi-functional device) that SOC uses, adopt the device of new structure, can on same device cell, realize multiple function.As document 1 (C.Oh, S.Kim, N.Kim, et al., " A Novel Multi-FunctionalSilicon-On-ONO (SOONO) MOSFETs for SoC applications:Electrical Characterization forHigh Performance Transistor and Embeded Memory Applications ", in Proc.of VLSI Dig.Tech., p.16,2006) shown in, based on MOSFET, proposed to realize the multi-function field effect transistor of multiple device function, as shown in Figure 2.Because this multi-function field effect transistor can possess logical device and two kinds of device functions of flash memory simultaneously or with no capacity MOS FET structure realization DRAM device function, therefore one times integration density nearly can be improved, the cost of unit chip area can be significantly reduced.This multifunction device has wide prospect in the SOC technology is used.
A kind of SOONO structure MOSFET multifunction device shown in the document 1 is equivalent to a kind of planar double-gated devices.Can possess following three kinds of functions.(1) function of high performance MOSFET logical device constitutes device by source, leakage, raceway groove, grid oxygen and preceding grid (FG), operating voltage 1.0V～1.2V (volt), and it is 0V that back of the body grid (BG) are used as underlayer electrode.(2) function of flash memory constitutes device by source, leakage, raceway groove, back of the body grid and back of the body grid ONO stack architectures (comprising tunnel oxide, silicon nitride trap layer, barrier oxide layer), and it is 0V that preceding grid are used as underlayer electrode; Source 0V leaks 3V, and back of the body grid 6V is with the channel hot electron injection programming; Leak 3V, back of the body grid-4V injects realization with the band-to-band-tunneling hot hole and wipes; The source adds small voltage, leaks 0V, reverse read.(3) function of DRAM constitutes device by source, leakage, raceway groove, grid oxygen and preceding grid, and back of the body grid add negative voltage; Before grid 1V, leak and to add high voltage 2V, hot electron is in the ionization that bumps of the drain terminal of raceway groove, the hole of generation is in the accumulation of the raceway groove back side, storage " 1 "; Preceding grid 1V, leakage adds back bias voltage, the hole is swept leakage, storage " 0 "; When reading, leak 0.2V.This capless DRAM, than the DRAM of conventional 1T1C (field-effect transistor adds an electric capacity), simple in structure, scaled down ability is strong, compatible fully with MOSFET technology.
But, this SOONO structure MOSFET multifunction device shown in the document 1, based on planar double-gated devices, there are the following problems: (1) (is respectively 1.4nm because the back of the body grid ONO stack architecture that device architecture and preparation technology cause is too thick, 42nm, 1.4nm, gross thickness reaches about 45nm), make threshold window young (2.5V), back gate voltage during program/erase higher (reaching 6V/-4V), the program/erase time is grown (reaching 0.5ms/0.5ms), application of thin tunnel oxide (1.4nm) makes the retention performance variation, too thick silicon nitride trap layer makes the distribution influence again of iunjected charge arrive the reliability of device simultaneously; (2) tunnel oxide and barrier oxide layer prepare simultaneously, make both have identical thickness, can not carry out the performance that thickness optimization design is improved flash memory respectively; (3) preparation method of conventional relatively MOSFET need to increase by two domains: a Stripe version (removing the SiGe sacrifice layer), one be the deep trench isolation domain, be used for isolating different back of the body grid; (4) back of the body grid cover raceway groove and source, leakage fully, and the band-to-band-tunneling hot hole when wiping can be injected into the overlay area of back of the body grid and leakage, have influence on the DC characteristic and the reliability of device.(5) as the SiGe layer of sacrifice layer with as the silicon layer of raceway groove, all be epitaxially grown, the technology cost is higher.
Summary of the invention
At the problem of the SOONO structure multifunctional MOSFET of above-mentioned document 1, for the multifunction device characteristic that realizes optimizing, improve integration density, the present invention proposes innovation from the device architecture aspect, proposed a kind of fin channel dual-bar multi-function field effect transistor.
A kind of fin channel dual-bar multi-function field effect transistor, this field-effect-transistor-based are in the SOI substrate, and the vertical direction of raceway groove sees that the raceway groove cross section is rectangular fin type Fin (along the vertical direction of raceway groove), form fin channel; One side of fin channel is grid oxygen and preceding grid (polysilicon or metal material), and opposite side is tunnel oxide, the silicon nitride trap layer as charge storage layer, barrier oxide layer and back of the body grid (polysilicon or metal material), forms double-gate structure; The two ends of fin channel connect common n+ source and n+ leaks, preceding grid and the autoregistration of back of the body grid, very little to the covering of n+ source and n+ leakage; Device is realized based on the SOI substrate, channel region, and source region and drain region all are positioned on the insulating barrier.
The cross section of described fin channel is that width W is that 30nm～60nm, height H are the rectangle (W is less than H) of 50nm～100nm.
The thickness of described grid oxygen is 1nm～2nm.
The thickness of described tunnel oxide is that the thickness of 2nm～4nm, silicon nitride trap layer is that the thickness of 4nm～7nm, barrier oxide layer is 4nm～6nm, and the gross thickness of promptly carrying on the back grid ONO stack architecture is 10～17nm.
Another object of the present invention is to, a kind of method for preparing fin channel dual-bar multi-function field effect transistor is provided, may further comprise the steps:
1) on the SOI substrate, thermal oxidation silicon dioxide, deposit silicon nitride again;
2) active area version photoetching, etching silicon dioxide and silicon nitride, silicon forms fin channel;
3) thermal oxidation tunnel oxide, deposit silicon nitride trap layer, deposit silicon dioxide;
4) the outer silicon dioxide of preceding grid one side of bombardment is injected at the argon ion inclination angle;
5) corrode silicon dioxide, corroding silicon nitride, corrode silicon dioxide, the silicon face of grid one side exposes before making, and will carry on the back the grid remaining silica simultaneously as barrier oxide layer, forms back of the body grid ONO stack architecture;
6) gate oxide before the thermal oxidation;
7) deposit or sputter grid material, the photoetching of grid version, impurity injects, and forms n+ source and leakage; The annealing activator impurity;
8) planarization forms self aligned independently preceding grid and back of the body grid.
In the described step 1), selected SOI substrate top silicon surface thickness is 50-100nm, and its thickness has determined the height H of fin channel.
In the described step 3), thermal oxidation tunnel oxide 2-4nm, deposit silicon nitride trap layer 4-7nm, deposit silicon dioxide is as the initiation layer 20-30nm of barrier oxide layer then.
In the described step 5), argon ion implant angle and vertical direction are 60 °-40 °.
In the described step 5), the thickness of described barrier oxide layer is 4-6nm.
Wherein, some key structure parameters of soi structure fin channel dual-bar multi-function field effect transistor of the present invention are as the long L of thickness, grid of the silicon dioxide insulating layer of the wide W of fin channel and high H, SOI substrate
G, back of the body grid ONO stack architecture material, raceway groove and the source of each layer thickness, gate oxide thickness, back of the body grid and preceding the grid doping content and the distribution of leaking, can make adjustment according to the design needs.Preparation method of the present invention, adopt the technology of conventional MOSFET preparation, as oxidation, deposit, etching, corrosion and ion injection etc.,, on the SOI substrate, can autoregistration realize fin channel dual-bar multi-function field effect transistor by new technology integrated (Process Integration).This preparation method and existing conventional MOSFET technology are compatible fully, do not need expensive technologies such as extension, when realizing the multifunction device characteristic of optimizing, can reduce the prepared cost.
Fin channel dual-bar multi-function field effect transistor of the present invention has following three kinds of functions equally.(1) function of high performance MOSFET logical device constitutes device by the grid oxygen and the preceding grid of grid one side before source, leakage, fin channel, the fin channel, operating voltage 1.0V～1.2V, and back of the body grid are 0V.(2) function of flash memory, by the ONO stack architecture (comprising tunnel oxide, silicon nitride trap layer, barrier oxide layer) and the back of the body grid formation device of source, leakage, fin channel, fin channel back of the body grid one side, preceding grid are 0V; Source 0V leaks 3V, and back of the body grid 4V is with the channel hot electron injection programming; Leak 3V, back of the body grid-4V injects realization with the band-to-band-tunneling hot hole and wipes; The source adds small voltage, leaks 0V, reverse read.(3) function of capless DRAM constitutes device by source, leakage, fin channel, preceding grid grid oxygen and preceding grid, and back of the body grid add negative voltage; Before grid 1V, leak and to add high voltage 2V, hot electron is in the ionization that bumps of the drain terminal of raceway groove, the hole of generation is in the accumulation of the raceway groove back side, storage " 1 "; Preceding grid 1V, leakage adds back bias voltage, the hole is swept leakage, storage " 0 "; When reading, leak 0.2V.
Multi-functional MOSFET with respect to document 1 based on planar double-gated structure, the technique effect of the fin channel dual-bar multi-function field effect transistor that the present invention proposes is: (1) fin channel, the height H of fin type structure is equivalent to the width W of device, compares the area that can reduce the W direction with planar structure and takies; (2) each layer thickness of back of the body grid ONO stack architecture can be according to the definition of design needs; (tunnel oxide of 2nm～4nm) is to improve the retention performance of storage data to adopt suitable thickness; Adopt suitable thickness (silicon nitride trap layer of 4nm～7nm), suppress stored charge in the distribution again of silicon nitride layer, improve reliability; Adopt the barrier oxide layer of suitable thickness (4-6nm), suppress the back of the body tunnelling of electric charge, improve programming efficiency and retention performance; (3) gross thickness of back of the body grid ONO stack architecture is not subjected to process technology limit, can reach 10nm～17nm (and about 45nm of thickness of the ONO stack architecture in the document 1), and the back of the body grid voltage when making program/erase reduces, improves simultaneously program/erase speed; (4) back of the body grid and preceding grid autoregistration all are by the definition of grid version, and be very little for the covering of source and leakage, can improve the DC characteristic and the reliability of multifunction device; (5) preceding grid and back of the body grid are drawn from the fin channel both sides respectively, compare with planar double-gated structure, and drawing of back of the body grid is easy to realize; (6) preparation method of conventional relatively MOSFET does not need to increase reticle, does not need epitaxial growth technology, and technology simply is easy to realize, can reduces the technology cost.
Therefore, fin channel dual-bar multi-function field effect transistor proposed by the invention in high reliability and highdensity high-performance SOC application, has clear superiority and application prospects.
Description of drawings
Fig. 1 is for needing the generalized section of three kinds of integrated devices in the high-performance SOC application, wherein Fig. 1 (a) is the high performance MOSFET logical device based on the SOI substrate, wherein Fig. 1 (b) is flash memory (the Flash Memory based on body silicon substrate MOSFET structure, can be called for short flash memory), wherein Fig. 1 (c) is the DRAM (dynamic RAM) of 1T1C (field-effect transistor adds an electric capacity).
Among Fig. 1 (a)-(c), identical label is represented identical parts:
The silicon dioxide buried regions of the bottom silicon 102-SOI substrate of 101-SOI substrate
103-polysilicon gate 104-grid oxygen
105-raceway groove (SOI top layer silicon) 106-n+ source 107-n+ leaks
The raceway groove of 108-body silicon substrate 109-flash memory
110-barrier oxide layer 111-silicon nitride trap layer 112-tunnel oxide
The electric capacity of 113-raceway groove (body silicon substrate) 114-DRAM
Fig. 2 is the domain and the structural representation of the SOONO structure multifunctional field-effect transistor of document 1: wherein, Fig. 2 (a) is the domain schematic diagram of this device, and M1 is the active area version, and M2 is Stripe version (removing the SiGe sacrifice layer), M3 is the grid version, and M4 is the domain of deep trench isolation; Fig. 2 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device; Fig. 2 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device.
Fig. 2 (b) and (c) in, identical label is represented identical parts:
The silicon dioxide of the place that 201-body silicon substrate (p-doping) 202-STI isolates
203-back of the body grid (n+ silicon) 204-barrier oxide layer 205-silicon nitride trap layer 206-tunnel oxide
207-polysilicon gate 208-grid oxygen
209-raceway groove 210-n+ source 211-n+ leaks
Fig. 3 is the domain and the structural representation of fin channel dual-bar multi-function field effect transistor provided by the present invention: wherein, Fig. 3 (a) is the domain schematic diagram of this device, and M1 is the active area version, and M2 is the grid version; Fig. 3 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device, can see that raceway groove is the structure of fin type, one side of fin channel is that grid oxygen and preceding grid, opposite side are back of the body grid ONO stack architecture and back of the body grid, and entire device is positioned on the insulating barrier of SOI substrate simultaneously; Fig. 3 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device.
Fig. 3 (b) and (c) in, identical label is represented identical parts:
The silicon dioxide buried regions of the bottom silicon 302-SOI substrate of 301-SOI substrate
Gate oxide before the grid 305-before the 303-fin channel 304-
306-back of the body grid 307-tunnel oxide 308-silicon nitride trap layer
309-barrier oxide layer 310-silicon dioxide resilient coating 311-silicon nitride hardmask layer
312-n+ source 313-n+ leaks
Fig. 4 (a)-(j) be one embodiment of the invention based on the preparation method's of the fin channel dual-bar multi-function field effect transistor of SOI substrate the technological process and the schematic diagram of each step institute counter structure thereof.
Among Fig. 4 (a)-(j), identical label is represented identical parts:
The silicon dioxide buried regions of the bottom silicon 402-SOI substrate of 401-SOI substrate
The top silicon surface 404-fin channel of 403-SOI substrate
405-silicon dioxide resilient coating 406-silicon nitride hardmask layer
The height H of the width W 408-fin channel of 407-fin channel
409-tunnel oxide 410-silicon nitride trap layer
The initiation layer of 411-barrier oxide layer
The 412-barrier oxide layer
Gate oxide 414-grid material 415-n+ source 416-n+ leaks before the 413-
Grid 418-back of the body grid before the 417-
Embodiment
Describe fin channel dual-bar multi-function field effect transistor provided by the present invention and preparation method thereof in detail below in conjunction with accompanying drawing, but be not construed as limiting the invention.
Shown in Fig. 3 (a)-(c), be the fin channel dual-bar multi-function field effect transistor of present embodiment.This device is based on the SOI substrate.Be depicted as the domain of this device as Fig. 3 (a), M1 active area version, M2 is the grid version.As Fig. 3 (b) with (c) be respectively the vertical direction along raceway groove (A1A2 direction) of this device and along the cross-section structure of channel direction (B1B2 direction).From the cross-section structure along the vertical direction of raceway groove, this field-effect transistor is positioned on the silicon dioxide buried regions 302 of SOI substrate, and the cross section of raceway groove is rectangular fin type Fin, and its width W is that 50nm, height H are 80nm, forms fin channel 303; One side of fin channel is the grid oxygen 305 of 1.5nm and the preceding grid 304 of polysilicon, and opposite side is tunnel oxide 307, the silicon nitride trap layer 308 as 4nm, the barrier oxide layer 309 of 5nm and the back of the body grid 306 of polysilicon of 3nm, forms double-gate structure; The two ends of fin channel 303 connect common n+ source 312 and n+ leaks 313; Preceding grid 304 and 306 autoregistrations of back of the body grid, and very little to the covering of n+ source 312 and n+ leakage 313.
Fin channel dual-bar multi-function field effect transistor of the present invention has following three kinds of functions equally.(1) function of high performance MOSFET logical device constitutes device by the grid oxygen and the preceding grid of grid one side before source, leakage, fin channel, the fin channel, operating voltage 1.0V～1.2V, and back of the body grid are 0V.(2) function of flash memory, by the ONO stack architecture (comprising tunnel oxide, silicon nitride trap layer, barrier oxide layer) and the back of the body grid formation device of source, leakage, fin channel, fin channel back of the body grid one side, preceding grid are 0V; Source 0V leaks 3V, and back of the body grid 4V is with the channel hot electron injection programming; Leak 3V, back of the body grid-4V injects realization with the band-to-band-tunneling hot hole and wipes; The source adds small voltage, leaks 0V, reverse read.(3) function of capless DRAM constitutes device by source, leakage, fin channel, preceding grid grid oxygen and preceding grid, and back of the body grid add negative voltage; Before grid 1V, leak and to add high voltage 2V, hot electron is in the ionization that bumps of the drain terminal of raceway groove, the hole of generation is in the accumulation of the raceway groove back side, storage " 1 "; Preceding grid 1V, leakage adds back bias voltage, the hole is swept leakage, storage " 0 "; When reading, leak 0.2V.
Fin channel dual-bar multi-function field effect transistor proposed by the invention in high reliability and highdensity high-performance SOC application, has clear superiority and application prospects.
The present invention prepares the method for fin channel dual-bar multi-function field effect transistor, comprises the steps:
Step 1: on the SOI substrate, thermal oxidation silicon dioxide (SiO
2) 10-20nm, deposit silicon nitride (Si again
3N
4) 30-50nm;
Step 2: the photoetching of active area version, etching SiO
2And Si
3N
4, silicon forms fin channel, the height H of the top silicon surface thickness decision fin channel of selected SOI substrate, and H is 50-100nm;
Step 3: thermal oxidation tunnel oxide 2-4nm, deposit silicon nitride trap layer 4-7nm, deposit silicon dioxide is as the initiation layer 20-30nm of barrier oxide layer then;
Step 4: the argon ion inclination angle is injected, the initiation layer of the barrier oxide layer of grid one side before the bombardment, the feasible SiO that is bombarded
2Wet etching speed strengthens;
Step 5: wet etching silicon dioxide, the wet etching silicon nitride, wet etching silicon dioxide, the silicon face of grid one side exposes before making, the barrier oxide layer initiation layer of carrying on the back grid one side simultaneously can be thinned to the thickness 4-6nm that forms barrier oxide layer, forms back of the body grid ONO stack architecture;
Step 6: gate oxide 1-2nm before the thermal oxidation;
Step 7: the deposit polysilicon, the photoetching of grid version, arsenic injects, and forms n+ source and leakage, and simultaneously to polysilicon doping; The annealing activator impurity.
Step 8: the chemico-mechanical polishing cmp planarizationization forms self aligned independently preceding grid and back of the body grid.
Be illustrated in figure 4 as the preparation method of a kind of fin channel dual-bar multi-function field effect transistor proposed by the invention.Each device architecture shown in Fig. 4 (a)-(j) is corresponding with each step among this preparation method.
Below in conjunction with each accompanying drawing this preparation method is elaborated:
On the step 1:SOI substrate, thermal oxidation SiO
215nm, deposit Si again
3N
440nm is (along the A1A2 direction) shown in Fig. 4 (a).
The photoetching of step 2:M1 active area version, etching SiO
2, Si
3N
4And silicon, form fin-shaped channel, the height H of the top silicon surface thickness decision fin channel of selected SOI substrate, H can be 80nm, shown in Fig. 4 (b) (along the A1A2 direction).
Step 3: thermal oxidation tunnel oxide 3nm, deposit silicon nitride trap layer 5nm, deposit silicon dioxide is as the initiation layer 25nm of barrier oxide layer, shown in Fig. 4 (c) (along the A1A2 direction) then.
Step 4: the argon ion inclination angle is injected, the initiation layer of the barrier oxide layer of grid one side before the bombardment, the feasible SiO that is bombarded
2Wet etching speed strengthens, and implant angle is 45 °, injects energy 50keV, implantation dosage 5 * 10
14Cm
-2, shown in Fig. 4 (d) (along the A1A2 direction).
Step 5: wet etching silicon dioxide, the wet etching silicon nitride, wet etching silicon dioxide, the silicon face of grid one side exposes before making, the barrier oxide layer initiation layer of carrying on the back grid one side does not simultaneously inject through argon ion, and corrosion rate is slower, can be thinned to the thickness 5nm that forms barrier oxide layer, form back of the body grid ONO stack architecture, shown in Fig. 4 (e) (along the A1A2 direction).
Step 6: gate oxide 1.5nm before the thermal oxidation, shown in Fig. 4 (f) (along the A1A2 direction).
Step 7: the deposit polysilicon, the photoetching of grid version, arsenic injects, and forms n+ source and leakage, and simultaneously to polysilicon doping; The annealing activator impurity is shown in Fig. 4 (g) (along the A1A2 direction) and Fig. 4 (h) (along the B1B2 direction).
Step 8: chemico-mechanical polishing (CMP) planarization, grind off the polysilicon at fin channel top, the polysilicon of fin channel both sides is disconnected mutually, form self aligned independently preceding grid and back of the body grid, shown in Fig. 4 (i) (along the A1A2 direction) and Fig. 4 (j) (along the B1B2 direction).
Step 9: further carry out conventional subsequent technique, deposit hypoxemia layer, the etching fairlead, depositing metal, photoetching, etching form metal wire, alloy, passivation.
Obtain the fin channel dual-bar multi-function field effect transistor based on the SOI substrate that can be used to test, the high 80nm of wide 50nm of the cross-section structure of fin channel at last.
More than by specific embodiment fin channel dual-bar multi-function field effect transistor provided by the present invention and preparation method thereof has been described, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to device architecture of the present invention; Its preparation method also is not limited to disclosed content among the embodiment.
Claims (9)
1, a kind of fin channel dual-bar multi-function field effect transistor, it is characterized in that: this field-effect-transistor-based is in the SOI substrate, its channel region, source region and drain region all are positioned on the insulating barrier, along the raceway groove vertical direction, the cross section of raceway groove is rectangular fin type Fin, form fin channel, the two ends of fin channel connect the n+ source and n+ leaks, one side of fin channel is grid oxygen and preceding grid, opposite side is tunnel oxide, the silicon nitride trap layer as charge storage layer, barrier oxide layer and back of the body grid, forms double-gate structure; Preceding grid and the autoregistration of back of the body grid.
2, fin channel dual-bar multi-function field effect transistor as claimed in claim 1 is characterized in that, described fin channel, and the scope of the width W in its cross section is that the scope of 30nm～60nm, height H is 50nm～100nm, W is less than H.
3, fin channel dual-bar multi-function field effect transistor as claimed in claim 1 is characterized in that, the thickness of described grid oxygen is 1nm～2nm.
4, as claim 1 or 3 described fin channel dual-bar multi-function field effect transistors, it is characterized in that, the thickness of described tunnel oxide is that the thickness of 2nm～4nm, silicon nitride trap layer is that the thickness of 4nm～7nm, barrier oxide layer is 4nm～6nm, and the gross thickness of promptly carrying on the back grid ONO stack architecture is 10～17nm.
5, a kind of method for preparing fin channel dual-bar multi-function field effect transistor as claimed in claim 1 is characterized in that, may further comprise the steps:
1) on the SOI substrate, thermal oxidation silicon dioxide, deposit silicon nitride again;
2) active area version photoetching, etching silicon dioxide and silicon nitride, silicon forms fin channel;
3) thermal oxidation tunnel oxide, deposit silicon nitride trap layer, deposit silicon dioxide are as the initiation layer of barrier oxide layer;
4) the outer silicon dioxide of preceding grid one side of bombardment is injected at the argon ion inclination angle;
5) corrode silicon dioxide, corroding silicon nitride, corrode silicon dioxide, the silicon face of grid one side exposes before making, and will carry on the back the grid remaining silica simultaneously as barrier oxide layer, forms back of the body grid ONO stack architecture;
6) gate oxide before the thermal oxidation;
7) deposit or sputter grid material, the photoetching of grid version, impurity injects, and forms n+ source and leakage; The annealing activator impurity;
8) planarization forms self aligned independently preceding grid and back of the body grid.
6, preparation method as claimed in claim 5 is characterized in that, in the described step 1), selected SOI substrate top silicon surface thickness is 50-100nm, and its thickness has determined the height H of fin channel.
7, preparation method as claimed in claim 5 is characterized in that, in the described step 3), and thermal oxidation tunnel oxide 2-4nm, deposit silicon nitride trap layer 4-7nm, deposit silicon dioxide is as the initiation layer 20-30nm of barrier oxide layer then.
8, preparation method as claimed in claim 5 is characterized in that, in the described step 5), argon ion implant angle and vertical direction are 60 °-40 °.
9, preparation method as claimed in claim 5 is characterized in that, in the described step 5), the thickness of barrier oxide layer is 4-6nm.
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