CN1941418A - Memory cell and structure of semiconductor non-volatile memory having that memory cell - Google Patents
Memory cell and structure of semiconductor non-volatile memory having that memory cell Download PDFInfo
- Publication number
- CN1941418A CN1941418A CNA2006101540500A CN200610154050A CN1941418A CN 1941418 A CN1941418 A CN 1941418A CN A2006101540500 A CNA2006101540500 A CN A2006101540500A CN 200610154050 A CN200610154050 A CN 200610154050A CN 1941418 A CN1941418 A CN 1941418A
- Authority
- CN
- China
- Prior art keywords
- zone
- semiconductor substrate
- grid
- memory cell
- resistance variations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 238000003860 storage Methods 0.000 claims abstract description 40
- 230000002093 peripheral effect Effects 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims description 117
- 229910052785 arsenic Inorganic materials 0.000 claims description 57
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 57
- 238000002513 implantation Methods 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 32
- 230000008676 import Effects 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 23
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 20
- 229910052796 boron Inorganic materials 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 10
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 12
- 239000012528 membrane Substances 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 238000009826 distribution Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000004088 simulation Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 239000002800 charge carrier Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A nonvolatile semiconductor memory has a memory cell structure with a doped semiconductor substrate (1), a gate electrode (26), a channel area (28) disposed in the substrate (1) below the gate electrode (26), a pair of variable resistance areas (30 and 32) disposed on opposite sides of the channel area (28) in the substrate, charge storage bodies (40) formed above the variable resistance areas (30 and 32) and on the sides of the gate electrode, and highly doped source and drain areas (28) formed on opposite sides of the variable resistance areas (30 and 32) in the substrate. The variable resistance areas (30 and 32) are doped at a carrier concentration of 5x10<17>cm<-3 >or less to ensure an adequate current difference between the programmed and erased states of the memory cell. The doping of the variable resistance areas differs from the lightly doped drain doping in peripheral circuit areas.
Description
Technical field
The structure that the present invention relates to memory cell and have the semiconductor non-volatile memory of this memory cell.
Background technology
In recent years, in semiconductor non-volatile memory, proposed to have the memory cell of 2 charge storage portions in the both sides of grid.
In patent documentation 1 and patent documentation 2, the memory cell of general structure is as shown in Figure 13 disclosed for example.
This memory cell 220 works as memory by moving in such a way.
At first, the situation of going into information with 236 sidelights in the drain region is that example describes.At first establish A-stage in the charge storage portion 240 of drain region 236 sides, there not being the state of stored charge.From this state, by on drain region 236, applying positive voltage, on grid 226, apply positive voltage, and source region 234 is made as earthed voltage, on the 2nd resistance variations zone 232, produce hot electron, and hot electron is injected selectively the charge storage portion 240 of drain region 236 sides.Can in charge storage portion 240, carry out writing of information like this.
Secondly, the action of the sense information of drain region 236 sides is described.
By on source region 234, applying positive voltage, on grid 226, apply positive voltage, and drain region 236 is made as earthed voltage, read.At this moment, when going into to have under the situation of information at drain region 236 sidelights on, promptly the charge storage portion internal memory of working as in drain region 236 sides contains under the situation of electric charge, the resistance in the 2nd resistance variations zone 232 rises, become the state that is difficult to provide charge carrier, can not flow through enough electric currents to channel region 228.On the other hand, under the situation of the A-stage that does not have writing information in drain region 236 sides, promptly working as does not have under the situation of stored charge in the charge storage portion 240 of drain region 236 sides, and the resistance in the 2nd resistance variations zone 232 can not rise.Its result provides charge carrier to channel region 228, flows through enough electric currents.Like this, utilize the read current before and after writing poor, differentiating logical value is 0 or 1.
More than be in the drain region 236 sidelights on go into, the action during sense information, when will be in the source region when 234 sides are carried out same action, replace the voltage between source region and the drain region, just can carry out same action.
In patent documentation 2, with concrete impurity concentration the structure (for example, with reference to execution mode 10) of several suitable source/drain regions is disclosed.
Patent documentation 1: the spy opens 2005-64295
Patent documentation 2: the spy opens 2004-342927
As above-mentioned, the read current before and after the memory cell utilization of structure shown in Figure 13 writes is poor.Thereby, if can not make this difference between current enough big, be 0 or 1 just be difficult to differentiate logical value.
But,, can not make the read current difference before and after writing enough big according to the semiconductor non-volatile memory that patent documentation 2 is put down in writing.
Summary of the invention
So in order to address the above problem, representational memory cell of the present invention is characterised in that to possess: on Semiconductor substrate across film formed the 1st grid of the 1st gate insulation; The 1st channel region that on the zone, top layer of described Semiconductor substrate and the position relative, forms with described the 1st grid; Be formed on the resistance variations zone of the both sides of described the 1st channel region, the impurity concentration in described resistance variations zone is lower than described the 1st channel region, and described impurity concentration is smaller or equal to 5 * 10
17Cm
-3Be formed on both sides, conductivity type 1st high concentration impurity opposite in resistance variations zone with described channel region; And be formed on the described resistance variations zone, can carry out the charge stored storage part of electric charge.
The effect of invention
According to the present invention, the read current that can fully increase before and after writing is poor.
Description of drawings
Fig. 1 is the profile of structure of the semiconductor non-volatile memory of expression the 1st execution mode.
Fig. 2 is the profile of structure of the memory cell of expression the 1st execution mode.
Fig. 3 is the figure of equivalent electric circuit of the memory cell of expression the 1st execution mode.
Fig. 4 is the profile of structure of the peripheral transistor of expression the 1st execution mode.
Fig. 5 is the profile of manufacture method of the semiconductor non-volatile memory of expression the 1st execution mode.
Fig. 6 is the profile of manufacture method of the semiconductor non-volatile memory of expression the 1st execution mode.
Fig. 7 is the profile of manufacture method of the semiconductor non-volatile memory of expression the 1st execution mode.
Fig. 8 is curve chart memory cell, the wide W1 of side wall and the asynchronous write diagnostics of arsenic implantation dosage N of expression the 1st execution mode.
Fig. 9 is the curve chart of the relation of the arsenic implantation dosage N of memory cell of expression the 1st execution mode and current changing rate.
Figure 10 (a) be the expression the 1st execution mode memory cell, arsenic implantation dosage N=1 * 10
12Cm
-2The time the curve chart of impurities concentration distribution of directions X.
Figure 10 (b) be the expression the 1st execution mode memory cell, arsenic implantation dosage N=1 * 10
12Cm
-2The time the curve chart of impurities concentration distribution of Y direction.
Figure 11 (a) be the expression the 1st execution mode memory cell, arsenic implantation dosage N=5 * 10
12Cm
-2The time the curve chart of impurities concentration distribution of directions X.
Figure 11 (b) be the expression the 1st execution mode memory cell, arsenic implantation dosage N=5 * 10
12Cm
-2The time the curve chart of impurities concentration distribution of Y direction.
Figure 12 is the profile of structure of the memory cell of expression the 2nd execution mode.
Figure 13 is a profile of representing the structure of memory cell in the past.
Embodiment
Below, referring to figs. 1 through Figure 12 embodiments of the present invention are described.Moreover each figure only is roughly to represent the shape of each composed component, size and configuration relation can understand degree of the present invention.Thereby, the invention is not restricted to illustrative example.
(1) the 1st execution mode
The structure and the manufacture method that the memory cell of the 1st execution mode of the present invention are described and have the semiconductor non-volatile memory of this memory cell with Fig. 1 to Figure 11 (b).
(structure of semiconductor non-volatile memory)
The structure of the semiconductor non-volatile memory 100 of present embodiment at first, is described with Fig. 1.
In Fig. 1,, have the memory cell region 2 that forms a plurality of memory cell 20 that are used for stored information and form a plurality of neighboring areas 5 that are used to carry out the peripheral transistor 50 of logical operation by the Semiconductor substrate 1 that the silicon that contains p type impurity constitutes.Moreover, as Semiconductor substrate 1, can suitably adopt the Semiconductor substrate of other structures such as insulator-base silicon (SOI) structure, process for sapphire-based epitaxial silicon (SOS) structure.
On the zone arbitrarily of memory cell region 2 and neighboring area 5, on Semiconductor substrate 1, all be formed with a plurality of element separation zone 7 that obtains by STI (shallow-trench isolation) method.On the Semiconductor substrate 1 in element separation zone 7, be formed with shallow slot 8, in shallow slot 8, imbed silicon oxide film 9 (NSG: non-doped silicate glasses).Moreover element separation zone 7 also can be to form by other element separation technology such as LOCOS method, polysilicon isolation, gas barrier.
In memory cell region 2, on a plurality of active regions 10 that surrounded by element separation zone 7, on the face side zone of Semiconductor substrate, be formed with the P well area 12,15 that contains p type impurity as the subregion of Semiconductor substrate 1.
Similarly in neighboring area 5, on a plurality of active regions 10 (active region) that surrounded by element separation zone 7, on the face side zone of Semiconductor substrate, be formed with the P well area 15 that contains p type impurity as the subregion of Semiconductor substrate 1.
On the active region 10 of memory cell region 2, be formed with memory cell 20, on the active region 10 of neighboring area 5, be formed with peripheral transistor 50.
Moreover, in the present embodiment, though be to be that example describes on the memory cell region with the conductivity type of well area in the situation that all is the P type on the neighboring area, but also can all be made as the N type, can also be made as and make their different separately conductivity types.
(structure of memory cell)
Fig. 2 is formed in the enlarged drawing of memory cell 20 on the active region 10 of memory cell region 2, the N channel-type.
As above-mentioned, on the face side zone of P type semiconductor substrate 1, be formed with P trap 12 zones of containing p type impurity.
On Semiconductor substrate 1, be formed with grid 26 (the 1st grid) across gate insulating film 22 (the 1st gate insulating film).Grid 26 is made of the stack membrane of polysilicon 24 and tungsten silicide 25.Grid length and grid width all are 0.16 μ m.
On the zone, top layer of Semiconductor substrate 1 and the position relative, be formed with high concentration (P with grid 26
+Type) channel region 28 (the 1st channel region) that contains p type impurity.
In the both sides of channel region 28, be formed with low concentration (P
-Type) the resistance variations zone 30 and 32 of containing p type impurity. Resistance variations zone 30 and 32 is formed on the below of charge storage described later portion 40.In addition, the impurity concentration in resistance variations zone 30 and 32 is lower than the impurity concentration of channel region 28.Specifically, the impurity concentration in resistance variations zone 30 and 32 is smaller or equal to 5 * 10
17Cm
-3Moreover, about the detailed content of the scope of the conductivity type in resistance variations zone 30 and 32 and suitable impurity concentration, narration in the back.
Both sides in 2 resistance variations zones 30 and 32 are formed with high concentration (N
+Type) contain the source region 34 of N type impurity and drain region 36 (general name they the time, be called the 1st high concentration impurity).The impurity concentration of source region 34 and drain region 36 is 8 * 10
20Cm
-3
In the both sides of grid 26, on the zone 30 and 32, be formed with 2 charge storage portions 40 from the sidewall of grid 26 to resistance variations.Charge storage portion is that to begin from lower floor be silicon oxide film 38 (silicon dioxide: SiO successively
2) and silicon nitride film 39 (silicon nitride: stack membrane SiN).Be horizontally formed at the part on the Semiconductor substrate 1 among this charge storage portion 40, when making memory cell 20 action, play function as memory by stored charge.Moreover, in the present embodiment, owing in charge storage portion 40, be formed with the 1st side wall (side wall) 42 that constitutes by oxide-film as described later, so the SiO preferably of charge storage portion 40
22 tunics of/SiN.But, (for example using under the situation of side wall of polysilicon) under the situation of not using oxide-film as the 1st side wall 42, must on silicon nitride film 39, form silicon oxide film again, must be by SiO
2/ SiN/SiO
2The charge storage portion 40 that this 3 tunic constitutes.
Along the charge storage portion 40 of grid 26 sidewalls, be formed with the 1st side wall 42 that constitutes by NSG.The 1st side wall 42 when making memory cell 20, works as the mask that is used to form source region 34 and drain region 36.Moreover, with the wide W1 that is made as of the 1st side wall 42 of memory cell 20.
Fig. 3 is the equivalent electric circuit of memory cell 20.
Be to work as variable resistor in resistance variations zone 30 and 32, and connected 2 variable-resistance circuit in the both sides of grid.
(structure of peripheral transistor)
Fig. 4 is formed in the enlarged drawing of the peripheral transistor 50 of the N channel-type on the active region 10 of neighboring area 5.
On the face side zone of Semiconductor substrate 1, be formed with high concentration (P
+) contain the P well area 15 of p type impurity.
On Semiconductor substrate 1, be formed with grid 56 (the 2nd grid) across gate insulating film 52 (the 2nd gate insulating film).Grid 56 is made of the stack membrane of polysilicon 54 and tungsten silicide 55.Grid length is 0.20 μ m, and grid width is 0.16 μ m.The grid length of peripheral transistor 50 is based on following reason than the grid length length of memory cell 20.As described later, the impurity concentration in the LDD of neighboring area 5 zone 60 and 62 is higher than the impurity concentration in the resistance variations zone 30 and 32 of memory cell region 2.Therefore the actual effect grid length owing to peripheral transistor 50 shortens, so if grid length is not lengthened to about 0.20 μ m, punch through will occur.
On the zone, top layer of Semiconductor substrate 1 and the position relative, be formed with high concentration (P with grid 56
+Type) channel region 58 (the 2nd channel region) that contains p type impurity.
In the both sides of channel region 58, be formed with low concentration (N
-Type) the LDD zone 60 and 62 of containing N type impurity.The impurity concentration in LDD zone 60 and 62 is higher than the impurity concentration of channel region 58, and is lower than source region 64 described later and drain region 66.Specifically, preferably be made as more than or equal to 1 * 10
18Cm
-3Smaller or equal to 1 * 10
19Cm
-3
Both sides in 2 LDD zones 60 and 62 are formed with high concentration (N
+Type) contain the source region 64 of N type impurity and drain region 66 (general name they the time, be called the 2nd high concentration impurity).The impurity concentration of source region 64 and drain region 66 is 1 * 10
20Cm
-3About.
In the both sides of grid 56, on the zone 60 and 62, be formed with from lower floor successively by silicon oxide film 68 (silicon dioxide: SiO from the sidewall of grid 56 to LDD
2) and silicon nitride film 69 (silicon nitride: the SiN) stack membrane 70 of Gou Chenging.Though this stack membrane 70 is identical structures with the stack membrane of the charge storage portion 40 that constitutes memory cell region 2, be not to move in the mode of the function that plays stored charge.
Along the stack membrane 70 of grid 56 sidewalls, be formed with the 2nd side wall 72 that constitutes by silicon dioxide.The 2nd side wall 72 when making peripheral transistor 50, works as the mask that is used to form source region 64 and drain region 66.
(manufacture method of semiconductor non-volatile memory)
Secondly, the manufacture method of the semiconductor non-volatile memory 100 of present embodiment is described with Fig. 5.
Moreover, following situation is arranged, promptly for the identical composed component of content of illustrated mistake in the explanation of the structure of semiconductor non-volatile memory 100, be marked with same label, and omit its explanation.
At first, shown in Fig. 5 (a), on Semiconductor substrate 1, form element separation zone 7 by the STI method with memory cell region 2 and neighboring area 5.That is, on Semiconductor substrate 1, form silicon nitride film by CVD (chemical vapor deposition) method.Remove these known photo-mask processs by photoresist coating, graph exposure, development of photoresist, figure etching and photoresist then silicon nitride film is carried out composition.Then, as mask, etching semiconductor substrate 1 forms shallow slot 8 with the figure of silicon nitride film.Secondly, form silicon oxide film 9 (NSG) by the CVD method, and pass through CMP (cmp) method Semiconductor substrate 1 flattening surface in the mode of filling shallow slot 8 at least.Then, remove silicon nitride film.Moreover, though form element separation zone 7 by the STI method, also can suitably adopt known elements isolation technologies such as LOCOS method, polysilicon isolation, gas barrier at this.
Secondly, shown in Fig. 5 (b), on the active region 10 as Semiconductor substrate 1 surf zone in neighboring area 5, that surrounded by element separation zone 7, form P well area 15.Specifically, on the zone beyond the neighboring area 5, form Etching mask 90, and import boron (B) as p type impurity with ion implantation.Ion implantation energy is 100keV, and implantation dosage (ion injection rate) is 2 * 10
13Cm
-2After ion injects, remove Etching mask.
Secondly, shown in Fig. 5 (c), on the active region 10 in memory cell region 2, form P well area 12.Specifically, on the zone beyond the memory cell region 2, form Etching mask 91, and divide the boron (B) that imports as p type impurity for 2 times with ion implantation.The 1st secondary ion injects, and ion implantation energy is 100keV, and implantation dosage is 3.5 * 10
13Cm
-2, the 2nd secondary ion injects, and ion implantation energy is 30keV, and implantation dosage is 1 * 10
13Cm
-2After ion injects, remove Etching mask 91.
Secondly, shown in Fig. 6 (d), on the Semiconductor substrate 1 of memory cell 2 and neighboring area 5, form grid 26 and 56.That is, at first, in 850 ℃ oxygen atmosphere,, form grid oxidation film with oxidation on Semiconductor substrate 1 surface.Secondly, on grid oxidation film, will constitute the polysilicon and the tungsten silicide film forming of grid in turn, and grid and grid oxidation film be carried out composition by photo-mask process.Thus, on the Semiconductor substrate of memory cell region, form the 1st grid 26 that the stack membrane by polysilicon 24 and tungsten silicide 25 constitutes across the 1st gate insulating film.Simultaneously, on the Semiconductor substrate 1 of neighboring area 5, form the 2nd grid 56 that the stack membrane by polysilicon 54 and tungsten silicide 55 constitutes across the 2nd gate insulating film.In addition at this moment, Semiconductor substrate 1 surface is exposed in the zone beyond the grid 56 of active region 10.
Secondly, shown in Fig. 6 (e), on the active region 10 of memory cell region 2, form resistance variations zone 30 and 32.That is, on the zone beyond the memory cell region 2, form Etching mask 92, Etching mask 92 and grid 26 as mask, are imported arsenic (As) as N type impurity by ion implantation then on the zone, top layer of Semiconductor substrate 1.Ion implantation energy is 30keV, and implantation dosage is 2 * 10
12Cm
-2Like this, on the zone, top layer of the Semiconductor substrate 1 beyond the grid of active region 10 26 times, form resistance variations zone 30 and 32.After ion injects, remove Etching mask 92.Moreover, about the suitable scope of the implantation dosage of arsenic, narration in the back.In addition, the impurity of importing also can not be arsenic but antimony (Sb).Because antimony is heavier than arsenic quality, therefore can further only reduce the impurity concentration of the surf zone of Semiconductor substrate 1.So, can make more precipitous CONCENTRATION DISTRIBUTION, thereby the read current that can further increase before and after writing is poor.
Secondly, shown in Fig. 6 (f), on the active region 10 of neighboring area 5, form LDD zone 60 and 62.That is, on the zone beyond the neighboring area 5, form Etching mask 93, and import N type foreign matter of phosphor (P) by ion implantation.Ion implantation energy is 20keV, and implantation dosage is 2 * 10
13Cm
-2After ion injects, remove Etching mask.
Secondly, shown in Fig. 7 (g), on memory cell region 2 and neighboring area 5, form charge storage layer 80.At first, on the Semiconductor substrate 1 that comprises memory cell region 2 and neighboring area 5, form silicon oxide film (the 1st oxide-film).Promptly, be exposed to by the Semiconductor substrate 1 that will form grid 26 and 56 in 1000 ℃ the oxygen atmosphere, with Semiconductor substrate 1 surface beyond under the grid 26 and 56 of 7 surfaces, element separation zone, active region 10 and the top and lateral oxidation of grid 26 and 56, form the silicon oxide film (the 1st oxide-film) of thickness 100 .Secondly, form the charge storage nitride film.That is, on silicon oxide film, form silicon nitride film (charge storage nitride film) by the CVD method.Thickness is 100 .By the stack membrane that these silicon oxide films and charge storage nitride film constitute, be charge storage layer 80.Secondly, on memory cell region 2 and neighboring area 5, form side wall oxide-film 82 (NSG) with the CVD method.Thickness is 400 .
Secondly, shown in Fig. 7 (h), on memory cell region 2 and neighboring area 5, form side wall 42 and 72 and charge storage portion 40 and 70.At first, the side wall oxide-film 82 with memory cell region 2 and neighboring area 5 carries out anisotropic etching.Thus, form the 1st side wall 42 in the outside of the charge storage layer 80 of the 1st grid 26 sides.In addition simultaneously, form the 2nd side wall 72 in the outside of the charge storage layer 80 of the 2nd grid 56 sides.Secondly, with the 1st side wall 42 and the 2nd side wall 72 as mask and etching charge accumulation layer 80.Thus, on memory cell region 2, remove charge storage layer 80 on the Semiconductor substrate 1 beyond charge storage layer 80 on the 1st grid 26 and the 1st grid 26 times and the 1st side wall 42 times by etching.In addition simultaneously, on neighboring area 5, remove charge storage layer 80 on the Semiconductor substrate 1 beyond charge storage layer 80, the 2 grids 56 times on the 2nd grid 56 and the 2nd side wall 72 times by etching.Like this, on memory cell region 2, form charge storage portion 40.Moreover, though on neighboring area 5, also form with charge storage portion 40 stack membrane 70 with spline structure, as above-mentioned, this stack membrane 70 is not to move in the mode of the function that plays stored charge.
Secondly, shown in Fig. 7 (i), on the active region 10 of memory cell region 2, form source region 34 and drain region 36 (the 1st high concentration impurity).That is, on the zone beyond the memory cell region 2, form Etching mask 94, and with Etching mask the 94, the 1st grid 26 and the 1st side wall 42 as mask, import arsenic (As) with ion implantation then as N type impurity.Ion implantation energy is 30keV, and implantation dosage is 1.0 * 10
15Cm-2.Thus, on the zone, top layer of the 1st grid 26 times and 42 times Semiconductor substrate 1 in addition of the 1st side wall, form source region 34 and drain region 36 (the 1st high concentration impurity).After ion injects, remove Etching mask 94.
Secondly, shown in Fig. 7 (j), on the active region 10 of neighboring area 5, form source region 64 and drain region 66 (the 2nd high concentration impurity).That is, on the zone beyond the neighboring area 5, form Etching mask 95, and with Etching mask the 95, the 2nd grid 56 and the 2nd side wall 72 as mask, import arsenic (As) with ion implantation then as N type impurity.Ion implantation energy is 30keV, and implantation dosage is 1.0 * 10
15Cm
-2Thus, on the zone, top layer of the 2nd grid 56 times and 72 times Semiconductor substrate 1 in addition of the 2nd side wall, form source region 64 and drain region 66 (the 2nd high concentration impurity).After ion injects, remove Etching mask.
Like this, just can shop drawings 1 and the semiconductor non-volatile memory 100 and the memory cell 20 of present embodiment shown in Figure 2.
(about the experiment and the simulation in resistance variations zone)
The structure and the manufacture method in the resistance variations of the memory cell 20 of present embodiment zone 30 and 32 are based on the result's of present inventor's research with keen determination.
Be that the present inventor is conceived to the structure in resistance variations zone 30 and 32 and the relation of manufacture method and the read current poor (write diagnostics) that writes front and back, carried out experiment and the simulation shown in following each figure.
Fig. 8 is that the wide W1 of side wall that is illustrated in the memory cell 20 of present embodiment is made as under the situation of 50nm, 75nm and 100nm, will be as the import volume (implantation dosage: N) be made as 0 (zero), 1 * 10 respectively of the arsenic (As) of the impurity that is used to form resistance variations zone 30 and 32
12Cm
-2And 2 * 10
12Cm
-2The time the curve chart of write diagnostics.That is, be 3 conditions about the wide W1 of side wall, be 3 conditions about arsenic implantation dosage N, total is 9 conditions.In addition, Writing condition is grid voltage 8V, drain voltage 5.5V, and the condition of reading is grid voltage 2.5V, source voltage 2V.That is, in the drain region 36 sidelights on go into, sense information.In each curve chart, transverse axis is write time (μ second), and the longitudinal axis is the read current (μ ampere) after the writing of the time shown in the transverse axis of having carried out.For example, from the wide W1 of side wall is 50nm, arsenic implantation dosage N is the curve chart of the condition of 0 (zero), write time is 0 (zero) as can be seen, read current (initial stage electric current) before promptly writing is about 40 μ amperes, the read current that has carried out after the writing of 20 μ seconds is 10 μ amperes, and the read current that has carried out after the writing of 100 μ seconds is about 4 μ amperes.
According to this experiment, if at first be conceived to the wide W1 of side wall, following tendency is arranged as can be known, that is, when W1 is 50nm when narrow like this, the resistance value in resistance variations zone 32 is less, therefore the initial stage electric current is bigger, opposite when W1 be 100nm so greatly the time, the resistance value in resistance variations zone 32 is bigger, so the initial stage electric current diminishes.
Secondly, if be conceived to arsenic implantation dosage N, following tendency is arranged as can be known, that is, when N is 0 so more after a little while, the initial stage electric current is less, on the contrary when N be 2 * 10
12Cm
-2So more for a long time, the in the initial stage of that electric current is bigger.
When the initial stage electric current was big, if can dwindle cell current after writing, it was poor just can to increase the read current that writes front and back, means that write diagnostics is good.On the other hand, when the initial stage electric current hour, even if suppose to dwindle cell current after writing, the read current that can not increase before and after writing is poor, so means that write diagnostics is relatively poor.
From this point, so big if the wide W1 of side wall becomes 100nm when the arsenic implantation dosage is zero, then the in the initial stage of that electric current reduces sharp, therefore considers the process deviation of the wide W1 of side wall, does not reach practicability.On the other hand, when N be 1 * 10
12Cm
-2And 2 * 10
12Cm
-2The time, so big if W1 is 100nm, though then the initial stage electric current reduces, can not reduce so sharp, if therefore the process deviation of W1 can be controlled at smaller or equal to about 10nm, just can obtain enough difference between currents, can reach practicability.
Fig. 9 is result's the curve chart of equipment simulating of situation of representing also to comprise the implantation dosage N of further increase arsenic.This is in that wide W1 is made as respectively under the situation of 30nm, 100nm and 150nm with side wall, will place 5 * 10 on the charge storage layer as being written in
-18Cm
-2Negative electric charge, promptly the rate of change of the read current during electronics is made curve chart.For example, be under the situation of 100nm at the wide W1 of side wall, can read arsenic implantation dosage N is 2 * 10
12Cm
-2The time current changing rate approximately be 0.3.The ratio with respect to the read current before writing that this means read current after writing is about 0.3, and mean read current because of write reduce so many.
According to this simulation, have following tendency as can be known, that is, (for example N is 1 * 10 more after a little while as arsenic implantation dosage N
12Cm
-2Situation under), the current changing rate that causes is bigger by writing, and becomes for a long time as N on the contrary, diminishes by writing the current changing rate that causes.For example work as N and become 5 * 10
12Cm
-2Therefore so for a long time, current changing rate begins to diminish, if make N more than this, current changing rate just diminishes, and does not reach practicability.In case N increase current changing rate just diminishes like this, be because when the concentration of the N type impurity of resistance variations regional 30 and 32 thickens, even if electric charge iunjected charge storage part 40 with this conductivity type, exhausting also and can being suppressed of the resistance variations zone 30 and 32 that is caused by it is difficult to realize resistance variations.
Figure 10 (a) and Figure 10 (b) represent that obtaining the arsenic implantation dosage N that will be used to form resistance variations zone 30 and 32 by two-dimentional processing simulation device is made as 1 * 10
12Cm
-2The time, the result's of the impurities concentration distribution of memory cell 20 curve chart.Figure 11 (a) and Figure 11 (b) represent that obtaining the arsenic implantation dosage N that will be used to form resistance variations zone 30 and 32 by two-dimentional processing simulation device is made as 5 * 10 in addition
12Cm
-2The time, the result's of the impurities concentration distribution of memory cell 20 curve chart.In each curve chart, for boron (B), arsenic (As) and overall charge carrier, the impurity concentration in the place shown on X-axis is represented with logarithm respectively on Y-axis.So-called overall charge carrier, the meaning are the concentration of the charge carrier integral body in this place.For example, in Figure 10 (a), the concentration of the boron in the place of X=0.5 μ m is about 4 * 10
17Cm-3, the concentration of arsenic is about 1 * 10
17Cm
-3Because the boron as p type impurity likens to the arsenic of N type impurity is many, therefore mean it is the P type as a whole, and its overall carrier concentration is about 3 * 10
17Cm
-3On the other hand, in Figure 11 (a), the concentration of the boron in the place of X=0.5 μ m is about 4 * 10
17Cm
-3, the concentration of arsenic is about 5 * 10
17Cm
-3Because the arsenic as N type impurity likens to the boron of p type impurity is many, therefore mean it is the N type as a whole, and its overall carrier concentration is about 2 * 10
17Cm
-3
In addition, Figure 10 (a) and Figure 11 (a) are the Impurity Distribution during along zone, the top layer of directions X (Fig. 2's is right-hand) cutting semiconductor substrate 1.On the zone of X≤0.49 μ m, be formed with grid 26.In any width of cloth of Figure 10 (a) and Figure 11 (a),, therefore know on the zone of X 〉=0.46 μ m to be formed with resistance variations zone 32 owing to the place of overall carrier concentration from X=0.46 μ m begins to reduce.On the other hand, in any width of cloth of Figure 10 (a) and Figure 11 (a),, therefore know on the zone of X 〉=0.53 μ m to be formed with drain region 36 because the concentration of arsenic increases in the zone of 0.52 μ m≤X≤0.53 μ m sharp.Thereby, know that the zone of 0.46 μ m≤X≤0.52 μ m is resistance variations zone 32 in any width of cloth of Figure 10 (a) and Figure 11 (a).
Figure 10 (b) and Figure 11 (b) are the places along Y direction (below of Fig. 2) cutting Figure 10 (a) and Figure 11 (a) X=0.5 μ m separately, i.e. Impurity Distribution the during the three unities in the resistance variations zone 32.In any width of cloth of Figure 10 (b) and Figure 11 (b), the zone of 0 μ m≤Y≤0.01 μ m is the zone that forms silicon oxide film 38.Thereby, know on the zone of Y 〉=0.01 μ m, to form resistance variations zone 32.On the other hand, in Figure 10 (b), know that overall carrier concentration begins to reduce to substrate surface direction (left) from the place of Y=0.05, and on the zone of Y≤0.05, be formed with resistance variations zone 32.In addition, in Figure 11 (b),, therefore know on the zone of Y≤0.07, to be formed with resistance variations zone 32 because overall carrier concentration reduces to substrate surface direction (left) from the place of Y=0.07.Thereby, know that in Figure 10 (b), the zone of 0.01 μ m≤Y≤0.05 μ m is resistance variations zone 32, in Figure 11 (b), the zone of 0.01 μ m≤Y≤0.07 μ m is resistance variations zone 32.
According to these curves, know when the arsenic implantation dosage N that injects resistance variations zone 32 more after a little while, i.e. N=1 * 10
12Cm
-2The time (with reference to Figure 10 (a) and Figure 10 (b)), though the concentration in resistance variations zone 32 reduces because of the injection of arsenic, but because the concentration of boron is still than the concentration height of arsenic, therefore in resistance variations zone 32 on the whole, conductivity type does not become the N type and still is the P type.And, the impurity concentration in resistance variations zone 32, the maximum that reads from Figure 10 (a) is 5 * 10
17Cm
-3(place of X=0.46), the maximum that reads from Figure 10 (b) also is 5 * 10
17Cm
-3(place of Y=0.05).Thereby, know when N=1 * 10
12During cm-2, in resistance variations zone 32 on the whole, conductivity type is the P type, and impurity concentration is smaller or equal to 5 * 10
17Cm
-3
On the other hand, when the arsenic implantation dosage N that injects resistance variations zone 32 is quite a lot of, i.e. N=5 * 10
12Cm
-2When (with reference to Figure 11 (a) and Figure 11 (b)), resistance variations zone 32 comprises p type island region territory and this two side of N type zone.That is, the part in resistance variations zone 32 becomes the N type.Specifically, in Figure 11 (a), among the zone as the 0.46 μ m≤X≤0.52 μ m in resistance variations zone 32, in the zone of 0.46 μ m≤X≤0.49 μ m, because the concentration of boron is higher than the concentration of arsenic, so conductivity type is the P type.But, in the zone of 0.49 μ m≤X≤0.52 μ m, be higher than the concentration of boron because the concentration of arsenic becomes, so conductivity type is the N type.In addition similarly in Figure 11 (b), among the zone as the 0.01 μ m≤Y≤0.07 μ m in resistance variations zone 32, in the zone of 0.01 μ m≤Y≤0.03 μ m, because the concentration of arsenic is higher than the concentration of boron, so conductivity type is the N type.But in the zone of 0.03 μ m≤Y≤0.07 μ m, because the concentration of boron is higher than the concentration of arsenic, so conductivity type is the P type.And this impurity concentration from the maximum that Figure 11 (a) reads, is all to be 5 * 10 under the situation of P type or under the situation of N type
17Cm
-3In addition, the maximum of the impurity concentration that reads from Figure 11 (b) is 5 * 10 under the situation of P type
17Cm
-3, under the situation of N type, be 1.5 * 10
17Cm
-3Thereby, know when N=5 * 10
12Cm
-2The time the conductivity type in resistance variations zone 32 comprise the zone of P type and this two side of zone of N type (, the part in resistance variations zone 32 is N types), its impurity concentration is all smaller or equal to 5 * 10 in the zone of P type or in the zone of N type
17Cm
-3
From experiment and the Simulation result of above Fig. 8 to Figure 11, we can say that the suitable scope of the conductivity type in arsenic implantation dosage N and resistance variations zone 32 and impurity concentration is as follows.
At first inquire into the scope of suitable arsenic implantation dosage N.As according to the explanation of the experimental result of Fig. 8 like that, if arsenic implantation dosage N is made as zero, then do not reach practicability.On the other hand, when arsenic implantation dosage N is increased to 5 * 10
12Cm
-2The time, owing to reduce,, just do not reach practicability if therefore N is increased to more than this as current changing rate with Fig. 9 explanation.Thereby arsenic implantation dosage N is if more than or equal to 1 * 10
12Cm
-2Smaller or equal to 5 * 10
12Cm
-2Scope, can reach practicability, very suitable.
Secondly, according to the curve shown in Figure 10 (a) and Figure 10 (b), the arsenic concentration in the place of the X=0.52 that the difference of the arsenic concentration in resistance variations zone 32 and boron concentration is minimum is 1.5 * 10
17Cm
-3, boron concentration is 3.5 * 10
17Cm
-3From this concentration to recently, arsenic concentration is identical with boron concentration, is when making the arsenic implantation dosage be approximately 2.3 (=3.5 ÷ 1.5) times.Because Figure 10 (a) and Figure 10 (b) are arsenic implantation dosage N=1 * 10
12Cm
-2Situation, therefore can infer when making arsenic implantation dosage N greater than 2.3 * 10
12Cm
-2The time, the conductivity type in resistance variations zone 32 may comprise the N type from having only the P type to be changed to.Thereby, can infer and work as arsenic implantation dosage N smaller or equal to 2.3 * 10
12Cm
-2The time, the conductivity type in resistance variations zone 32 still is the P type.If consider to add the analog result of Fig. 9 at this, a side current changing rate less owing to arsenic implantation dosage N is bigger, therefore when the conductivity type in resistance variations zone 32 is the P type, become with the conductivity type in resistance variations zone 32 and to compare when comprising the N type, can obtain bigger current changing rate.Thereby, if arsenic implantation dosage N is more than or equal to 1 * 10
12Cm
-2Smaller or equal to 2.3 * 10
12Cm
-2Scope, can make the whole P of becoming types in resistance variations zone 32, and can obtain bigger current changing rate, therefore more suitable.
Secondly, inquire into conductivity type and impurity concentration with the corresponding resistance variations of the scope zone 32 of above-mentioned suitable implantation dosage N.At first, when arsenic implantation dosage N be 1 * 10
12Cm
-2The time, according to Figure 10 (a), Figure 10 (b), the whole of resistance variations zone 32 are P types, its impurity concentration is smaller or equal to 5 * 10
17Cm
-3On the other hand, when arsenic implantation dosage N be 5 * 10
12Cm
-2The time, according to Figure 11 (a), Figure 11 (b), resistance variations zone 32 comprises p type island region territory and this two side of N type zone, its impurity concentration all is smaller or equal to 5 * 10 in the zone arbitrarily of P type and N type
17Cm
-3Thereby, be more than or equal to 1 * 10 at arsenic implantation dosage N
12Cm
-2Smaller or equal to 5 * 10
12Cm
-2Scope in, be that its impurity concentration is all smaller or equal to 5 * 10 under any one the situation of P type, N type at the conductivity type in resistance variations zone 32
17Cm
-3
As previously discussed, be under any one the situation of P type, N type at the conductivity type in resistance variations zone 32, when its impurity concentration smaller or equal to 5 * 10
17Cm
-3The time, can reach practicability, very suitable.
In addition, as above-mentioned, when resistance variations zone 32 whole were the P type, the situation that becomes the N type with the part in resistance variations zone 32 is compared, and can obtain bigger current changing rate, and was very suitable.Thereby if the whole of resistance variations zone 32 are P types, and its impurity concentration is smaller or equal to 5 * 10
17Cm
-3, can obtain bigger current changing rate, thus more suitable.
(comparison in resistance variations zone and LDD zone)
The resistance variations zone 30 and 32 of the memory cell 20 of memory cell region 2, obtain by above structure and manufacture method, if but with and its feature of relatively arrangement in the LDD zone 60 and 62 of the peripheral transistor 50 of neighboring area 5, we can say that following saying is very suitable.
At first, the impurity concentration in the resistance variations of memory cell region 2 zone 30 and 32 is preferably lower than the impurity concentration in the LDD zone 60 and 62 of neighboring area 5.That is because as above-mentioned, the resistance variations zone 30 of memory cell region 2 preferably be made as P type or N type smaller or equal to 5 * 10
17Cm
-3, with respect to this, the impurity concentration in the LDD of neighboring area 5 zone 60 and 62 preferably is made as more than or equal to 1 * 10
18Cm
-3Smaller or equal to 1 * 10
19Cm
-3
In addition, the degree of depth in the resistance variations of memory cell region 2 zone 30 and 32 cans be compared to the depth as shallow in the LDD zone 60 and 62 of neighboring area 5 most.Promptly, though resistance variations zone 30 and 32 and the degree of depth in LDD zone 60 and 62 by kind, ion implantation energy and the implantation dosage decision of the ion (dopant) that imports, but it is as above-mentioned, the resistance variations zone 30 and 32 of memory cell region 2, preferably by being 30keV with the ion implantation energy with arsenic, implantation dosage N is more than or equal to 1 * 10
12Cm
-2Smaller or equal to 5 * 10
12Cm
-2The mode injected of condition ion form.On the other hand, the LDD of neighboring area 5 zone 60 and 62, by being 20keV with the ion implantation energy with phosphorus, implantation dosage is 2.0 * 10
13Cm
-2The mode injected of condition ion form.Forming resistance variations zone 30 and 32 and LDD zone 60 and at 62 o'clock with this condition, the degree of depth in the resistance variations zone 30 and 32 of memory cell region 2 is than the depth as shallow in the LDD zone 60 and 62 of neighboring area 5.Thereby, we can say that the degree of depth in the resistance variations zone 30 and 32 of memory cell region 2 cans be compared to the depth as shallow in the LDD zone 60 and 62 of neighboring area 5 most.
In addition, be used to form the resistance variations zone 30 and 32 of memory cell region 2 and the impurity that is imported into, preferably the element of the impurity weight that is imported into than the LDD zone 60 and 62 that is used to form neighboring area 5 of service quality.Promptly because as above-mentioned, the resistance variations of memory cell region 2 zone 30 and 32 preferably imports arsenic or antimony by ion implantation, with respect to this, the LDD of neighboring area 5 zone 60 and 62 preferably imports phosphorus by ion implantation.
In addition, the resistance variations of memory cell region 2 zone 30 and 32, the little implantation dosage of implantation dosage in LDD zone 60 and 62 that the most handy ratio is used to form the peripheral transistor 50 of neighboring area 5 forms.That is,, preferably be made as more than or equal to 1 * 10 owing to, form the resistance variations zone 30 of memory cell region 2 and 32 o'clock implantation dosage N as above-mentioned
12Cm
-2Smaller or equal to 5 * 10
12Cm
-2, with respect to this, forming the LDD zone 60 of neighboring area 5 and 62 o'clock implantation dosage is 2 * 10
13Cm
-2
(2) the 2nd execution modes
The structure and the manufacture method that the memory cell of the 2nd execution mode of the present invention are described and have the semiconductor non-volatile memory of this memory cell with Figure 12.The memory cell 120 of the 2nd execution mode is characterized in that, under the resistance variations zone 30 and 32 of the memory cell 20 of the 1st execution mode, possesses the bag (pocket) layers 134 that contains the high slightly p type impurity of concentration ratio channel region 28.Thereby the semiconductor non-volatile memory cell of the 2nd execution mode is the semiconductor non-volatile memory with this memory cell 120.Moreover, for the composed component components identical that in the structure of the memory cell of the 1st execution mode and semiconductor non-volatile memory and manufacture method, illustrates, be marked with same label, and omit its explanation.
(structure of semiconductor non-volatile memory)
The structure of the semiconductor non-volatile memory of the 2nd execution mode, except exist in the configuration aspects of memory cell 120 and the 1st execution mode difference structure with the semiconductor non-volatile memory 100 of the 1st execution mode shown in Figure 1 identical, so omit its explanation at this.
Figure 13 is the enlarged drawing of the memory cell 120 of the 2nd execution mode.
Under resistance variations zone 30 and 32, possesses the bag layer 134 that contains the high slightly p type impurity of concentration ratio channel region 28.In addition the memory cell 20 with the 1st execution mode is identical, therefore omits its explanation at this.
Like this, owing under resistance variations zone 30 and 32, possess bag layer 134, therefore, accelerate thereby make to write writing near the fashionable electric field that can strengthen the drain region 36 (when writing source region 34 sides, being source region 34).
(manufacture method)
Secondly, the manufacture method of the semiconductor non-volatile memory of the 2nd execution mode is described
The manufacture method of the semiconductor non-volatile memory of the 2nd execution mode, it is characterized in that, in the manufacturing process of the semiconductor non-volatile memory 100 of the 1st execution mode, the operation (Fig. 6 (e)) in formation resistance variations zone 30 and 32 is appended an operation that forms bag layer 134 afterwards on the active region 10 of memory cell region 2.In addition the manufacture method with the semiconductor non-volatile memory 100 of the 1st execution mode is identical.
That is, on the active region 10 of memory cell region 2, import after the N type impurity, do not remove Etching mask 92 by ion implantation, and with grid 26 and Etching mask 92 as mask, import boron (B) by ion implantation then as p type impurity.Ion implantation energy is 40keV, and implantation dosage is 1 * 10
13Cm
-2Like this, when the energy with 40keV imports boron, because the range straggling from Semiconductor substrate 1 surface to Semiconductor substrate 1 inside near 0.12 μ m, therefore can form bag layer 134 for substantially resistance variations zone 30 and 32 with impacting.Then, remove Etching mask 92, carry out on the active region 10 of neighboring area 5, forming the operation in LDD zone 60 and 62.After, with the manufacture method identical (Fig. 6 (f) is to Fig. 7 (j)) of the semiconductor non-volatile memory 100 of the 1st execution mode.
Moreover, can also the same mode that imports with ion implantation as the indium (In) of p type impurity be formed bag layer 134 by replacing boron.Because indium has about 10 times quality of boron, therefore can form the higher P type bag layer (134) of impurity concentration.Therefore, can make more precipitous CONCENTRATION DISTRIBUTION, so the read current that can further increase before and after writing is poor.
Claims (18)
1. memory cell is characterized in that possessing:
On Semiconductor substrate across film formed the 1st grid of the 1st gate insulation;
The 1st channel region that on the zone, top layer of described Semiconductor substrate and the position relative, forms with described the 1st grid;
Be formed on the resistance variations zone of the both sides of described the 1st channel region, the impurity concentration in described resistance variations zone is lower than described the 1st channel region, and described impurity concentration is smaller or equal to 5 * 10
17Cm
-3
Be formed on both sides, conductivity type 1st high concentration impurity opposite in described resistance variations zone with described channel region; And
Form on the described resistance variations zone, can carry out the charge stored storage part of electric charge.
2. memory cell as claimed in claim 1 is characterized in that, described resistance variations zone is identical with described the 1st channel region conductivity type.
3. memory cell as claimed in claim 1 is characterized in that, described resistance variations zone forms in the mode that imports impurity arsenic.
4. memory cell as claimed in claim 1 is characterized in that, described resistance variations zone forms in the mode that imports impurity antimony.
5. memory cell as claimed in claim 1 is characterized in that, under described resistance variations zone, it is identical with described the 1st channel region to be formed with conductivity type, and impurity concentration is higher than the bag layer of described channel region.
6. memory cell as claimed in claim 5 is characterized in that, described bag layer forms in the mode that imports boron impurities.
7. memory cell as claimed in claim 5 is characterized in that, described bag layer forms in the mode that imports the impurity indium.
8. a semiconductor non-volatile memory has memory cell region that possesses memory cell and the neighboring area that possesses peripheral transistor, it is characterized in that:
Described memory cell has:
On Semiconductor substrate across film formed the 1st grid of the 1st gate insulation;
The 1st channel region that on the zone, top layer of described Semiconductor substrate and the position relative, forms with described the 1st grid;
Be formed on the resistance variations zone of the both sides of described the 1st channel region, the impurity concentration in described resistance variations zone is lower than described the 1st channel region;
Be formed on both sides, conductivity type 1st high concentration impurity opposite in described resistance variations zone with described the 1st channel region; And
Be formed on the described resistance variations zone, can carry out the charge stored storage part of electric charge;
Described peripheral transistor possesses:
On described Semiconductor substrate across film formed the 2nd grid of the 2nd gate insulation;
On the zone, top layer of described Semiconductor substrate and the position relative, form the 2nd channel region with described the 2nd grid;
Be formed on the LDD zone of the both sides of described the 2nd channel region; And
Be formed on both sides, conductivity type 2nd high concentration impurity opposite in described LDD zone with described the 2nd channel region; Wherein
The impurity concentration in described resistance variations zone is lower than the impurity concentration in described LDD zone.
9. nonvolatile memory as claimed in claim 8 is characterized in that, the impurity concentration in described resistance variations zone is smaller or equal to 5 * 10
17Cm
-3
10. a semiconductor non-volatile memory has memory cell region that possesses memory cell and the neighboring area that possesses peripheral transistor, it is characterized in that:
Described memory cell has:
On Semiconductor substrate across film formed the 1st grid of the 1st gate insulation;
The 1st channel region that on the zone, top layer of described Semiconductor substrate and the position relative, forms with described the 1st grid;
Be formed on the resistance variations zone of the both sides of described the 1st channel region, the impurity concentration in described resistance variations zone is lower than described the 1st channel region;
Be formed on both sides, conductivity type 1st high concentration impurity opposite in described resistance variations zone with described the 1st channel region; And
Be formed on the described resistance variations zone, can carry out the charge stored storage part of electric charge;
Described peripheral transistor possesses:
On described Semiconductor substrate across film formed the 2nd grid of the 2nd gate insulation;
On the zone, top layer of described Semiconductor substrate and the position relative, form the 2nd channel region with described the 2nd grid;
Be formed on the LDD zone of the both sides of described the 2nd channel region; And
Be formed on both sides, conductivity type 2nd high concentration impurity opposite in described LDD zone with described the 2nd channel region; Wherein
The degree of depth in described resistance variations zone is than the depth as shallow in described LDD zone.
11. a semiconductor non-volatile memory has memory cell region that possesses memory cell and the neighboring area that possesses peripheral transistor, it is characterized in that:
Described memory cell has:
On Semiconductor substrate across film formed the 1st grid of the 1st gate insulation;
The 1st channel region that on the zone, top layer of described Semiconductor substrate and the position relative, forms with described the 1st grid;
Be formed on the resistance variations zone of the both sides of described the 1st channel region, the impurity concentration in described resistance variations zone is lower than described the 1st channel region;
Be formed on both sides, conductivity type 1st high concentration impurity opposite in described resistance variations zone with described the 1st channel region; And
Be formed on the described resistance variations zone, can carry out the charge stored storage part of electric charge;
Described peripheral transistor possesses:
On described Semiconductor substrate across film formed the 2nd grid of the 2nd gate insulation;
On the zone, top layer of described Semiconductor substrate and the position relative, form the 2nd channel region with described the 2nd grid;
Be formed on the LDD zone of the both sides of described the 2nd channel region; And
Be formed on both sides, conductivity type 2nd high concentration impurity opposite in described LDD zone, wherein with described the 2nd channel region
The impurity that imports in order to form described resistance variations zone uses the heavy element of impurity that imports than in order to form described LDD zone.
12. a semiconductor non-volatile memory has memory cell region that possesses memory cell and the neighboring area that possesses peripheral transistor, it is characterized in that:
Described memory cell has:
On Semiconductor substrate across film formed the 1st grid of the 1st gate insulation;
The 1st channel region that on the zone, top layer of described Semiconductor substrate and the position relative, forms with described the 1st grid;
Be formed on the resistance variations zone of the both sides of described the 1st channel region, the impurity concentration in described resistance variations zone is lower than described the 1st channel region;
Be formed on both sides, conductivity type 1st high concentration impurity opposite in described resistance variations zone with described the 1st channel region; And
Be formed on the described resistance variations zone, can carry out the charge stored storage part of electric charge;
Described peripheral transistor possesses:
On described Semiconductor substrate across film formed the 2nd grid of the 2nd gate insulation;
On the zone, top layer of described Semiconductor substrate and the position relative, form the 2nd channel region with described the 2nd grid;
Be formed on the LDD zone of the both sides of described the 2nd channel region; And
Be formed on both sides, conductivity type 2nd high concentration impurity opposite in described LDD zone with described the 2nd channel region; Wherein
Described resistance variations zone is used than being used to form the implantation dosage that lacks in described LDD zone to form.
13. the manufacture method of a memory cell is characterized in that, possesses:
On Semiconductor substrate, form the operation of the 1st grid across the 1st gate insulating film;
With described the 1st grid as mask, with more than or equal to 1 * 10
12Cm
-2Smaller or equal to 5 * 10
12Cm
-2Implantation dosage the 1st impurity that conductivity type is opposite with described Semiconductor substrate import the zone, top layer of Semiconductor substrate, form the operation in resistance variations zone on the zone, top layer of the Semiconductor substrate beyond under described the 1st grid;
Form the operation of side wall and charge storage portion in described the 1st gate side; And
With described the 1st grid and described side wall as mask, import the zone, top layer of Semiconductor substrate by the 2nd impurity that conductivity type is opposite with described Semiconductor substrate, under described the 1st grid and the operation that forms the 1st high concentration impurity on the zone, top layer of the Semiconductor substrate beyond under the described side wall.
14. the manufacture method of a memory cell is characterized in that, possesses:
On Semiconductor substrate, form the operation of the 1st grid across the 1st gate insulating film;
With described the 1st grid as mask, by with more than or equal to 1 * 10
12Cm
-2Smaller or equal to 2.3 * 10
12Cm
-2Implantation dosage the 1st impurity that conductivity type is opposite with described Semiconductor substrate import the zone, top layer of Semiconductor substrate, form the operation in resistance variations zone on the zone, top layer of the Semiconductor substrate beyond under described the 1st grid;
Form the operation of side wall and charge storage portion in described the 1st gate side;
With described the 1st grid and described side wall as mask, import the zone, top layer of Semiconductor substrate then by the 2nd impurity that conductivity type is opposite with described Semiconductor substrate, in the operation of formation the 1st high concentration impurity under described the 1st grid and on the zone, top layer of the Semiconductor substrate beyond under the described side wall.
15. the manufacture method as claim 13 or 14 described memory cell is characterized in that, described the 1st impurity is arsenic.
16. the manufacture method as claim 13 or 14 described memory cell is characterized in that, described the 1st impurity is antimony.
17. the manufacture method of a semiconductor non-volatile memory is characterized in that, possesses:
Preparation has the operation of the Semiconductor substrate of memory cell region and neighboring area;
On the described Semiconductor substrate of described memory cell region, form the 1st grid across the 1st gate insulating film, on the described Semiconductor substrate of described neighboring area, form the operation of the 2nd grid across the 2nd gate insulating film simultaneously;
Form the 1st Etching mask on the zone beyond the described memory cell region, and will described the 1st Etching mask and described the 1st grid as mask, pass through then with more than or equal to 1 * 10
12Cm
-2Smaller or equal to 5 * 10
12Cm
-2Implantation dosage the 1st impurity that conductivity type is opposite with described Semiconductor substrate import the zone, top layer of described Semiconductor substrate, form the operation in resistance variations zone on the zone, top layer of the described Semiconductor substrate beyond under described the 1st grid of described memory cell region;
On the zone beyond the described neighboring area, form the 2nd Etching mask, and with described the 2nd Etching mask and described the 2nd grid as mask, import the zone, top layer of described Semiconductor substrate by the 2nd impurity that conductivity type is opposite with described Semiconductor substrate, form the operation in LDD zone on the zone, top layer of the described Semiconductor substrate beyond under described the 2nd grid of described neighboring area;
On the zone beyond the described memory cell region, form the 3rd Etching mask, and with described the 3rd Etching mask, described the 1st grid and described the 1st side wall as mask, import the zone, top layer of Semiconductor substrate by the 3rd impurity that conductivity type is opposite with described Semiconductor substrate, under described the 1st grid and the operation that forms the 1st high concentration impurity on the zone, top layer of the described Semiconductor substrate beyond under described the 1st side wall;
On the zone beyond the described neighboring area, form the 4th Etching mask, and with described the 4th Etching mask, described the 2nd grid and the 2nd side wall as mask, import the zone, top layer of described Semiconductor substrate then by the 4th impurity that conductivity type is opposite with described Semiconductor substrate, form the operation of the 2nd high concentration impurity on the zone, top layer of the described Semiconductor substrate beyond under described the 2nd grid and under the 2nd side wall.
18. the manufacture method of semiconductor non-volatile memory as claimed in claim 17 is characterized in that, described the 1st impurity is the element heavier than described the 2nd impurity.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005287777A JP2007103424A (en) | 2005-09-30 | 2005-09-30 | Memory cell and structure of semiconductor non-volatile memory having the same |
| JP2005287777 | 2005-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1941418A true CN1941418A (en) | 2007-04-04 |
Family
ID=37901072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101540500A Pending CN1941418A (en) | 2005-09-30 | 2006-09-20 | Memory cell and structure of semiconductor non-volatile memory having that memory cell |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7514738B2 (en) |
| JP (1) | JP2007103424A (en) |
| KR (1) | KR101422277B1 (en) |
| CN (1) | CN1941418A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7622349B2 (en) * | 2005-12-14 | 2009-11-24 | Freescale Semiconductor, Inc. | Floating gate non-volatile memory and method thereof |
| JP5142494B2 (en) * | 2006-08-03 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP2009049097A (en) * | 2007-08-16 | 2009-03-05 | Oki Electric Ind Co Ltd | Semiconductor nonvolatile memory cell and manufacturing method thereof, and semiconductor nonvolatile memory having the semiconductor nonvolatile memory cell and manufacturing method thereof |
| US20090179256A1 (en) * | 2008-01-14 | 2009-07-16 | Sung-Bin Lin | Memory having separated charge trap spacers and method of forming the same |
| US20090189212A1 (en) * | 2008-01-30 | 2009-07-30 | Spansion Llc | Electronic device having a doped region with a group 13 atom |
| JP5469893B2 (en) * | 2009-03-26 | 2014-04-16 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| US9000525B2 (en) * | 2010-05-19 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for alignment marks |
| US8835297B2 (en) * | 2013-01-25 | 2014-09-16 | Macronix International Co., Ltd. | Fabricating method of non-volatile memory structure |
| JP6069054B2 (en) * | 2013-03-19 | 2017-01-25 | 株式会社フローディア | Nonvolatile semiconductor memory device |
| CN106328504B (en) * | 2015-06-30 | 2019-01-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108630740B (en) * | 2017-03-16 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714413A (en) * | 1995-12-11 | 1998-02-03 | Intel Corporation | Method of making a transistor having a deposited dual-layer spacer structure |
| JP3973819B2 (en) * | 1999-03-08 | 2007-09-12 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
| JP4923321B2 (en) * | 2000-09-12 | 2012-04-25 | ソニー株式会社 | Method of operating nonvolatile semiconductor memory device |
| US6670240B2 (en) * | 2001-08-13 | 2003-12-30 | Halo Lsi, Inc. | Twin NAND device structure, array operations and fabrication method |
| CN101388396B (en) * | 2001-11-21 | 2012-07-04 | 夏普株式会社 | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
| JP2004104009A (en) * | 2002-09-12 | 2004-04-02 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
| US6887758B2 (en) * | 2002-10-09 | 2005-05-03 | Freescale Semiconductor, Inc. | Non-volatile memory device and method for forming |
| JP2004186452A (en) * | 2002-12-04 | 2004-07-02 | Renesas Technology Corp | Nonvolatile semiconductor memory device and its manufacturing method |
| JP2004342767A (en) * | 2003-05-14 | 2004-12-02 | Sharp Corp | Semiconductor memory, semiconductor device, and portable electronic equipment |
| JP2004342927A (en) * | 2003-05-16 | 2004-12-02 | Sharp Corp | Semiconductor memory device and portable electronic equipment |
| JP2005064295A (en) | 2003-08-14 | 2005-03-10 | Oki Electric Ind Co Ltd | Semiconductor nonvolatile memory, method of recording information thereto, and method of reding information therefrom |
-
2005
- 2005-09-30 JP JP2005287777A patent/JP2007103424A/en active Pending
-
2006
- 2006-09-20 US US11/523,661 patent/US7514738B2/en not_active Expired - Fee Related
- 2006-09-20 KR KR1020060091349A patent/KR101422277B1/en not_active IP Right Cessation
- 2006-09-20 CN CNA2006101540500A patent/CN1941418A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007103424A (en) | 2007-04-19 |
| KR20070037324A (en) | 2007-04-04 |
| US20070075354A1 (en) | 2007-04-05 |
| KR101422277B1 (en) | 2014-07-22 |
| US7514738B2 (en) | 2009-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1941418A (en) | Memory cell and structure of semiconductor non-volatile memory having that memory cell | |
| CN1317772C (en) | Semiconductor device and method for fabricating the same | |
| CN1310329C (en) | Semiconductor integrated circuit device and its manufacturing method | |
| CN1222021C (en) | MDSFEET device system and method | |
| CN1244157C (en) | Nonvolatile semiconductor memory device | |
| CN1298042C (en) | Semiconductor with shallow slot isolation without depression and its producing method | |
| CN1282253C (en) | Semiconductor device with small bag and its mfg. | |
| CN1734786A (en) | Transistor and method of making same | |
| CN1257554C (en) | Metal oxide semiconductor transistor and its mfg. method | |
| CN1716572A (en) | Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device | |
| CN1240131C (en) | Semiconductor device and manufacture thereof | |
| CN1841749A (en) | Semiconductor device with increased channel length and method for fabricating the same | |
| CN1976033A (en) | Semiconductor device and semiconductor device manufacturing method | |
| CN1855545A (en) | Mos transistor, coms integrated circuit device including same, and related methods of manufacture | |
| CN1501461A (en) | Semiconductor device and manufacturing method thereof | |
| CN1505158A (en) | Integrated memory circuit and method of forming an integrated memory circuit | |
| CN1839479A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN1679169A (en) | Semiconductor device and method for fabricating the same | |
| CN1574298A (en) | Manufacturing method of a semiconductor integrated circuit device | |
| CN101047193A (en) | Semiconductor storage device and method of fabrication thereof | |
| CN101079434A (en) | 3D dual fin channel dual-bar multi-function field effect transistor and its making method | |
| CN1976041A (en) | Non-volatile semiconductor memory device and method for manufacturing the same | |
| CN1220266C (en) | Non-volatile semiconductor memory and its producing process | |
| CN1540742A (en) | Semiconductor device and its mfg. method | |
| CN1469478A (en) | Semiconductor integrated circuit and producing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20070404 |