CN107968124A - A kind of semiconductor device structure and preparation method thereof - Google Patents
A kind of semiconductor device structure and preparation method thereof Download PDFInfo
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- CN107968124A CN107968124A CN201610908290.9A CN201610908290A CN107968124A CN 107968124 A CN107968124 A CN 107968124A CN 201610908290 A CN201610908290 A CN 201610908290A CN 107968124 A CN107968124 A CN 107968124A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 46
- 238000005468 ion implantation Methods 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 9
- 239000010409 thin film Substances 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract 4
- 239000007924 injection Substances 0.000 abstract 4
- 239000010408 film Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 229910014299 N-Si Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Abstract
The present invention relates to thin film transistor (TFT) manufacturing field, more particularly to a kind of semiconductor device structure and preparation method thereof, and after being prepared in grid, lightly doped district is formed in substrate using vertical ion injection technology；Continue to prepare barrier layer, with forming side wall on the side wall of grid；Using above-mentioned grid and side wall as mask, vertical ion injection technology is carried out again, and to form the heavily doped region as source-drain electrode in above-mentioned lightly doped district, and lightly doped district is located at region the blocking due to side wall below side wall, its ion concentration still maintains constant, using the lightly doped drain as device（LDD）Area；Due to using vertical ion injection technology, and based on the heavily doped region re-formed on the basis of lightly doped district as source-drain area, the implantation dosage for each region intermediate ion to be formed can be accurately controlled, the depth of injection ion can also be improved at the same time, and can neatly adjust the size of LDD region by adjusting the thickness of side wall.
Description
Technical Field
The invention relates to the technical field of thin film transistor manufacturing, in particular to a semiconductor device structure and a preparation method thereof.
Background
With the continuous development of the thin film transistor manufacturing technology, the integration level is higher and higher, which leads to the continuous reduction of the length of the conductive channel, and the shorter conductive channel causes the increase of the leakage current of the source and drain and the generation of the hot carrier effect, which greatly reduces the performance of the thin film transistor.
Currently, in the industry, to avoid the above problem, an LDD (lightly doped drain) process is generally used to improve the performance of the device, that is, a lightly doped region is formed under the gate oxide layer inside the gate electrode by doping a lower dose relative to the source/drain electrode, so as to form a doping concentration gradient between the source/drain electrode and the channel, so as to form a higher series resistance at the source/drain electrode, thereby achieving the purpose of suppressing the leakage current and the hot carrier effect.
However, the dose of ion implantation in the conventional LDD process is difficult to control, and the depth of ion implantation is limited, so that leakage current and hot carrier effect cannot be effectively suppressed.
Disclosure of Invention
In view of the above technical problems, the present invention provides a semiconductor device structure with LDD regions and a method for fabricating the same, which can precisely control the ion implantation dose, adjust the size of the LDD regions, and increase the ion implantation depth.
The main technical scheme for solving the technical problems is as follows:
a semiconductor device structure, comprising:
a semiconductor substrate provided with a heavily doped region and a Lightly Doped Drain (LDD) region in contact with the heavily doped region;
a gate disposed over the semiconductor substrate; and
the side wall is arranged on the semiconductor substrate and covers the side wall of the grid;
the region of the side wall arranged on the semiconductor substrate corresponds to a lightly doped drain region in the semiconductor substrate, and the heavily doped region is positioned on one side of the lightly doped drain region, which is far away from the grid electrode.
Preferably, in the semiconductor device structure, the semiconductor substrate includes a substrate, and a silicon nitride layer, a silicon oxide layer and an N-type substrate sequentially covering the substrate from bottom to top, and the LDD region and the heavily doped region are both disposed in the N-type substrate; and
the LDD region is a P-type lightly doped region, and the heavily doped region is a P-type heavily doped region.
Preferably, in the semiconductor device structure, the semiconductor substrate includes a substrate, and a silicon nitride layer, a silicon oxide layer and a P-type substrate sequentially covering the substrate from bottom to top, and the LDD region and the heavily doped region are both disposed in the P-type substrate; and
the LDD region is an N-type lightly doped region, and the heavily doped region is an N-type heavily doped region.
Preferably, in the above semiconductor device structure, the semiconductor substrate further includes:
and the second silicon dioxide layer covers the N-type substrate or the P-type substrate, and the grid is arranged on the second silicon dioxide layer.
Preferably, in the semiconductor device structure, a material of the gate electrode includes molybdenum.
Preferably, the semiconductor device structure described above further includes:
the barrier layer covers the upper surface and the side wall of the grid electrode and the exposed upper surface of the semiconductor substrate, and the barrier layer covering the side wall of the grid electrode forms the side wall; wherein,
the height of the barrier layer is greater than the thickness of the barrier layer.
Preferably, the semiconductor device structure described above further includes:
and the second gate layer is covered on the barrier layer positioned on the upper surface and the side wall of the gate, and the material of the second gate layer comprises molybdenum.
Preferably, in the above semiconductor device structure, a silicon nitride film is further disposed between the second gate layer and the blocking layer.
Based on the semiconductor device structure, the invention also provides a preparation method of the semiconductor device structure, which is characterized by comprising the following steps:
providing a semiconductor substrate with a prepared grid;
forming a lightly doped region in the semiconductor substrate by using the grid as a mask and adopting a first vertical ion implantation process;
preparing a side wall to cover the side wall of the grid; and
forming a heavily doped region in part of the lightly doped region by using the side wall and the grid as masks and adopting a second vertical ion implantation process in the semiconductor substrate;
wherein, in the second vertical ion implantation process, the lightly doped region which is not secondarily doped forms an LDD region.
Preferably, in the above preparation method, the sidewall is prepared by using silicon oxide or silicon nitride.
Preferably, in the above manufacturing method, the ion concentration implanted by the second vertical ion implantation process is greater than the ion concentration implanted by the first vertical ion implantation process.
Preferably, in the above preparation method, the semiconductor substrate includes a substrate, and a silicon nitride layer, a silicon oxide layer and an N-type substrate which are sequentially disposed on the substrate from bottom to top, and the LDD region and the heavily doped region are both disposed in the N-type substrate;
the LDD region is a P-type lightly doped region, and the heavily doped region is a P-type heavily doped region.
Preferably, in the above preparation method, the semiconductor substrate includes a substrate, and a silicon nitride layer, a silicon oxide layer and a P-type substrate which are sequentially disposed on the substrate from bottom to top, and the LDD region and the heavily doped region are both disposed in the P-type substrate;
the LDD region is an N-type lightly doped region, and the heavily doped region is an N-type heavily doped region.
Preferably, in the above manufacturing method, the semiconductor substrate further includes:
and the second silicon dioxide layer covers the N-type substrate or the P-type substrate, and the grid is arranged on the second silicon dioxide layer.
Preferably, in the above preparation method, the width of the LDD region is consistent with the thickness of the sidewall; and is
And adjusting the width of the LDD region by adjusting the thickness of the side wall.
Preferably, in the above preparation method, the step of preparing the sidewall spacer to cover the sidewall of the gate includes:
preparing a barrier layer to cover the upper surface and the side wall of the grid electrode and the exposed upper surface of the semiconductor substrate, wherein the barrier layer covering the side wall of the grid electrode forms the side wall, and the height of the side wall is larger than the thickness of the side wall.
Preferably, in the above preparation method, before performing the second vertical ion implantation process, the preparation method further includes:
and vertically and directionally etching the barrier layer partially covering the exposed upper surface of the semiconductor substrate to improve the ion implantation depth of the heavily doped region.
Preferably, in the above preparation method, after the step of preparing to form the heavily doped region and the LDD region, the method further includes:
and sputtering a second gate layer on the gate to increase the capacitance formed between the second gate layer and the gate.
The technical scheme has the following advantages or beneficial effects:
after the grid electrode is prepared, a vertical ion implantation process is adopted to form a lightly doped region in the substrate; continuously preparing an oxide film layer to form a side wall on the side wall of the grid; taking the grid and the side wall as masks, and performing a vertical ion implantation process again to form a heavily doped region serving as a source and a drain in the lightly doped region, wherein the ion concentration of the region of the lightly doped region below the side wall is still unchanged due to the shielding of the side wall and the grid so as to serve as an LDD region of the device; because the vertical ion implantation process is adopted, and the heavily doped region serving as the source drain region is formed on the basis of the lightly doped region, the implantation dosage of ions in each formed region can be accurately controlled, the depth of implanted ions can be improved, and the size of the LDD region can be flexibly adjusted by adjusting the thickness of the side wall.
Drawings
Embodiments of the present invention will be described more fully with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a flow chart of a method of fabricating a semiconductor device structure of the present invention;
fig. 2 to 4 are structural diagrams of steps in the manufacturing process of the semiconductor device structure of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. Of course, the invention is capable of other embodiments in addition to those detailed.
The invention provides a semiconductor device structure with an LDD region and a preparation method thereof, aiming at accurately controlling the dosage of ion implantation, adjusting the size of the LDD region by adjusting the thickness of a side wall and providing more adjustment parameters for the process; meanwhile, the depth of ion implantation is improved by combining a method of directionally etching part of the barrier layer by a vertical substrate; after the ion implantation is completed, the second gate layer can be formed continuously or the second gate layer can be sputtered after the silicon nitride film is deposited continuously, so that the capacitance of the capacitor formed between the two gate layers can be adjusted.
The structure of the semiconductor device and the method for manufacturing the same according to the present invention will be described in detail with reference to the following embodiments and the accompanying drawings.
Referring to fig. 1, the method for manufacturing a semiconductor device structure of the present invention includes the steps of:
in a first step, a semiconductor substrate 1 prepared with a gate 2 is provided, and the specific structure thereof is as shown in fig. 2, including: a substrate 10 and a silicon nitride layer (SiN) sequentially covering the substrate 10X) 11, silicon oxide layer (SiO)X) 12, an N-type substrate (N-Si) 13 and a second silicon oxide layer (SiO)X) 14 and a gate 2 is disposed over the second silicon dioxide layer 14. It should be noted that the present embodiment is explained by taking the N-type substrate (N-Si) 13 as an example, and in practical application, the substrate can be replaced by a P-type substrate (P-Si) according to the requirement of the manufactured thin film transistor. In this embodiment, ions are implanted into the N-type substrate 13 to form a P-doped region, and in other embodiments, ions are implanted into the P-type substrate to form an N-doped region.
As a preferred embodiment, the material of the gate electrode 2 may include molybdenum (Mo), which has advantages of high melting point, low expansion coefficient, and low secondary electron emission rate.
Second, using the gate 2 as a mask, a first vertical ion implantation process is performed to form a lightly doped region 3 in the substrate 13 of the semiconductor substrate 1 (since the substrate 13 of this embodiment is an N-type substrate, the implanted ions are P-type ions, i.e., the formed lightly doped region 3 is a P-type lightly doped region (P-)).
As a preferred embodiment, in the second step, since a vertical ion implantation process is adopted, that is, the angle of ion implantation is perpendicular to the substrate 10, it can be ensured that ions are not implanted in the substrate 13 below the gate 2, that is, the lightly doped P-region 3 is only formed on the surface of the remaining substrate 13 except the substrate 13 which vertically corresponds to the gate 2, so that the subsequent ion implantation is continued to form a source and drain in the lightly doped P-region 3 formed on the substrate 13.
Third, referring to fig. 3, a blocking layer 5 is prepared to cover the upper surface and the sidewalls of the gate 2 and the exposed upper surface of the semiconductor substrate 1 (i.e., the upper surface of the second silicon oxide layer 14 not covered by the gate 2), and the blocking layer 5 forms sidewalls 50 on the sidewalls of the gate 2. In this step, the barrier layer 5 is deposited to a thickness on the upper surface of the gate electrode 2 corresponding to the thickness on the exposed upper surface of the semiconductor substrate 1.
Continuing with the fourth step, referring to fig. 3, using the sidewall 50 and the gate 2 as masks, and using a second vertical ion implantation process (similar to the first vertical ion implantation process in the second step, controlling the angle of ion implantation to be perpendicular to the substrate 10 can ensure that ions are not implanted into the gate 2 and the substrate 13 below the sidewall 50, that is, controlling the second vertical ion implantation process to only implant ions into the remaining lightly doped P-regions 3 except the lightly doped P-region 3 vertically corresponding to the gate 2 and the sidewall 50), so as to form a heavily doped region (P +) 4 in the lightly doped region 3.
As a preferred embodiment, after forming the heavily doped region (P +) 4, the lightly doped P-region 3 only has a region 30 vertically corresponding to the sidewall 50, where the region 30 is a LDD (lightly doped drain) region to be prepared in the present invention, that is, the LDD region 30 is located in the substrate 13 adjacent to the gate 2, and the heavily doped region 4 is located on the other side of the LDD region 30 opposite to the gate 2 and contacts the LDD region 30. Preferably, the width of the LDD region 30 is the same as the thickness of the sidewall 50, and the width of the LDD region 30 can be flexibly adjusted by adjusting the thickness of the sidewall 50, so as to realize accurate control of the ion implantation dose; and the size of the LDD region 30 can be adjusted by adjusting the thickness of the side wall 50, so that more adjustment parameters can be provided for the preparation process of the thin film transistor, and the preparation of the thin film transistor with different requirements can be flexibly adapted.
In the present embodiment, due to the blocking of the gate 2 and the sidewall 50, the heavily doped region (P +) 4 can be precisely formed in the lightly doped P-region 3 outside the LDD region 30 vertically corresponding to the sidewall 50. It should be noted that, since the blocking layer 5 has the function of inhibiting the ion penetration, and a better mask blocking function is ensured to be formed below the LDD region 30 and the gate 2 in the second vertical ion implantation process, the thickness of the blocking layer 5 covering the exposed upper surface of the second silicon oxide layer 14 should be smaller than the thickness of the blocking layer 5 covering the upper surface and the sidewall of the gate 2; alternatively, before the second vertical ion implantation process is performed, the ion implantation depth of the heavily doped region 4 to be formed is increased by vertically and directionally etching the barrier layer 5 partially covering the exposed upper surface of the second silicon oxide layer 14 (i.e., the barrier layer 5 above the heavily doped region 4 to be formed is partially etched perpendicular to the substrate 10).
As a preferred embodiment, the material of the barrier layer 5 may be silicon oxide (SiO)X) Or silicon nitride (SiN)X）。
Preferably, the heavily doped region 4 can be used as a source and a drain of the thin film transistor, and due to the existence of the lightly doped LDD region 30, a doping concentration gradient can be formed between the source and the drain and a channel to form a higher series resistance at the source and the drain, thereby achieving the purpose of suppressing the leakage current and the hot carrier effect.
After the ion implantation to form the heavily doped region 4 and the LDD region 30, the following steps may be further included:
fifthly, referring to fig. 4, a second gate layer 7 is formed on the gate 2 by sputtering, so as to adjust the capacitance formed between the second gate layer 7 and the gate 2. Preferably, the material of the second gate layer 7 may include molybdenum.
Further, a layer of silicon nitride (SiN) may be deposited on the barrier layer 5 before the second gate layer 7 is formed by sputteringX) A film 6, and a second gate layer 7 is formed on the silicon nitride film 6 by sputtering at a position corresponding to the gate 2The capacitance of the capacitor is formed between the two layers of grid electrodes.
In summary, in the semiconductor device structure with LDD regions and the method for fabricating the same according to the present invention, after the gate is fabricated, the lightly doped region is formed in the substrate by using the vertical ion implantation process; continuously preparing a barrier film layer to form a side wall on the side wall of the grid; taking the grid and the side wall as masks, and performing a vertical ion implantation process again to form a heavily doped region serving as a source and a drain in the lightly doped region, wherein the ion concentration of the region of the lightly doped region below the side wall is still unchanged due to the shielding of the side wall and the grid so as to serve as an LDD region of the device; because a vertical ion implantation process is adopted, and a heavily doped region serving as a source drain region is formed on the basis of a lightly doped region, the implantation dosage of ions in each formed region can be accurately controlled; meanwhile, the depth of implanted ions can be improved by a method of directionally etching part of the barrier layer by the vertical substrate, and the size of the LDD region can be flexibly adjusted by adjusting the thickness of the side wall.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (18)
1. A semiconductor device structure, comprising:
the semiconductor substrate is provided with a heavily doped region and a lightly doped drain region which is in contact with the heavily doped region;
a gate disposed over the semiconductor substrate; and
the side wall is arranged on the semiconductor substrate and covers the side wall of the grid;
the region of the side wall arranged on the semiconductor substrate corresponds to a lightly doped drain region in the semiconductor substrate, and the heavily doped region is positioned on one side of the lightly doped drain region, which is far away from the grid electrode.
2. The semiconductor device structure of claim 1, wherein the semiconductor substrate comprises a substrate and a silicon nitride layer, a silicon oxide layer and an N-type substrate which are sequentially stacked and covered on the substrate, and the lightly doped drain region and the heavily doped region are both arranged in the N-type substrate; wherein,
the lightly doped drain region and the heavily doped region are both P-type doped regions.
3. The semiconductor device structure of claim 1, wherein the semiconductor substrate comprises a substrate and a silicon nitride layer, a silicon oxide layer and a P-type substrate which are sequentially stacked and covered on the substrate, and the lightly doped drain region and the heavily doped region are both arranged in the P-type substrate; wherein,
the lightly doped drain region and the heavily doped region are both N-type doped regions.
4. The semiconductor device structure of claim 2 or 3, wherein the semiconductor substrate further comprises:
and the second silicon dioxide layer covers the N-type substrate or the P-type substrate, and the grid is arranged on the second silicon dioxide layer.
5. The semiconductor device structure of claim 1, wherein a material of the gate comprises molybdenum.
6. The semiconductor device structure of claim 1, further comprising:
the barrier layer covers the upper surface and the side wall of the grid electrode and part of the upper surface of the semiconductor substrate, and the barrier layer covering the side wall of the grid electrode forms the side wall; wherein,
the height of the barrier layer is greater than the thickness of the barrier layer.
7. The semiconductor device structure of claim 6, further comprising:
and the second gate layer is covered on the barrier layer positioned on the upper surface and the side wall of the gate, and the material of the second gate layer comprises molybdenum.
8. The semiconductor device structure of claim 7, further comprising a silicon nitride film disposed between the second gate layer and the barrier layer.
9. A method for fabricating a semiconductor device structure, comprising:
providing a semiconductor substrate with a prepared grid;
forming a lightly doped region in the semiconductor substrate by using the grid as a mask and adopting a first vertical ion implantation process;
preparing a side wall with the side wall of the grid; and
forming a heavily doped region in part of the lightly doped region by using the side wall and the grid as masks and adopting a second vertical ion implantation process in the semiconductor substrate;
and in the second vertical ion implantation process, the lightly doped region which is not secondarily doped forms a lightly doped drain region.
10. The method of claim 9, wherein the sidewall spacers are formed of silicon oxide or silicon nitride.
11. The method of claim 9, wherein the second vertical ion implantation process implants ions at a concentration greater than the concentration of ions implanted by the first vertical ion implantation process.
12. The method according to claim 9, wherein the semiconductor substrate comprises a base plate, and a silicon nitride layer, a silicon oxide layer and an N-type substrate which are sequentially arranged on the base plate from bottom to top, and the lightly doped drain region and the heavily doped region are both arranged in the N-type substrate;
and the lightly doped drain region and the heavily doped region are both P-type doped regions.
13. The method according to claim 9, wherein the semiconductor substrate comprises a base plate, and a silicon nitride layer, a silicon oxide layer and a P-type substrate which are sequentially arranged on the base plate from bottom to top, and the lightly doped drain region and the heavily doped region are both arranged in the P-type substrate;
and the lightly doped drain region and the heavily doped region are both N-type doped regions.
14. The manufacturing method according to claim 12 or 13, wherein the semiconductor substrate further comprises:
and the second silicon dioxide layer covers the N-type substrate or the P-type substrate, and the grid is arranged on the second silicon dioxide layer.
15. The method according to claim 9, wherein the lightly doped drain region has a width consistent with a thickness of the sidewall; and is
And adjusting the width of the lightly doped drain region by adjusting the thickness of the side wall.
16. The method of claim 9, wherein the step of forming the sidewall spacers to cover the sidewalls of the gate comprises:
preparing a barrier layer to cover the upper surface and the side wall of the grid electrode and the exposed upper surface of the semiconductor substrate, wherein the barrier layer covering the side wall of the grid electrode forms the side wall, and the height of the side wall is larger than the thickness of the side wall.
17. The method of claim 16, wherein prior to performing the second vertical ion implantation process, the method further comprises:
and vertically and directionally etching the barrier layer partially covering the exposed upper surface of the semiconductor substrate to improve the ion implantation depth of the heavily doped region.
18. The method of claim 9, wherein after the step of forming the heavily doped region and the lightly doped drain region, the method further comprises:
and sputtering a second gate layer on the gate to increase the capacitance formed between the second gate layer and the gate.
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| CN109037045A (en) * | 2018-06-20 | 2018-12-18 | 武汉华星光电技术有限公司 | The production method and semiconductor devices of a kind of ion injection method, semiconductor devices |
| WO2020192555A1 (en) * | 2019-03-25 | 2020-10-01 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method therefor, substrate and preparation method therefor, and display device |
| CN112366179A (en) * | 2020-10-15 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method |
| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
| US20220244581A1 (en) * | 2019-07-24 | 2022-08-04 | Rockley Photonics Limited | Electro-optic modulator |
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| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
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