CN110676321A - Trench MOSFET and method of manufacturing the same - Google Patents

Trench MOSFET and method of manufacturing the same Download PDF

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Publication number
CN110676321A
CN110676321A CN201810713734.2A CN201810713734A CN110676321A CN 110676321 A CN110676321 A CN 110676321A CN 201810713734 A CN201810713734 A CN 201810713734A CN 110676321 A CN110676321 A CN 110676321A
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gate electrode
epitaxial layer
substrate
conductivity type
doping concentration
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张新
李巍
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Wuxi China Resources Huajing Microelectronics Co Ltd
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Wuxi China Resources Huajing Microelectronics Co Ltd
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel

Abstract

The application provides a trench MOSFET and a method of manufacturing the same. The trench MOSFET includes: a substrate having a first conductivity type; an epitaxial layer having a first conductivity type formed over the substrate, the epitaxial layer having a doping concentration lower than that of the substrate; a trench formed in the epitaxial layer; the gate structure is filled in the groove and comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and a dielectric layer filled at the side part of the control gate electrode; the multiple injection regions are formed in the epitaxial layer and have the first conductivity type, the multiple injection regions are distributed from top to bottom and are positioned on the side parts of the shielding gate electrode, and the doping concentration of the injection regions is greater than that of the epitaxial layer; a body region of the second conductivity type formed in the epitaxial layer and located over the plurality of implant regions; and the source region is formed in the epitaxial layer and positioned above the body region and has the first conductivity type, and the doping concentration of the source region is greater than that of the body region.

Description

Trench MOSFET and method of manufacturing the same
Technical Field
The application relates to the technical field of semiconductors, in particular to a trench MOSFET and a manufacturing method thereof.
Background
In the development of the Semiconductor Field, for a low-voltage MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), reducing on-resistance is an important issue.
The SGTMOS (shielded Gate Trench MOS) includes a substrate, an epitaxial layer located over the substrate, and a device structure located within the epitaxial layer. In the prior art, the doping concentration of the epitaxial layer of the SGTMOS is constant, and the specific on resistance (on resistance per unit area) of the SGTMOS can be reduced by increasing the doping concentration of the epitaxial layer, but the withstand voltage of the SGTMOS is also reduced. Therefore, the conventional SGTMOS cannot further reduce the specific on-resistance of the SGTMOS without reducing the withstand voltage of the SGTMOS.
Disclosure of Invention
According to a first aspect of embodiments of the present application, there is provided a trench MOSFET, comprising:
a substrate having a first conductivity type;
an epitaxial layer having a first conductivity type formed over the substrate, the epitaxial layer having a doping concentration lower than a doping concentration of the substrate;
a trench formed in the epitaxial layer;
a gate structure filled in the trench, the gate structure including a shield gate electrode;
a plurality of injection regions with a first conductivity type formed in the epitaxial layer, wherein the injection regions are arranged from top to bottom and are positioned at the side parts of the shielding gate electrode, and the doping concentration of the injection regions is greater than that of the epitaxial layer;
a body region of a second conductivity type formed in the epitaxial layer and over the plurality of implant regions;
and the source region is formed in the epitaxial layer and positioned above the body region and has the first conductivity type, and the doping concentration of the source region is greater than that of the body region.
In one embodiment of the present application, a distance h1 between the bottom of the lowermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm different from a distance h2 between the bottom of the shield gate electrode and the upper surface of the substrate, and a distance h3 between the top of the uppermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm different from a distance h4 between the top of the shield gate electrode and the upper surface of the substrate.
In one embodiment of the present application, the number of the implantation regions is two to five.
In one embodiment of the present application, the plurality of implant regions are uniformly spaced.
In one embodiment of the present application, the doping concentration of a plurality of the implanted regions is the same.
In an embodiment of the present application, the doping concentrations of the plurality of implantation regions sequentially increase or sequentially decrease from top to bottom.
In an embodiment of the present application, the gate structure further includes a control gate electrode located above the shield gate electrode, a dielectric layer covering the shield gate electrode, and a dielectric layer filled at a side of the control gate electrode. According to a second aspect of embodiments of the present application, there is provided a method of manufacturing a trench MOSFET, the method including:
preparing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is less than that of the substrate;
preparing a plurality of injection regions with a first conductivity type in the epitaxial layer, wherein the plurality of injection regions are distributed from top to bottom, and the doping concentration of the injection regions is greater than that of the epitaxial layer;
preparing a groove in the epitaxial layer;
preparing a gate structure in the trench, wherein the gate structure comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and filling the side part of the control gate electrode, and the shielding gate electrode is positioned on the side part of the injection regions;
preparing a body region with a second conductivity type above the plurality of implanted regions in the epitaxial layer;
preparing a source region with the first conductivity type above the body region in the epitaxial layer, wherein the doping concentration of the source region is greater than that of the body region.
In one embodiment of the present application, a distance h1 between the bottom of the lowermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm different from a distance h2 between the bottom of the shield gate electrode and the upper surface of the substrate, and a distance h3 between the top of the uppermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm different from a distance h4 between the top of the shield gate electrode and the upper surface of the substrate.
In one embodiment of the present application, the plurality of implant regions are uniformly spaced.
According to the trench MOSFET and the manufacturing method thereof provided by the embodiment of the application, the plurality of injection regions which are arranged from top to bottom and are positioned at the side part of the control gate electrode are formed in the epitaxial layer, so that the doping concentrations of the epitaxial layer at different positions of the part of the epitaxial layer in the height range of the control gate electrode can be adjusted. When the trench MOSFET is subjected to a reverse voltage, the electric field in the height range of the control gate electrode is significantly increased, and therefore, the withstand voltage of the trench MOSFET can be improved. And because the doping concentration of the plurality of injection regions is greater than that of the epitaxial layer, the specific on-resistance of the trench MOSFET can be reduced.
Drawings
Fig. 1 is a schematic structural diagram of a trench MOSFET according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of another trench MOSFET according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of another trench MOSFET according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another trench MOSFET according to an embodiment of the present application;
FIG. 5 is a schematic view of a trench MOSFET structure without an implanted region formed therein and the electric field distribution;
fig. 6 is a schematic diagram of a structure and an electric field distribution of a trench MOSFET according to an embodiment of the present application;
fig. 7 is a flowchart of a method for manufacturing a trench MOSFET according to an embodiment of the present application.
The reference numerals in the figures are respectively:
1. a substrate;
2. an epitaxial layer;
3. a trench;
4. a gate structure;
401. a shield gate electrode;
402. a control gate electrode;
403. a dielectric layer;
5. an implantation region;
6. a body region;
7. a source region;
8. a source electrode;
9. a drain electrode;
10. an insulating layer;
11. the hole is filled.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "plurality" includes two, and is equivalent to at least two. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The shielded gate trench MOSFET and the manufacturing method thereof in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the following examples and embodiments can be supplemented or combined with each other without conflict.
Fig. 1 to 4 are schematic structural views of a trench MOSFET according to an embodiment of the present invention, fig. 5 is a schematic structural view and an electric field distribution view of a trench MOSFET without an implant region according to an embodiment of the present invention, and fig. 6 is a schematic structural view and an electric field distribution view of a trench MOSFET according to an embodiment of the present invention. The trench MOSFET provided by the embodiment of the application is a low-voltage (less than 100V) MOSFET.
In the embodiment of the present application, the direction pointing from the substrate to the epitaxial layer is upward.
Referring to fig. 1 to 4, a trench MOSFET provided in an embodiment of the present application includes:
a substrate 1 having a first conductivity type;
an epitaxial layer 2 having a first conductivity type formed over a substrate 1, the doping concentration of the epitaxial layer 2 being lower than the doping concentration of the substrate 1;
a trench 3 formed in the epitaxial layer 2;
a gate structure 4 filled in the trench 3, the gate structure 4 including a shield gate electrode 401;
a plurality of implantation regions 5 with a first conductivity type formed in the epitaxial layer 2, the implantation regions 5 being arranged from top to bottom and located at the side of the shield gate electrode 401, the doping concentration of the implantation regions 5 being greater than the doping concentration of the epitaxial layer 2;
a body region 6 of the second conductivity type formed in the epitaxial layer 2 and located above the plurality of implanted regions 5;
a source region 7 of the first conductivity type formed in the epitaxial layer 2 and located above the body region 6, the doping concentration of the source region 7 being greater than the doping concentration of the body region 6;
a source electrode 8; and
and a drain electrode 9.
According to the trench MOSFET provided by the embodiment of the application, the plurality of implantation regions 5 arranged from top to bottom are formed in the epitaxial layer 2 and located at the side portion of the shielding gate electrode 401, so that the doping concentrations of the epitaxial layer 2 at different positions of the portion in the height range of the shielding gate electrode 401 can be adjusted. As can be seen from a comparison of fig. 5 and 6, by forming a plurality of implantation regions 5 in the portion of the epitaxial layer 2 within the height range of the shield gate electrode 401, the electric field within the height range of the shield gate electrode 401 can be significantly increased when the trench MOSFET is subjected to a reverse voltage, and therefore, the withstand voltage of the trench MOSFET can be improved. And because the doping concentration of the plurality of injection regions 5 is greater than that of the epitaxial layer 2, the specific on-resistance of the trench MOSFET can be reduced by 15% -20%.
In one embodiment of the present application, the distance h1 between the bottom of the lowermost implant region 5 and the upper surface of the substrate 1 is in the range of-0.2 μm to 0.2 μm from the distance h2 between the bottom of the shield gate electrode 401 and the upper surface of the substrate 1, and the distance h3 between the top of the uppermost implant region 5 and the upper surface of the substrate 1 is in the range of-0.2 μm to 0.2 μm from the distance h4 between the top of the shield gate electrode 401 and the upper surface of the substrate 1. Referring to fig. 5, it can be seen that the electric field distribution of the epitaxial layer 2 of the trench MOSFET, in which the implantation region 5 is not formed, has a valley at a portion corresponding to the shield gate electrode 401. Forming the plurality of implantation regions 5 in the region of the epitaxial layer 2 corresponding to the shield gate electrode 401 can increase the electric field at the region of the epitaxial layer 2 corresponding to the shield gate electrode 401, and make the electric field distribution in this region closer to a rectangle, thereby improving the withstand voltage of the trench MOSFET.
In one embodiment of the present application, the gate structure 4 further includes a control gate electrode 402 located above the shield gate electrode 401, a dielectric layer 403 covering the shield gate electrode 401 and filling the side of the control gate electrode 402. The dielectric layer 403 includes a field oxide layer covering the shield gate electrode 401 and a gate oxide layer filled at the side of the control gate electrode 402. The field oxide layer on the bottom and side of the shield gate electrode 401 may be formed by thermal oxidation deposition, and the field oxide layer between the shield gate electrode 401 and the control gate electrode 402 may be formed by high density plasma chemical vapor deposition (HDP) process.
In one embodiment of the present application, the number of implanted regions 5 is two to five. The larger the number of the implantation regions 5, the more the electric field distribution of the trench MOSFET is close to rectangular, but at the same time, the complexity of the manufacturing process of the trench MOSFET is also increased. Considering the electric field distribution and the complexity of the manufacturing process, the number of the implantation regions 5 is preferably three.
In one embodiment of the present application, the plurality of implant regions 5 are uniformly spaced. The plurality of injection regions 5 are arranged at intervals, and compared with continuous distribution, the manufacturing process is simpler and the manufacturing cost is lower.
In one embodiment of the present application, the doping concentration of the plurality of implanted regions 5 is the same.
In another embodiment of the present application, the doping concentrations of the plurality of implantation regions 5 sequentially increase or sequentially decrease from top to bottom. In other embodiments, the doping concentration of the plurality of implantation regions 5 may also be irregularly distributed.
For MOSFETs with different sizes and different trench depths, the doping concentrations in different distribution ranges can be selected to make the electric field distribution more approximate to a rectangle, and the doping concentration of the implantation region is determined according to the withstand voltage of the MOSFET.
In one embodiment of the present application, the trench MOSFET further includes an insulating layer 10 over the control gate electrode 402 and the source region 7. Filling holes 11 are formed in the insulating layer 10, the body region 6, and the source region 7. The source electrode 8 includes a metal layer over the insulating layer 10 and a metal filled in the filling hole 11.
In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. That is, the substrate 1 is an N-type substrate, the epitaxial layer 2 is an N-type epitaxial layer, the body region 6 is formed by P-type doping, the source region 7 is formed by N-type doping, and the implantation region 5 is formed by N-type doping.
In the trench MOSFET provided in the embodiment of the present application, the doping concentrations and thicknesses of the epitaxial layer 2 and the implantation region 5 may be determined according to the requirement of the trench MOSFET for withstanding voltage.
Fig. 7 is a flowchart of a method for manufacturing a trench MOSFET according to an embodiment of the present application. Referring to fig. 7, the preparation method includes the following steps 201 to 210.
In step 201, an epitaxial layer having a first conductivity type is prepared on a substrate having the first conductivity type, and the doping concentration of the epitaxial layer is less than that of the substrate.
In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type.
In one embodiment of the present application, an N-type doped semiconductor may be used as a substrate, and an N-type lightly doped semiconductor may be deposited on the substrate by an epitaxial growth method to form an epitaxial layer.
In step 202, a plurality of implantation regions of the first conductivity type are formed in the epitaxial layer from top to bottom, and the doping concentration of the implantation regions is greater than that of the epitaxial layer.
When the plurality of injection regions are prepared, the plurality of injection regions are prepared according to the sequence from bottom to top, namely, the injection region positioned below is prepared firstly, and the injection region positioned above is prepared.
In one embodiment of the present application, the distance h1 between the bottom of the lowermost implanted region and the upper surface of the substrate is in the range of-0.2 μm to 0.2 μm from the distance h2 between the bottom of the shield gate electrode and the upper surface of the substrate, and the distance h3 between the top of the uppermost implanted region and the upper surface of the substrate is in the range of-0.2 μm to 0.2 μm from the distance h4 between the top of the shield gate electrode and the upper surface of the substrate.
In one embodiment of the present application, a plurality of N-type implant regions are formed in the epitaxial layer by implanting impurities through an annealing process.
In one embodiment of the present application, the number of implanted regions is two to five, and may be three, for example.
In one embodiment of the present application, the plurality of implant regions are uniformly spaced. Compared with continuous distribution, the multiple injection regions are arranged at intervals, the manufacturing process is simple, and the manufacturing cost is lower.
In one embodiment of the present application, the doping concentrations of the plurality of implanted regions are the same.
In another embodiment of the present application, the doping concentrations of the plurality of implanted regions sequentially increase or sequentially decrease from top to bottom. In other embodiments, the doping concentrations of the plurality of implanted regions may be irregularly distributed.
In step 203, trenches are prepared in the epitaxial layer.
In one embodiment of the present application, trenches are formed in the epitaxial layer by photolithography and etching techniques.
In step 204, a gate structure is prepared within the trench, the gate structure including a shield gate electrode.
In the embodiment of the application, the gate structure further comprises a control gate electrode located above the shield gate electrode, a dielectric layer covering the shield gate electrode and filled at the side part of the control gate electrode, and the shield gate electrode is located at the side part of the injection regions.
In one embodiment of the present application, the dielectric layer covering the shield gate electrode is a field oxide layer, and the dielectric layer filled at the side portion of the control gate electrode is a gate oxide layer.
In one embodiment of the present application, field oxide layers are formed on sidewalls of a bottom and a lower side of a trench through a thermal oxidation deposition process, a shield gate electrode is formed through a deposition of polysilicon and an etching technique, a field oxide layer is formed over the shield gate electrode through a high density plasma chemical vapor deposition (HDP) and an etching process, a gate oxide layer is formed on sidewalls of an upper side of the trench through the thermal oxidation deposition process, and a control gate electrode is formed over the field oxide layer through the deposition of polysilicon and the etching technique.
In step 205, body regions of the second conductivity type are prepared in the epitaxial layer over the plurality of implanted regions.
In one embodiment of the present application, a P-type body region is formed in the epitaxial layer by implanting impurities through an annealing process. The P-type body region is arranged at intervals with the uppermost injection region.
In step 206, a source region of the first conductivity type is formed in the epitaxial layer over the body region, the source region having a doping concentration greater than a doping concentration of the body region.
In one embodiment of the present application, an N-type source region is formed at an upper portion of the body region by implanting impurities through an annealing process.
In step 207, an insulating layer is prepared over the control gate electrode and the source region.
In one embodiment of the present application, an insulating layer is formed over the trench and the source region by chemical vapor deposition.
In step 208, contact holes are made in the insulating layer, body regions, and source regions.
In one embodiment of the present application, contact holes are formed in the insulating layer, the body region, and the source region by photolithography and etching techniques.
In step 209, a source electrode is prepared in the contact hole and over the insulating layer.
In one embodiment of the present application, a metal layer is formed over the insulating layer and filled in the contact hole by a metal sputtering process, and the metal layer in the contact hole constitute a source electrode.
In step 210, a drain is fabricated below the substrate.
In one embodiment of the present application, the drain electrode is formed by a metal evaporation process.
According to the preparation method of the trench MOSFET, the plurality of injection regions which are arranged from top to bottom and located on the side portion of the control gate electrode are formed in the epitaxial layer, so that the doping concentrations of the epitaxial layer at different positions of the portion of the epitaxial layer in the height range of the control gate electrode can be adjusted. When the trench MOSFET is subjected to a reverse voltage, the electric field in the height range of the control gate electrode is significantly increased, and therefore, the withstand voltage of the trench MOSFET can be improved. And because the doping concentration of the plurality of injection regions is greater than that of the epitaxial layer, the specific on-resistance of the trench MOSFET can be reduced by 15% -20%.
Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (10)

1. A trench MOSFET, comprising:
a substrate (1) having a first conductivity type;
an epitaxial layer (2) of a first conductivity type formed over the substrate (1), the doping concentration of the epitaxial layer (2) being lower than the doping concentration of the substrate (1);
a trench (3) formed in the epitaxial layer (2);
a gate structure (4) filled in the trench (3), the gate structure (4) comprising a shield gate electrode (401);
a plurality of injection regions (5) with a first conductivity type formed in the epitaxial layer (2), wherein the plurality of injection regions (5) are arranged from top to bottom and are positioned at the side part of the shielding gate electrode (401), and the doping concentration of the injection regions (5) is greater than that of the epitaxial layer (2);
a body region (6) of a second conductivity type formed in said epitaxial layer (2) and located above said plurality of implanted regions (5);
a source region (7) of the first conductivity type formed in the epitaxial layer (2) and located above the body region (6), the source region (7) having a doping concentration greater than a doping concentration of the body region (6).
2. The trench MOSFET of claim 1 wherein a distance h1 between the bottom of the lowermost implant region (5) and the upper surface of the substrate (1) differs from a distance h2 between the bottom of the shield gate electrode (401) and the upper surface of the substrate (1) by a range of-0.2 μm to 0.2 μm, and a distance h3 between the top of the uppermost implant region (5) and the upper surface of the substrate (1) differs from a distance h4 between the top of the shield gate electrode (401) and the upper surface of the substrate (1) by a range of-0.2 μm to 0.2 μm.
3. The trench MOSFET of claim 1 wherein the number of implanted regions (5) is two to five.
4. The trench MOSFET of claim 1 wherein the plurality of implanted regions (5) are uniformly spaced.
5. Trench MOSFET according to claim 1, characterized in that the doping concentration of a plurality of said implanted regions (5) is the same.
6. The trench MOSFET of claim 1 wherein the doping concentration of the plurality of implanted regions (5) increases or decreases sequentially from top to bottom.
7. The trench MOSFET of claim 1 wherein the gate structure (4) further comprises a control gate electrode (402) over the shield gate electrode (401), a dielectric layer (403) encapsulating the shield gate electrode (401) and filling the sides of the control gate electrode (402).
8. A method of fabricating a trench MOSFET, the method comprising:
preparing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is less than that of the substrate;
preparing a plurality of injection regions with a first conductivity type in the epitaxial layer, wherein the plurality of injection regions are distributed from top to bottom, and the doping concentration of the injection regions is greater than that of the epitaxial layer;
preparing a groove in the epitaxial layer;
preparing a gate structure in the trench, wherein the gate structure comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and filling the side part of the control gate electrode, and the shielding gate electrode is positioned on the side part of the injection regions;
preparing a body region with a second conductivity type above the plurality of implanted regions in the epitaxial layer;
preparing a source region with the first conductivity type above the body region in the epitaxial layer, wherein the doping concentration of the source region is greater than that of the body region.
9. The method of claim 8, wherein a distance h1 between a bottom of the lowermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm from a distance h2 between a bottom of the shield gate electrode and the upper surface of the substrate, and a distance h1 between a top of the uppermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm from a distance h3 between the top of the shield gate electrode and the upper surface of the substrate.
10. The method of claim 8 wherein the plurality of implanted regions are uniformly spaced.
CN201810713734.2A 2018-07-03 2018-07-03 Trench MOSFET and method of manufacturing the same Pending CN110676321A (en)

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CN112185816A (en) * 2020-08-14 2021-01-05 江苏东海半导体科技有限公司 High-energy-efficiency shielded gate trench MOSFET and manufacturing method thereof
CN113299750A (en) * 2020-02-21 2021-08-24 苏州东微半导体股份有限公司 Semiconductor power device

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CN107546257A (en) * 2017-08-23 2018-01-05 恒泰柯半导体（上海）有限公司 The epitaxial layer structure of metal oxide channel semiconductor field-effect transistor

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