CN105225958B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN105225958B CN105225958B CN201410308867.3A CN201410308867A CN105225958B CN 105225958 B CN105225958 B CN 105225958B CN 201410308867 A CN201410308867 A CN 201410308867A CN 105225958 B CN105225958 B CN 105225958B
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Abstract
A kind of forming method of fin formula field effect transistor, including：Semiconductor substrate is provided, semiconductor substrate surface is formed with more than two discrete and arranged in parallel fins；Separation layer is formed, insulation surface is less than the top surface of fin；The gate structure of multiple fins is developed across in insulation surface；The first ion implanting is carried out to gate structure side fin, the acute angle of the injection direction of the first ion implanting between the projection of semiconductor substrate surface and fin length direction is the first torsion angle, and first torsion angle is more than 0 ° and is less than 45 °；The second ion implanting is carried out to gate structure opposite side fin, and acute angle of the injection direction of the second ion implanting between the projection of semiconductor substrate surface and fin length direction is the second torsion angle, second torsion angle is more than 0 ° and is less than 45 °.The above method can reduce blocking effect of the adjacent fin to ion implanting, so as to improve the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of fin formula field effect transistor.
Background technology
With the continuous development of semiconductor process technique, process node is gradually reduced, and rear grid (gate-last) technique obtains
Extensive use to obtain ideal threshold voltage, improves device performance.But when the characteristic size of device further declines
When, even if using rear grid technique, the structure of conventional metal-oxide-semiconductor field effect transistor also can not meet the needs of to device performance, more
Gate device has obtained extensive concern as the replacement of conventional device.
Fin formula field effect transistor is a kind of common multi-gate device, as shown in Figure 1, for existing fin field effect crystal
The structure diagram of pipe.The fin formula field effect transistor includes Semiconductor substrate 10；Several fins 20 on substrate 10；
Separation layer 30 positioned at 10 surface of Semiconductor substrate, the surface of the separation layer 30 is less than the top surface of fin 20, and covers
The partial sidewall of lid fin 20；Positioned at 30 surface of separation layer and across the gate structure of the fin 20, the gate structure packet
Include gate dielectric layer 41 and the grid 42 positioned at 41 surface of gate dielectric layer.It is also formed in the fin 20 of the gate structure both sides
There is source electrode and drain electrode.In order to improve the channel region area of fin formula field effect transistor, the grid of the fin formula field effect transistor
Structure is generally across multiple fins 20.
The prior art during the fin formula field effect transistor is formed, it is elongated can be in the raceway groove below gate structure
Pocket ion implanting is carried out between region and source electrode, drain region, the Doped ions type of the pocket ion implanting is with treating shape
Into fin formula field effect transistor type on the contrary, the source electrode and drain electrode of the fin formula field effect transistor of formation can be improved between
Punch through voltage, so as to inhibit the Punchthrough effect of fin formula field effect transistor, improve the performance of fin formula field effect transistor.
But in the prior art, the effect of the pocket ion implanting carried out to fin formula field effect transistor is poor, pocket note
The Doped ions entered are hardly entered close to the part of channel region in source region, drain region, so as to be imitated to fin field
The performance improvement for answering transistor is limited, needs further to improve the technique of the pocket ion implanting, to further improve fin
The performance of field-effect transistor.
Invention content
It is of the invention to solve the problems, such as to be to provide a kind of forming method of fin formula field effect transistor, improve the fin field of formation
The performance of effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：Offer is partly led
Body substrate, the semiconductor substrate surface are formed with more than two discrete and arranged in parallel fins；In the Semiconductor substrate
Surface forms separation layer, and the insulation surface is less than the top surface of fin and the partial sidewall of covering fin；It is described every
Absciss layer surface is developed across the gate structure of one or more fins, and the gate structure covers the fin side wall and top；
First ion implanting, injection direction and the gate structure phase of first ion implanting are carried out to gate structure side fin
It is right, and the injection direction of first ion implanting is sharp between the projection of semiconductor substrate surface and fin length direction
Angle angle is the first torsion angle, and first torsion angle is more than 0 ° and is less than 45 °；The is carried out to the gate structure opposite side fin
Two ion implantings, the injection direction of second ion implanting is opposite with gate structure, and the note of second ion implanting
Enter acute angle of the direction between the projection of semiconductor substrate surface and fin length direction for the second torsion angle, described second
Torsion angle is more than 0 ° and is less than 45 °.
Optionally, first torsion angle is identical with the second torsion angle size.
Optionally, first ion implanting includes：First direction ion implanting is carried out to the side of fin, then to institute
The opposite side for stating fin carries out second direction ion implanting.
Optionally, the injection direction of the first direction ion implanting and the injection direction of second direction ion implanting about
The length direction of fin is symmetrical.
Optionally, second ion implanting includes：Third direction ion implanting is carried out to the side of fin, then to institute
The opposite side for stating fin carries out fourth direction ion implanting.
Optionally, the injection direction of the third direction ion implanting and the injection direction of fourth direction ion implanting about
The length direction of fin is symmetrical.
Optionally, the Semiconductor substrate is wafer, and the crystal round fringes have alignment mark, the alignment mark and crystalline substance
Line between the round heart is vertical with the length direction of fin.
Optionally, the tangent value at the inclination angle between the injection direction of first ion implanting and Semiconductor substrate normal
Less than or equal to the ratio at the top of the spacing and fin of adjacent fin between the difference in height of insulation surface.
Optionally, the tangent value at the inclination angle between the injection direction of second ion implanting and Semiconductor substrate normal
Less than or equal to the ratio at the top of the spacing and fin of adjacent fin between the difference in height of insulation surface.
Optionally, the inclination angle between the injection direction of second ion implanting and Semiconductor substrate normal with first from
The injection direction of son injection is identical with the inclination angle between Semiconductor substrate normal.
Optionally, the accumulated dose of the accumulated dose and the second ion implanting of first ion implanting differs.
Optionally, the type of the Doped ions of first ion implanting and the second ion implanting and fin field to be formed
The type of effect transistor is opposite.
Optionally, the ion energy of first ion implanting is 15KeV~60KeV, dosage 3E13atom/cm2~
6E13atom/cm2。
Optionally, the ion energy of first direction ion implanting is 15KeV~60KeV, dosage 1.5E13atom/cm2
~3E13atom/cm2；The ion energy of second direction ion implanting is 15KeV~60KeV, dosage 1.5E13atom/cm2~
3E13atom/cm2。
Optionally, the ion energy of second ion implanting is 15KeV~60KeV, dosage 3E13atom/cm2~
6E13atom/cm2。
Optionally, the ion energy of third direction ion implanting is 15KeV~60KeV, dosage 1.5E13atom/cm2
~3E13atom/cm2；The ion energy of fourth direction ion implanting is 15KeV~60KeV, dosage 1.5E13atom/cm2~
3E13atom2。
Optionally, before first ion implanting and the second ion implanting is carried out, to the gate structure both sides
Fin carries out that ion implanting is lightly doped, and the Doped ions type that ion implanting is lightly doped is brilliant with fin field effect to be formed
The type of body pipe is identical.
Optionally, after first ion implanting and the second ion implanting is carried out, to the gate structure both sides
Fin carries out that ion implanting is lightly doped, and the Doped ions type that ion implanting is lightly doped is brilliant with fin field effect to be formed
The type of body pipe is identical.
Optionally, after the first ion implanting and the second ion implanting is carried out to the fin, the fin is carried out
Heavy doping ion is injected, and forms the source electrode positioned at gate structure side and the drain electrode positioned at gate structure opposite side.
Compared with prior art, technical scheme of the present invention has the following advantages：
In technical scheme of the present invention, more than two discrete and arranged in parallel fins are formed on a semiconductor substrate；So
Surface is formed on a semiconductor substrate afterwards less than the separation layer at the top of fin, one or more is developed across on the separation layer
The gate structure of fin；Then the first ion implanting, first ion implanting are carried out to the fin of the gate structure side
First torsion angle of the injection direction between the projection of semiconductor substrate surface and fin length direction be more than 0 ° and be less than 45 °,
First torsion of the injection direction of second ion implanting between the projection of semiconductor substrate surface and fin length direction
Angle is more than 0 ° and is less than 45 °.On the one hand, since first torsion angle and the second torsion angle are more than 0 °, so first ion
Injection and the second ion implanting have the component perpendicular to fin, and Doped ions can enter fin；On the other hand, it was injecting
Cheng Zhong, in order to reduce the barrier effect of adjacent fin, enable the injection ion of the first ion implanting and the second ion implanting into
Enter the fin of gate structure adjacent edges, first torsion angle and the second torsion angle have critical value, and the critical value is equal to
Arctan (s/d), wherein, the spacing between adjacent fin is s, and the length of the fin of gate structure side is d.Due to current device
The integrated level of part is higher, and the distance s between adjacent fin are usually less than the length d of the fin of gate structure side, so
Arctan (s/d) is less than 45 °.So when the first torsion angle and the second torsion angle of technical scheme of the present invention are less than 45 °, it can be with
Barrier effect of the adjacent fin for the first ion implanting and the second ion implanting is reduced, makes the first ion implanting and the second ion
The Doped ions of injection can enter or close proximity to channel region, while first torsion angle and the second torsion angle are smaller,
The barrier effect of adjacent fin is smaller.
Further, have the between the ion implanting direction of first ion implanting and the normal direction of Semiconductor substrate
One inclination angle has second to tilt between the ion implanting direction of second ion implanting and the normal direction of Semiconductor substrate
The tangent value at angle, first inclination angle and the second inclination angle is less than or equal to the spacing of adjacent fin with fin top with being isolated
Ratio between the difference in height of layer surface, so that the Doped ions of the first ion implanting and the second ion implanting can
It reaches in the fin of separation layer, the doped region of the formation made is distributed in the short transverse of fin more uniformly, so as to carry
High first ion implanting and the second ion implanting for the Punchthrough problem of fin formula field effect transistor improvement,
And then improve the performance of fin formula field effect transistor.
Description of the drawings
Fig. 1 is the structure diagram of the fin formula field effect transistor of the prior art of the present invention；
Fig. 2 to Figure 14 is the structure diagram of the forming process of the fin formula field effect transistor of the embodiment of the present invention.
Specific embodiment
As described in the background art, the existing pocket ion implanting carried out to fin formula field effect transistor enters source area
Ion dose in domain, drain region close to channel region is smaller, the punch through of source-drain electrode is improved limited.
The study found that since the prior art would generally form several adjacent fins, also, fin on a semiconductor substrate
The gate structure of field-effect transistor generally also can be simultaneously across multiple fins, to improve the channel region of fin formula field effect transistor
Area.Since the integrated level of existing semiconductor chip is all higher, so, the spacing between adjacent fin is also smaller.The pocket
Ion implanting needs to inject Doped ions in the fin between channel region and source drain region, so, the pocket ion
The injection direction of injection would generally have certain angle between the short transverse of fin and the length direction of fin, will
Doped ions inject fin at the position of gate structure.
Due to stereochemical structure of the fin for protrusion, need to carry out ion implanting to the both sides of source electrode and drain electrode respectively,
It is existing during ion implanting is carried out, the certain situation of angle in ion implanting direction and the short transverse stent of fin
Under, it is general so that the angle between the projection on a semiconductor substrate of ion implanting direction and fin length direction be 45 ° or
90 °, in order to source electrode and drain electrode different location carry out ion implanting when, facilitate adjustment inject angle.When the angle is
At 45 °, since the distance between adjacent fin is smaller, during pocket ion implanting is carried out, adjacent fin can be to note
The ion beam entered has certain effect of blocking, and so as to generate shadow effect to ion implanting, above-mentioned pocket ion implanting is caused to arrive
It is reduced up to the quantity near channel region, Punchthrough problem can not be effectively improved；And when the angle is 90 °, and be difficult
The injection ion made enters in channel region, it is impossible to be effectively improved Punchthrough effect.
The embodiment of the present invention proposes a kind of forming method of fin formula field effect transistor, to fin carry out pocket from
During son injection, the angle between injection direction projection on a semiconductor substrate and the length direction of fin is made to be more than 0 °
Less than 45 °, reduce the barrier effect of adjacent fin.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Please refer to Fig.2, Semiconductor substrate 100 be provided, 100 surface of Semiconductor substrate be formed with it is more than two discrete and
Fin 101 arranged in parallel.
The material of the Semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs, the semiconductor
Substrate 100 can be that body material can also be composite construction such as silicon-on-insulator.Those skilled in the art can be according to partly leading
The semiconductor devices formed in body substrate 100 selects the type of the Semiconductor substrate 100, therefore the Semiconductor substrate 100
Type should not limit the scope of the invention.In the present embodiment, the material of the Semiconductor substrate 100 is monocrystalline silicon wafer
Circle.
Can also may be used by performing etching the formation fin 101 in the Semiconductor substrate 100 to Semiconductor substrate 100
After forming epitaxial layer in the Semiconductor substrate 100, etch the epitaxial layer and form the fin 101.
In the present embodiment, to form two fins 101 on a semiconductor substrate 100 as an example, the present invention other
In embodiment, multiple discrete and arranged in parallel fin 101 can also be formed in the Semiconductor substrate 100.
It please refers to Fig.3, forms separation layer 200 on 100 surface of Semiconductor substrate, 200 surface of separation layer is less than
The top surface of fin 101 and the partial sidewall for covering fin 101.
The material of the separation layer 200 can be the insulating dielectric materials such as silica, silicon nitride, silicon oxide carbide, it is described every
Absciss layer 200 as the isolation structure between adjacent fin 101 and the gate structure being subsequently formed and Semiconductor substrate 100 it
Between isolation structure.
The forming method of the separation layer 200 includes：The depositing isolation material in the Semiconductor substrate 100, it is described every
Fin 101 is covered from material, and fills the groove between the adjacent fin 101 of full phase；Using 101 top of the fin as grinding
Stop-layer is ground, planarization process is carried out to the isolated material using chemical mechanical milling tech, is formed and 101 top table of fin
The spacer material layer that face flushes；Then, the spacer material layer is etched back, makes the apparent height of the spacer material layer
Decline, form the separation layer 200 that surface is less than 101 top surface of fin.
It is formed after the fin 101, ion doping, such as trap doping, adjusting thresholds can be carried out to the fin 101
Doping etc..
In the present embodiment, the Semiconductor substrate 100 is wafer, and the crystal round fringes have alignment mark, the alignment
Label can be notch or groove etc., and the alignment mark hangs down with the direction of wafer circle center line connecting and the length direction of fin 101
Directly.In other embodiments of the invention, the length direction of the fin 101 can also be connects with alignment mark and the wafer center of circle
The direction of line is parallel or into any angle.
It please refers to Fig.4, the gate structure 300 of multiple fins 101, the grid is developed across on 200 surface of separation layer
Pole structure 300 covers 101 side wall of fin and top.
In the present embodiment, the gate structure 300 includes gate dielectric layer 301 and positioned at 301 surface of gate dielectric layer
Grid 302.The material of the grid 302 can be the gate metals material such as aluminium, tungsten, titanium, titanium nitride, tantalum or ramet, described
The material of gate dielectric layer 301 can be the high K dielectric materials such as hafnium oxide, zirconium oxide, aluminium oxide, silicon hafnium oxide or silicon zirconium oxide.
In the other embodiment of the present invention, the gate structure 300 is pseudo- grid structure.The gate structure 300 includes puppet
Gate dielectric layer 301 and the dummy grid 302 positioned at pseudo- 301 surface of gate dielectric layer.The material of the puppet gate dielectric layer 301 is oxygen
SiClx, the material of the dummy grid 302 is polysilicon, and subsequently using rear grid technique, it is described to replace to form metal gate structure
Gate structure 300.
In the present embodiment, the gate structure 300 is across two fins 101, so as to increase the gate structure
The area of the channel region of 300 lower sections.In other embodiments of the invention, according to the performance requirement of practical devices, the grid
Pole structure 300 can be across one or more fins.
Specifically, the forming method of the gate structure 300 includes：Gate medium material is formed on 200 surface of separation layer
The bed of material, the gate dielectric material layer cover the separation layer 200 and fin 101, and grid are formed in the gate dielectric material layer surface
Then pole material layer is patterned the gate material layers and gate dielectric material layer, be developed across the grid knot of fin 101
Structure 300.
It in other embodiments of the invention, can be to the gate structure after the gate structure 300 is formed
300 and 101 surface of fin carry out oxidation processes, form oxide layer on the gate structure 300 and 101 surface of fin.It can adopt
The oxide layer is formed with thermal oxidation technology, for repairing the damage of the gate structure 300,101 surface of fin, and it is described
Oxide layer during subsequently ion implanting is carried out to fin 101 can also avoid that channelling effect occurs.
It is formed after the gate structure 300, the first ion note is carried out to the fin 101 of 300 side of gate structure
Enter, the injection direction of first ion implanting is opposite with gate structure phase 300, and the injection side of first ion implanting
It is the first torsion angle to the acute angle between 101 length direction of the projection on 100 surface of Semiconductor substrate and fin, described the
One torsion angle is more than 0 ° and is less than 45 °.
The fin 101 of 300 side of gate structure is source electrode or drain region, and first ion implanting is needed in crystalline substance
Doped region, and the Doped ions type of first ion implanting are formed between the channel region of body pipe and source electrode or drain region
Type with fin formula field effect transistor to be formed is on the contrary, to improve the source-drain electrode punch through voltage of transistor.In the present embodiment,
First ion implanting is carried out to the source region of 300 side of gate structure.It in other embodiments of the invention, can also be to grid
Structure 300 side drain region in pole carries out first ion implanting.
Due to stereochemical structure of the fin for protrusion, in order to improve the uniform of the first ion implanting in the fin
Property, in the present embodiment, first ion implanting includes：First direction ion implanting is carried out to the side of fin 101, it is then right
The opposite side of the fin 101 carries out second direction ion implanting, so that it is guaranteed that the fin 101 positioned at 300 side of gate structure
Both sides side wall by ion implanting, so as to improve the uniformity of the first ion implanting.
Fig. 5 is please referred to, first direction ion note is carried out to being located at the side of fin 101 of 300 side of gate structure
Enter.Meanwhile Fig. 6 is please referred to, it is the angle schematic diagram of the first direction ion implanting.Wherein, Semiconductor substrate 100 is crystalline substance
It is round, the length of the line 01 and fin 101 (please referring to Fig. 5) between alignment mark 102 and the wafer center of circle in Semiconductor substrate 100
Spend that direction 02 is vertical, the projection on a semiconductor substrate 100 of the injection direction 11 of the first direction ion implanting and fin are long
The acute angle spent between direction 02 is the first torsion angle α 11, and the injection direction 11 of the first direction ion implanting is with partly leading
There is the first inclination angle Ψ 11 between the normal 03 of body substrate 100.
Since the purpose of first ion implanting is the source-drain electrode punch through voltage in order to improve transistor, described first from
Son injection needs to carry out ion implanting between the fin of 300 side of channel region and gate structure below gate structure 300,
In the present embodiment, the first torsion angle α 11 of the injection direction 11 of the first direction ion implanting is more than 0 °, can be with less than 45 °
Reduce barrier effect of the adjacent fin 101 to the first direction ion implanting.
Fig. 7 is please referred to, the schematic top plan view of first direction ion implanting is carried out for Fig. 5.
Fig. 7 shows that first direction ion implanting can form doped region between channel region and source electrode or drain region
Critical injection direction.At this point, between the injection direction 11 of the first direction ion implanting and the length direction of fin 101
First torsion angle α 11=arctan (s/d), wherein, spacing between adjacent fin 101 is s, the fin of 300 side of gate structure
The length in portion 101 is d.Since the integrated level of current device is higher, the distance s between adjacent fin 101 are usually less than grid knot
The length d of the fin 101 of 300 side of structure, so, the first torsion angle α 11=arctan (s/d) are usually less than 45 °.When described
One torsion angle α 11 is smaller, and the first direction ion implanting is smaller by the barrier effect of adjacent fin 101.
But during the first torsion angle α 11=0 °, the injection direction 11 and fin 101 of the first direction ion implanting are flat
Row, component is not injected into fin 101, and doped region can not be formed in fin 101, so, the first torsion angle α 11 is more than
0°。
So in the present embodiment, the first torsion angle α 11 is more than 0 °, less than 45 °.First direction can be reduced to the greatest extent
The barrier effect being subject to during ion implanting.If with the alignment mark and wafer circle center line connecting 01 as reference, described first
The injection direction 11 of direction ion implanting and the acute angle of alignment mark and the part of wafer circle center line connecting 01 are more than 45 °, are less than
90°。
Fig. 8 is please referred to, is along the diagrammatic cross-section of secant AA ' when first direction ion implanting is carried out in Fig. 5.
Due to having between the ion implanting direction 11 of the first direction ion implanting and the direction of Semiconductor substrate 100
First inclination angle Ψ 11, and the fin 101 is perpendicular to the Semiconductor substrate 100, so, the first inclination angle Ψ 11 with
Angle of the fin 101 in the plane perpendicular to Semiconductor substrate 100 is the first inclination angle Ψ 11.The first inclination angle Ψ 11
With critical value, to reduce the barrier effect of adjacent fin, so as to make the first direction ion implanting enable to be higher than every
The fin 101 of absciss layer 200 is by ion implanting.
The critical localisation of first inclination angle Ψ 11 is shown in Fig. 8, at this point, Ψ 11=arctan (s/h), wherein, phase
Spacing between adjacent fin 101 is s, and fin 101 is h higher than the height of 200 part of separation layer.And the first inclination angle Ψ 11
Smaller, the barrier effect that the first direction ion implanting is subject to is smaller.But when the first inclination angle Ψ 11 is 0 °, institute
First direction ion implanting is stated perpendicular to Semiconductor substrate 100, doped region can not be formed in 101 side wall of fin, so described the
One inclination angle Ψ 11 needs to be more than 0, and less than or equal to arctan (s/h), i.e., the injection direction 11 of described first ion implanting
The tangent value of the first inclination angle Ψ 11 between 100 normal of Semiconductor substrate be less than or equal to adjacent fin 101 spacing d with
Ratio between 100 top of fin and the difference in height h on 100 surface of separation layer, and the first inclination angle Ψ 11 is more than 0.
In the present embodiment, the ion energy of the first direction ion implanting is 15KeV~60KeV, and dosage is
1.5E13atom/cm2~3E13atom/cm2.The Doped ions type of the first direction ion implanting and fin to be formed
The type of field-effect transistor is opposite.In the present embodiment, fin formula field effect transistor to be formed is PMOS transistor, described the
One direction ion implanting can be P, As or Sb using n-type doping ion.In other embodiments of the invention, shape is treated
Into fin formula field effect transistor for NMOS transistor, the first direction ion implanting, can be with using p-type Doped ions
It is B, Ga or In.
Fig. 9 is please referred to, second direction ion is carried out to being located at the opposite side of fin 101 of 300 side of gate structure
Injection.Meanwhile 0 is please referred to Fig.1, it is the angle schematic diagram of the second direction ion implanting.The second direction ion implanting
The projection on a semiconductor substrate 100 of injection direction 12 and fin length direction 02 between acute angle be the first torsion angle
α 12 has the first inclination angle between the injection direction 12 of the second direction ion implanting and the normal 03 of Semiconductor substrate 100
Ψ12。
Since the purpose of second ion implanting is the source-drain electrode punch through voltage in order to improve transistor, described second from
Son injection needs to carry out ion implanting between the fin of 300 side of channel region and gate structure below gate structure 300,
It is similar with first direction ion implanting, in the present embodiment, the first torsion of the injection direction 12 of the second direction ion implanting
Angle α 12 is more than 0 °, less than 45 °, can reduce barrier effect of the adjacent fin 101 to the second direction ion implanting.
The first inclination angle between the injection direction 12 of the second direction ion implanting and the normal of Semiconductor substrate 100
Ψ 12 is more than 0, and the tangent value of the first inclination angle Ψ 12 is pushed up less than or equal to the spacing of adjacent fin 101 with fin 100
Ratio between the difference in height on 100 surface of portion and separation layer, to reduce the barrier effect of adjacent fin, so as to make the first party
The fin 101 higher than separation layer 200 is enabled to by ion implanting to ion implanting.
In the present embodiment, the first inclination angle Ψ 12 is identical with 11 sizes of the first inclination angle Ψ, the first torsion angle α
12 is identical with the first torsion angle α 11 so that the injection direction 11 of the first direction ion implanting and second direction ion implanting
Injection direction 12 it is symmetrical about the length direction of fin 101.
In the present embodiment, the ion energy of the second direction ion implanting is 15KeV~60KeV, and dosage is
1.5E13atom/cm2~3E13atom/cm2.The Doped ions type of the second direction ion implanting and fin to be formed
The type of field-effect transistor is opposite.In the present embodiment, fin formula field effect transistor to be formed is PMOS transistor, described the
Two direction ion implantings can be P, As or Sb using n-type doping ion.In other embodiments of the invention, shape is treated
Into fin formula field effect transistor for NMOS transistor, the second direction ion implanting, can be with using p-type Doped ions
It is B, Ga or In.
In other embodiments of the invention, first ion implanting may also be only first direction ion implanting or only
For second direction ion implanting, and pass through annealing, injection ion is made to diffuse to the opposite side of fin.The first ion note
The ion energy entered is 15KeV~60KeV, dosage 3E13atom/cm2~6E13atom/cm2。
After the fin 101 of 300 side of gate structure carries out the first ion implanting, to 300 opposite side of gate structure
Fin 101 carries out the second ion implanting, to form doped region in the fin 101 of 300 opposite side of gate structure.Described second
The injection direction of ion implanting is opposite with gate structure 200, and the injection direction of second ion implanting is served as a contrast in semiconductor
Acute angle between 101 length direction of projection and fin on 100 surface of bottom is the second torsion angle, and second torsion angle is more than
0 ° is less than 45 °.
Due to stereochemical structure of the fin 101 for protrusion, in order to improve the equal of the second ion implanting in the fin
Even property, second ion implanting include：Third direction ion implanting is carried out to the side of fin 101, then to the fin
Opposite side carry out fourth direction ion implanting.
1 is please referred to Fig.1, third direction ion is carried out to being located at the side of fin 101 of 300 opposite side of gate structure
Injection.Meanwhile 2 are please referred to Fig.1, it is the implant angle schematic diagram of the injection direction 21 of the third direction ion implanting.It is described
Acute angle between the projection on a semiconductor substrate 100 of the injection direction 21 of third direction ion implanting and fin length direction 02
Angle is the second torsion angle α 21, the injection direction 21 of the third direction ion implanting and the normal 03 of Semiconductor substrate 100 it
Between have the second inclination angle Ψ 21.
In the present embodiment, second ion implanting injects the drain electrode of 300 opposite side of gate structure.With first party
Identical to the angle requirement of ion implanting, in the present embodiment, the second of the injection direction 21 of the third direction ion implanting turns round
Corner α 21 is more than 0 °, less than 45 °, can reduce barrier effect of the adjacent fin 101 to the third direction ion implanting.
The second inclination angle between the injection direction 21 of the third direction ion implanting and the normal of Semiconductor substrate 100
Ψ 21 is more than 0, and the tangent value of the second inclination angle Ψ 21 is pushed up less than or equal to the spacing of adjacent fin 101 with fin 100
Ratio between the difference in height on 100 surface of portion and separation layer, to reduce the barrier effect of adjacent fin 101, so as to make described
Three direction ion implantings enable to the fin 101 higher than separation layer 200 by ion implanting.
In the present embodiment, the second torsion angle α 21 is identical with 11 sizes of the first torsion angle α, and the second inclination angle Ψ 21
It is identical with 11 sizes of the first inclination angle Ψ.In other embodiments of the invention, the second torsion angle α 21 and the second inclination angle
Ψ 21 or other angles.
In the present embodiment, the ion energy of the third direction ion implanting is 15KeV~60KeV, and dosage is
1.5E13atom/cm2~3E13atom/cm2.The Doped ions type of the third direction ion implanting and fin to be formed
The type of field-effect transistor is opposite.In the present embodiment, fin formula field effect transistor to be formed is PMOS transistor, described the
Three direction ion implantings can be P, As or Sb using n-type doping ion.In other embodiments of the invention, shape is treated
Into fin formula field effect transistor for NMOS transistor, the third direction ion implanting, can be with using p-type Doped ions
It is B, Ga or In.
Please refer to Fig.1 3, to be located at 300 opposite side of gate structure fin 101 opposite side carry out fourth direction from
Son injection.Meanwhile 4 are please referred to Fig.1, it is the implant angle schematic diagram of the injection direction 22 of the fourth direction ion implanting.Institute
It states sharp between the projection on a semiconductor substrate 100 of the injection direction 22 of fourth direction ion implanting and fin length direction 02
Angle angle is the second torsion angle α 22, the injection direction 22 of the fourth direction ion implanting and the normal 03 of Semiconductor substrate 100
Between have the second inclination angle Ψ 22.
In the present embodiment, the second torsion angle α 22 of the injection direction 22 of the fourth direction ion implanting is more than 0 °, is less than
45 °, barrier effect of the adjacent fin 101 to the fourth direction ion implanting can be reduced.
The second inclination angle between the injection direction 22 of the fourth direction ion implanting and the normal of Semiconductor substrate 100
Ψ 22 is more than 0, and the tangent value of the second inclination angle Ψ 22 is pushed up less than or equal to the spacing of adjacent fin 101 with fin 100
Ratio between the difference in height on 100 surface of portion and separation layer, to reduce the barrier effect of adjacent fin 101, so as to make described
Four direction ion implantings enable to the fin 101 higher than separation layer 200 by ion implanting.
In the present embodiment, the second inclination angle Ψ 21 is identical with 22 sizes of the second inclination angle Ψ, the second torsion angle α
21 is identical with the second torsion angle α 22 so that the injection direction 21 of the third direction ion implanting and fourth direction ion implanting
Injection direction 22 it is symmetrical about the length direction of fin 101.
In the present embodiment, the ion energy of the fourth direction ion implanting is 15KeV~60KeV, and dosage is
1.5E13atom/cm2~3E13atom/cm2.The Doped ions type of the fourth direction ion implanting and fin to be formed
The type of field-effect transistor is opposite.In the present embodiment, fin formula field effect transistor to be formed is PMOS transistor, described the
Four direction ion implantings can be P, As or Sb using n-type doping ion.In other embodiments of the invention, shape is treated
Into fin formula field effect transistor for NMOS transistor, the fourth direction ion implanting, can be with using n-type doping ion
It is B, Ga or In.
In other embodiments of the invention, second ion implanting may also be only third direction ion implanting or only
For fourth direction ion implanting, and pass through annealing, injection ion is made to diffuse to the opposite side of fin.The second ion note
The ion energy entered is 15KeV~60KeV, dosage 3E13atom/cm2~6E13atom/cm2。
In the present embodiment, the Doped ions accumulated dose and the Doped ions of the second ion implanting of first ion implanting are total
Dosage is identical, and symmetrical doped region is formed in the fin 101 of 300 both sides of gate structure；In other embodiments of the invention,
Doped ions accumulated dose and the Doped ions accumulated dose of the second ion implanting of first ion implanting can not also be identical, example
The implantation dosage of drain region can such as be made to be more than the implantation dosage of source region, imitated with the improvement improved to Punchthrough phenomenon
Fruit.
It in other embodiments of the invention, can be with before first ion implanting and the second ion implanting is carried out
To the fin 101 of 300 both sides of gate structure be lightly doped ion implanting to improve the short-channel effect of transistor, it is described
The Doped ions type that ion implanting is lightly doped is identical with the type of fin formula field effect transistor to be formed.In its of the present invention
In his embodiment, it can also be carried out after the first ion implanting and the second ion implanting are carried out to the fin 101 described light
Doped ions inject.
Can also subsequently heavy doping ion injection be carried out to the fin 101, be formed positioned at the source of 300 side of gate structure
Pole and the drain electrode positioned at 300 opposite side of gate structure.
The above method during the first ion implanting and the second ion implanting is carried out, can reduce adjacent fin pair
Inject the barrier effect of ion so that there are enough Doped ions in first ion implanting and the second ion implantation process
It can enter between the channel region in fin and source electrode, drain electrode, be formed in the opposite doped region of source electrode, drain implants type,
To improve the performance of fin formula field effect transistor.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of fin formula field effect transistor, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate surface is formed with more than two discrete and arranged in parallel fins；
Separation layer is formed in the semiconductor substrate surface, the insulation surface is less than the top surface and covering fin of fin
Partial sidewall；
The gate structure of one or more fins is developed across in the insulation surface, the gate structure covers the fin
Side wall and top；
The first ion implanting, injection direction and the grid knot of first ion implanting are carried out to gate structure side fin
Structure is opposite, and the injection direction of first ion implanting is between the projection of semiconductor substrate surface and fin length direction
Acute angle for the first torsion angle, first torsion angle is more than 0 ° and is less than 45 °；
Second ion implanting, the injection direction and grid of second ion implanting are carried out to the gate structure opposite side fin
Structure is opposite, and the injection direction of second ion implanting semiconductor substrate surface projection and fin length direction it
Between acute angle for the second torsion angle, second torsion angle is more than 0 ° and is less than 45 °；
The tangent value at the inclination angle between the injection direction of first ion implanting and Semiconductor substrate normal is less than or equal to
Ratio at the top of the spacing and fin of adjacent fin between the difference in height of insulation surface；
The tangent value at the inclination angle between the injection direction of second ion implanting and Semiconductor substrate normal is less than or equal to
Ratio at the top of the spacing and fin of adjacent fin between the difference in height of insulation surface.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first torsion angle
It is identical with the second torsion angle size.
3. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the first ion note
Enter including：First direction ion implanting is carried out to the side of fin, then the opposite side of the fin is carried out second direction from
Son injection.
4. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that the first direction from
The injection direction and the injection direction of second direction ion implanting of son injection are symmetrical about the length direction of fin.
5. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the second ion note
Enter including：Third direction ion implanting is carried out to the side of fin, then the opposite side of the fin is carried out fourth direction from
Son injection.
6. the forming method of fin formula field effect transistor according to claim 5, which is characterized in that the third direction from
The injection direction and the injection direction of fourth direction ion implanting of son injection are symmetrical about the length direction of fin.
7. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the Semiconductor substrate
For wafer, the crystal round fringes have alignment mark, the length of line and fin between the alignment mark and the wafer center of circle
Direction is vertical.
8. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the second ion note
Inclination angle and the injection direction and Semiconductor substrate of the first ion implanting between the injection direction and Semiconductor substrate normal that enter
Inclination angle between normal is identical.
9. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the first ion note
The accumulated dose of the accumulated dose entered and the second ion implanting differs.
10. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first ion
The type of the Doped ions of injection and the second ion implanting is opposite with the type of fin formula field effect transistor to be formed.
11. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first ion
The ion energy of injection is 15KeV~60KeV, dosage 3E13atom/cm2~6E13atom/cm2。
12. the forming method of fin formula field effect transistor according to claim 4, which is characterized in that first direction ion
The ion energy of injection is 15KeV~60KeV, dosage 1.5E13atom/cm2~3E13atom/cm2；Second direction ion is noted
The ion energy entered is 15KeV~60KeV, dosage 1.5E13atom/cm2~3E13atom/cm2。
13. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that second ion
The ion energy of injection is 15KeV~60KeV, dosage 3E13atom/cm2~6E13atom/cm2。
14. the forming method of fin formula field effect transistor according to claim 6, which is characterized in that third direction ion
The ion energy of injection is 15KeV~60KeV, dosage 1.5E13atom/cm2~3E13atom/cm2；Fourth direction ion is noted
The ion energy entered is 15KeV~60KeV, dosage 1.5E13atom/cm2~3E13atom2。
15. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that carrying out described the
Before one ion implanting and the second ion implanting, the fin of the gate structure both sides is carried out that ion implanting is lightly doped, it is described
The Doped ions type that ion implanting is lightly doped is identical with the type of fin formula field effect transistor to be formed.
16. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that carrying out described the
After one ion implanting and the second ion implanting, the fin of the gate structure both sides is carried out that ion implanting is lightly doped, it is described
The Doped ions type that ion implanting is lightly doped is identical with the type of fin formula field effect transistor to be formed.
17. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the fin
After carrying out the first ion implanting and the second ion implanting, heavy doping ion injection is carried out to the fin, is formed and is located at grid
The source electrode of structure side and the drain electrode positioned at gate structure opposite side.
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