US20210151602A1 - Semiconductor structure and fabrication method thereof - Google Patents
Semiconductor structure and fabrication method thereof Download PDFInfo
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- US20210151602A1 US20210151602A1 US17/248,520 US202117248520A US2021151602A1 US 20210151602 A1 US20210151602 A1 US 20210151602A1 US 202117248520 A US202117248520 A US 202117248520A US 2021151602 A1 US2021151602 A1 US 2021151602A1
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Definitions
- the present disclosure generally relates to the field of semiconductor technology and, more particularly, relates to a semiconductor structure and fabrication method thereof.
- FinFET fin field effect transistors
- the gate electrode can control the fin from at least two sides.
- the FinFET has a much stronger gate-to-channel control capability than the planar device, and can well suppress the short-channel effect.
- the FinFET has better compatibility with existing integrated circuit (IC) fabrication processes.
- carrier mobility is one of the main factors that affect the performance of the transistor. Effectively increasing the carrier mobility has become one of focuses of the transistor device manufacturing process. Because stress can change an energy gap and the carrier mobility of a silicon material, the performance of the transistor is commonly improved by forming a stress layer. For example, a stress layer capable of providing tensile stress is formed in an N-type transistor to increase electron mobility, and a stress layer capable of providing compressive stress is formed in a P-type transistor to increase hole mobility.
- the disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.
- One aspect of the present disclosure includes a method for fabricating a semiconductor structure.
- the method includes providing a base substrate, and forming a first stress layer in the base substrate.
- the method also includes forming a gate structure on the base substrate.
- the first stress layer in the base substrate is on both sides of the gate structure.
- the method includes after forming the gate structure, forming an opening in the first stress layer by back-etching the first stress layer. Further, the method includes forming a second stress layer in the opening of the first stress layer.
- the semiconductor structure includes a gate structure on a base substrate, and a first stress layer in the base substrate on both sides of the gate structure.
- the semiconductor structure also includes a second stress layer in the first stress layer and surrounded by the first stress layer.
- FIGS. 1-2 illustrate semiconductor structures corresponding to certain stages for forming a semiconductor structure
- FIGS. 3-17 illustrate semiconductor structures corresponding to certain stages for forming an exemplary semiconductor structure consistent with various disclosed embodiments of the present disclosure.
- FIG. 18 illustrates an exemplary fabrication method for forming a semiconductor structure consistent with various disclosed embodiments of the present disclosure.
- FIGS. 1-2 illustrate semiconductor structures corresponding to certain stages for forming the semiconductor structure.
- a substrate 11 is provided, and a plurality of discrete fins 12 are formed on the substrate 11 .
- a gate structure 13 is formed on the fin 12 , and the gate structure 13 is across a length portion of the fin 12 and covers a portion of each of a top surface and a sidewall of the fin 12 .
- a stress layer 14 is formed in the fins 12 on both sides of the gate structure 13 .
- An ion implantation process is performed on the stress layer 14 by an in-situ self-doping method.
- the gate structure 13 is a dummy gate structure.
- an interlayer dielectric layer 15 is formed on the substrate 11 .
- the interlayer dielectric layer 15 exposes the dummy gate structure.
- the dummy gate structure is removed to form a gate opening (not illustrated) in the interlayer dielectric layer 15 .
- a metal gate structure 16 is formed in the gate opening.
- the activation of doping ions in the stress layer 14 and the formation of the metal gate structure 16 are accompanied by the use of many thermal processes. Therefore, a thermal budget of the subsequent processes after forming the stress layer 14 is high. The high thermal budget will cause the stress layer 14 a stress-released issue, and affect the performance of the formed semiconductor structure.
- the size of the stress layer 14 keeps decreasing.
- a doping concentration of the stress layer 14 keeps increasing. The increasing of the doping concentration of the stress layer 14 will enhance the short-channel effect of the formed semiconductor structure, and, thus, affect the performance of the formed semiconductor structure.
- the reduction of the size of the stress layer 14 will cause the stress layer 14 to reduce the stress applied on the channel of the formed semiconductor structure. Therefore, the mobility of carriers in the channel decreases, and the performance of the formed semiconductor structure degrades.
- a first stress layer and a second stress layer may be formed before and after forming a gate structure, respectively.
- the first stress layer and the second stress layer may form a source and drain doped region of the semiconductor structure.
- the second stress layer may be formed after forming the gate structure, thereby the influence of the formation process of the gate structure on the second stress layer may be reduced, and the probability of the occurrence of a stress-released issue in the second stress layer may be effectively reduced, facilitating improving the performance of the formed semiconductor structure.
- FIG. 18 illustrates an exemplary fabrication method for forming a semiconductor structure consistent with various disclosed embodiments of the present disclosure
- FIGS. 3-17 illustrate semiconductor structures corresponding to certain stages of the exemplary fabrication method.
- a base substrate 100 may be formed, and a gate structure 160 (illustrated in FIG. 11 ) may be formed on the base substrate 100 .
- a first stress layer 141 (illustrated in FIG. 11 ) may be formed in the base substrate 100 on both sides of the gate structure 160 .
- FIG. 18 at the beginning of the fabrication method, a base substrate with certain structures may be formed (S 101 ).
- FIG. 3 illustrates a corresponding semiconductor structure.
- a base substrate 100 may be formed.
- the base substrate 100 may provide an operation platform for subsequent processes.
- the formed semiconductor structure may include a fin structure, and the base substrate 100 may include a substrate 110 and a plurality of discrete fins 120 on the substrate 110 .
- the formed semiconductor structure may include a planar structure, and the base substrate may include a planar substrate.
- the substrate 110 may provide an operation platform for subsequent processes.
- a channel of the formed semiconductor structure may be located in the fin 120 .
- the substrate 110 may be made of monocrystalline silicon.
- the substrate may be made of polysilicon, amorphous silicon, amorphous germanium, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc.
- the substrate may be made of a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, a glass substrate, and other types of substrates.
- SOI silicon on insulator
- GOI germanium on insulator
- the substrate may be made of materials adapted to process requirements and easy integration.
- the fin 120 may be made of a same material as the substrate 110 . Both the fin 120 and the substrate 110 may be made of monocrystalline silicon. In another embodiment, the fin may be made of a material different from the substrate. The fin may be made of amorphous germanium, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc.
- the substrate 110 and the fin 120 may be formed at the same time. Forming the substrate 110 and the fin 120 may include: providing an initial substrate; forming a patterned fin mask layer 121 on a surface of the initial substrate; and etching the initial substrate using the fin mask layer 121 as a mask to remove portions of the initial substrate, thereby the substrate 110 and the fin 120 protruding on the substrate 110 may be formed. In one embodiment, after forming the substrate 110 and the fin 120 , the fin mask layer 121 may be retained to protect a top of the fin 120 . In another embodiment, after forming the substrate and the fin, the fin mask layer may be removed to expose the top of the fin.
- a liner oxide layer 122 may be formed on the surface of the substrate 110 and the sidewall of the fin 120 .
- the liner oxide layer 122 may smooth sharp corners on the surface of the substrate 110 and the sidewall of the fin 120 , and act as a buffer layer between the subsequently formed film layer and the substrate 110 and the fin 120 to reduce the lattice mismatch thereof.
- the liner oxide layer 122 may be formed by a chemical vapor deposition process, or a thermal oxidation process, etc. In certain embodiments, the liner oxide layer may not be formed. The damages may be repaired by performing an annealing process on the substrate 110 and the fin 120 .
- FIGS. 4-5 illustrate corresponding semiconductor structures.
- an isolation layer 124 may be formed to fill a gap between adjacent fins 120 .
- the isolation layer 124 may cover a portion of the sidewall of the fin 120 , and a top of the isolation layer 124 may be lower than the top of the fin 120 .
- the isolation layer as an isolation structure of the semiconductor structure, may electrically isolate adjacent devices and the adjacent fins.
- the isolation layer 124 may be formed on the substrate 110 exposed by the fin 120 , and a height of the isolation layer 124 may be lower than a height of the fin 120 .
- the isolation layer may be made of silicon oxide.
- the isolation layer may be made of silicon nitride, silicon oxynitride, or other suitable insulating material(s).
- forming the isolation layer 124 may include: forming an isolation material layer 123 (illustrated in FIG. 4 ) on the substrate 110 exposed by the fin 120 , where the isolation material layer 123 may cover the top of the fin 120 ; removing the isolation material layer 123 above the top of the fin 120 by polishing; and removing a portion of the remaining isolation material layer along a thickness direction of the isolation material layer by back-etching to expose the top and a portion of the sidewall of the fin 120 , thereby the isolation layer 124 may be formed.
- the fin mask layer 121 illustrated in FIG. 3
- the fin mask layer 121 may protect the top of the fin 120 during the back-etching process.
- the fin mask layer 121 may be removed to expose the top of the fin 120 .
- the gate structure 160 may be a gate structure of the formed semiconductor structure, and may be used to control turned-on and turned-off of the channel of the formed semiconductor structure.
- the first stress layer 141 may be used as a portion of a source and drain doped region of the formed semiconductor structure, and may provide stress on the channel of the formed semiconductor structure to increase mobility of carriers in the channel.
- the formed semiconductor structure may include a metal gate structure. That is, the gate structure 160 may be a metal gate structure.
- the gate structure 160 may include a gate dielectric layer and a metal gate electrode.
- the gate structure may be a polysilicon gate structure or other gate structures.
- forming the first stress layer 141 (illustrated in FIG. 8 ) and the gate structure 160 (illustrated in FIG. 11 ) may include forming a dummy gate structure 130 on the base substrate 100 after forming the base substrate 100 ; forming the first stress layer 141 in the base substrate 100 on both sides of the dummy gate structure 130 ; forming a first dielectric layer 151 after forming the first stress layer 141 , where the first dielectric layer 151 may expose the dummy gate structure 130 ; forming a gate opening 161 (illustrated in FIG. 10 ) in the first dielectric layer 151 by removing the dummy gate structure 130 (illustrated in FIG. 9 ), and forming the metal gate structure (illustrated in FIG. 11 ) in the gate opening 161 .
- FIGS. 6-7 illustrate corresponding semiconductor structures.
- a dummy gate structure 130 may be formed on the base substrate 100 .
- the dummy gate structure 130 may occupy a space for subsequently forming a metal gate structure.
- the base substrate 100 may include the substrate 110 and the fin 120 . Therefore, the dummy gate structure 130 may be across a length portion of the fin 120 and cover a portion of each of the top surface and the sidewall of the fin 120 .
- the dummy gate structure 130 may be a stacked-layer structure.
- the dummy gate structure 130 may include a dummy oxide layer 1301 and a dummy gate layer 1302 on the dummy oxide layer 1301 .
- the dummy gate structure may be a single-layer structure.
- the dummy gate structure may include the dummy gate layer.
- the dummy oxide layer 1301 may be made of silicon oxide. In another embodiment, the dummy oxide layer may be made of silicon oxynitride. In one embodiment, the dummy gate layer 1302 may be made of polysilicon. In another embodiment, the dummy gate layer may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon, etc.
- forming the dummy gate structure 130 may include: forming an oxide material layer 125 (illustrated in FIG. 6 ) on the surface of the fin 120 exposed by the isolation layer 124 ; forming a dummy gate material layer (not illustrated) on the oxide material layer 125 ; forming a patterned gate mask 131 on a surface of the dummy gate material layer; and etching the dummy gate material layer until the oxide material layer 125 is exposed by using the patterned gate mask 131 as a mask to form the dummy gate layer 1302 on the oxide material layer 125 .
- the dummy gate layer 1302 may be across the length portion of the fin 120 and cover a portion of each of the top surface and the sidewall of the fin 120 .
- Forming the dummy gate structure 130 may also include removing the oxide material layer 125 exposed by the dummy gate layer 1302 to expose the surface of the fin 120 .
- the remaining oxide material layer 125 covered by the dummy gate layer 1302 may be used as the dummy oxide layer 1301 .
- the dummy oxide layer 1301 may be across the length portion of the fin 120 and cover a portion of each of the top surface and the sidewall of the fin 120 .
- the gate mask 131 on the top of the dummy gate structure 130 may be retained.
- the gate mask 131 may be made of silicon nitride.
- the gate mask 131 may be made of silicon oxynitride, silicon carbide, or boron nitride, etc. The gate mask 131 may protect the top of the dummy gate structure 130 during subsequent processes.
- a sidewall spacer 132 may be formed on the sidewall of the dummy gate structure 130 .
- the sidewall spacer 132 may protect the dummy gate structure 130 and define a position of a subsequently formed source and drain doped region.
- the sidewall spacer 132 may be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, etc.
- the sidewall spacer may be a single-layer structure, or a stacked-layer structure. In one embodiment, the sidewall spacer 132 may be a single-layer structure, and may be made of silicon nitride.
- FIG. 8 illustrates a corresponding semiconductor structure.
- a first stress layer 141 may be formed in the base substrate 100 on both sides of the dummy gate structure 130 .
- the first stress layer 141 may be used as a portion of the source and drain doped region of the formed semiconductor structure.
- the formed semiconductor structure may be used to form an NMOS device, thus, the stress layer 141 may be an N-type doped stress layer.
- the first stress layer 141 may be made of N-type doped silicon carbon or silicon.
- the dopant ions in the first stress layer 141 may be N-type ions, such as P, As, or Sb, etc.
- the formed semiconductor structure may be used to form a PMOS device, or a CMOS device.
- the first stress layer may be made of P-type doped silicon germanium or silicon.
- the dopant ions in the first stress layer may be P-type ions, such as B, Ga, or In, etc.
- the material and doped type of the first stress layer may be different according to different types of the semiconductor structure.
- the base substrate 100 may include the substrate 110 and the fin 120 .
- the first stress layer 141 may be formed in the fin 120 on both sides of the dummy gate structure 130 . Therefore, forming the first stress layer 141 may include forming the first stress layer 141 in the fin 120 on both sides of the dummy gate structure 130 .
- the first stress layer 141 may be disposed adjacent to the dummy gate structure 130 .
- the sidewall spacer 132 may be formed on the sidewall of the dummy gate structure 130 , such that the first stress layer 141 may be in contact with the sidewall spacer 132 .
- forming the first stress layer 141 may include forming openings (not illustrated) in the fin 120 on both sides of the dummy gate structure 130 ; and forming the first stress layer 141 in the openings by an epitaxial growth process, where an in-situ self-doping may be performed during the epitaxial growth of the first stress layer 141 .
- the formed semiconductor structure may be used to form an NMOS device, the in-situ self-doped dopant ions may be P ions, and a doping concentration may be in a range of approximately 8.0 ⁇ 10 20 atoms/cm 3 -2.5 ⁇ 10 21 atoms/cm 3 .
- the formed semiconductor structure may be used to form a PMOS device, and the in-situ self-doped dopant ions may be B ions, and a doping concentration may be in a range of approximately 2.0 ⁇ 10 20 atoms/cm 3 -1.5 ⁇ 10 21 atoms/cm 3 .
- FIG. 9 illustrates a corresponding semiconductor structure.
- a first dielectric layer 151 may be formed on the base substrate 100 .
- the first dielectric layer 151 may expose the top of the dummy gate structure 130 .
- the first dielectric layer 151 as a portion of an interlayer dielectric layer, may electrically isolate adjacent semiconductor structures.
- the first dielectric layer 151 may be made of silicon oxide. In another embodiment, the first dielectric layer 151 may be made of silicon nitride, silicon oxynitride, or other suitable insulating material(s).
- Forming the first dielectric layer 151 may include: forming a dielectric material layer (not illustrated) on the substrate 110 exposed by the dummy gate structure 130 , where the dielectric material layer may cover the dummy gate structure 130 ; removing the dielectric material layer above the dummy gate structure 130 by polishing, thereby the first dielectric layer 151 may be formed; and removing the gate mask 131 to expose the top of the dummy gate structure 130 .
- FIG. 10 illustrates a corresponding semiconductor structure.
- a gate opening 161 may be formed in the first dielectric layer 151 by removing the dummy gate structure 130 (illustrated in FIG. 9 ).
- the gate opening 161 may provide a process space for the formation of a metal gate structure.
- the base substrate 100 may include the substrate 110 and the fin 120 .
- the dummy gate structure 130 may be across the length portion of the fin 120 and cover a portion of each of the top surface and the sidewall of the fin 120 . Therefore, a bottom of the gate opening 161 may expose a portion of each of the top surface and the sidewall of the fin 120 .
- FIG. 11 illustrates a corresponding semiconductor structure.
- a gate structure 160 may be formed in the gate opening 161 (illustrated in FIG. 10 ).
- the gate structure 160 may include a gate dielectric layer (not illustrated) and a metal gate electrode (not illustrated) on the gate dielectric layer.
- Forming the gate structure 160 in the gate opening 161 may include: forming the gate dielectric layer on the base substrate 100 exposed at the bottom of the gate opening 161 , and forming the metal gate electrode on the gate dielectric layer.
- the gate dielectric layer may electrically isolate the gate structure 160 and the channel in the base substrate 100 .
- the gate dielectric layer may be made of a high-K dielectric material, where the high-K dielectric material may be referred to a dielectric material having a relative dielectric constant greater than silicon oxide.
- the gate dielectric layer may be made of HfO 2 .
- the gate dielectric layer may be made of ZrO 2 , HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, or Al 2 O 3 , etc.
- the bottom of the gate opening 161 may exposes a portion of each of the top surface and the sidewall of the fin 120 .
- the gate dielectric layer may be across the length portion of the fin 120 and on a portion of each of the top surface and the sidewall of the fin 120 .
- the gate dielectric layer may be formed by an atomic layer deposition process.
- the gate dielectric layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, or other film deposition processes.
- the metal gate electrode may be configured as an electrode to achieve electrical connection to an external circuit.
- the metal gate electrode may be made of W.
- the metal gate electrode may be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.
- a high-K last metal gate last process sequence is described for illustrative purposes. In certain embodiments, a high-K first metal gate last process sequence, or a high-K first metal gate first process sequence may be used.
- FIGS. 12-13 illustrate corresponding semiconductor structures.
- an opening 143 may be formed in the first stress layer 141 by back-etching the first stress layer 141 .
- an interlayer dielectric layer may be formed on the base substrate 100 . Therefore, referring to FIG. 12 , before performing the back-etching process, a second dielectric layer 152 may be formed on the first dielectric layer 151 . The second dielectric layer 152 may cover the gate structure 160 . The second dielectric layer 152 , as a portion of the interlayer dielectric layer, may be used together with the first dielectric layer 151 to electrically isolate different semiconductor structures.
- the second dielectric layer 152 may be made of silicon oxide.
- the second dielectric layer may be made of silicon nitride, silicon oxynitride, or other suitable insulating material(s).
- Forming the opening 143 may include: referring to FIG. 12 , forming a contact hole 181 in the interlayer dielectric layer, where a bottom of the contact hole may expose the first stress layer 141 ; and referring to FIG. 13 , back-etching the first stress layer 141 along the contact hole 181 to form the opening 143 .
- the contact hole 181 may expose the first stress layer 141 , and provide a process operation space for the formation of the opening 143 and a subsequent second stress layer. In one embodiment, the contact hole 181 may also provide a process space for the subsequent formation of a plug.
- the interlayer dielectric layer may include the first dielectric layer 151 and the second dielectric layer 152 , thus, the contact hole 181 may penetrate through the first dielectric layer 151 and the second dielectric layer 152 .
- the contact hole 181 may be formed by a dry etching process.
- the dry etching process may have strong anisotropic characteristics, effectively reduce the loss of the interlayer dielectric layer, and improve the quality of the contact hole 181 .
- a contact etch stop layer (CESL) (not illustrated) may be formed.
- the contact etch stop layer may cover the base substrate 100 , the first stress layer 141 , and the gate structure 160 .
- the contact etch stop layer may protect the first stress layer 141 and the gate structure 160 from adverse effects caused by the formation process of the contact hole 181 .
- the contact etch stop layer may be made of silicon nitride.
- Forming the contact hole 181 may include: forming the contact hole 181 to penetrate through the interlayer dielectric layer by a dry etching process, where the bottom of the contact hole 181 may expose the contact etch stop layer on the first stress layer 141 ; and removing the exposed contact etch stop layer to expose the first stress layer 141 at the bottom of the contact hole 181 .
- the process of back-etching the first stress layer 141 may be used to remove a portion of the first stress layer 141 , thereby the first stress layer 141 affected by the fabrication process of the gate structure 160 may be removed. Moreover, the process of back-etching the first stress layer 141 may form the opening 143 in the first stress layer 141 , thereby providing a process space for the subsequent formation of a second stress layer.
- Forming the opening 143 by performing the back-etching process through the contact hole 181 may reduce the process steps for forming the semiconductor structure, reduce the number of times of photolithography process, and avoid alignment issues of the fore and post lithography processes, thereby facilitating improving the performance and yield of the formed semiconductor structure.
- the first stress layer 141 may be back-etched through a dry etching process. That is, a portion of the first stress layer 141 exposed at the bottom of the contact hole 180 may be removed by a dry etching process along the contact hole 180 (illustrated in FIG. 12 ) to form the opening 143 in the first stress layer 141 .
- the opening 143 may be used to subsequently form the second stress layer, thus, the size of the opening 143 may be related to the size of the subsequently formed second stress layer. Therefore, a depth of the opening 143 cannot be too small or too large.
- the depth of the opening 143 is too large, the amount of the removed first stress layer 141 may be too large, thus, a volume of the second stress layer subsequently formed in the opening 143 may be substantially large, and a depth of the formed second stress layer may be too large. Therefore, a distance between the formed second stress layer and the channel of the formed semiconductor structure may be too small, causing the short-channel effect to be easily deteriorated, and an excessive leakage current issue may be likely to occur. If the depth of the opening 143 is too small, the amount of the removed first stress layer 141 may be too small, and the volume of the second stress layer subsequently formed in the opening 143 may be too small. Therefore, the effect of the formed second stress layer exerting stress on the channel of the formed semiconductor structure may not be effectively increased, the mobility of carriers in the channel may not be effectively improved, and the performance of the formed semiconductor structure may not be effectively improved.
- a ratio of the depth of the opening 143 over an entire thickness of the first stress layer 141 may be in a range of approximately 1 ⁇ 3-2 ⁇ 3. That is, in a direction perpendicular to the surface of the substrate 110 , the ratio of the size of the opening 143 over the size of the first stress layer 141 may be in a range of approximately 1 ⁇ 3-2 ⁇ 3.
- Process parameters of the back-etching process may be selected within a reasonable range.
- the thickness of the removed first stress layer 141 may be controlled, and, thus, the depth of the opening 143 may be controlled to enable the depth of the opening 143 to meet design requirements.
- FIG. 14 illustrates a corresponding semiconductor structure.
- an anti-leakage doped region 170 may be formed in the base substrate 100 under the first stress layer 141 by performing an anti-leakage implantation 171 along the opening 143 (illustrated in FIG. 13 ).
- the anti-leakage implantation 171 may be used to implant dopant ions into the base substrate 100 under the first stress layer 141 , thus, the anti-leakage doped region 170 may be formed.
- the anti-leakage doped region 170 may be used to suppress the leakage current of the formed semiconductor structure.
- the anti-leakage implantation 171 may be performed along the opening 143 (illustrated in FIG. 13 ) to form the anti-leakage doped region 170 in the base substrate 100 under the first stress layer 141 . Because the opening 143 is disposed within the first stress layer 141 , by performing the anti-leakage implantation 171 along the opening 143 , an energy of the anti-leakage implantation 171 may be effectively reduced, and the influence of the anti-leakage implantation 171 on other semiconductor structures may be reduced, facilitating improving the performance of the formed semiconductor structure.
- the base substrate 100 may include the substrate 110 and the fin 120 , thus, the anti-leakage doped region 170 may be located in the fin 120 under the first stress layer 141 .
- the openings 143 may be located at the bottom of the contact hole 181 (illustrated in FIG. 12 ), and may be through-connected to the contact hole 181 .
- the contact hole 181 may penetrate through the first dielectric layer 151 and the second dielectric layer 152 .
- the anti-leakage implantation 171 is performed along the contact hole 181 and the opening 143 , the energy required for the anti-leakage implantation 171 may be effectively reduced, and the damages on the first stress layer 141 and the fin 120 caused by the anti-leakage implantation 171 may be reduced, thereby facilitating improving the performance of the formed semiconductor structure.
- process parameters of the anti-leakage implantation 171 may include the following.
- Implanted ions may be P ions
- an implantation energy may be in a range of approximately 2 KeV-20 KeV
- an implantation dose may be in a range of approximately 2.0 ⁇ 10 14 atoms/cm 3 -5.0 ⁇ 10 15 atoms/cm 3 .
- the process parameters of the anti-leakage implantation 171 may include the following.
- Implanted ions may be B ions or BF 2 ions, an implantation energy may be in a range of approximately 2 KeV-20 KeV, and an implantation dose may be in a range of approximately 2.0 ⁇ 10 13 atoms/cm 3 -3.0 ⁇ 10 15 atoms/cm 3 .
- FIG. 15 illustrates a corresponding semiconductor structure.
- an activation annealing 172 may be performed on the anti-leakage doped region 170 .
- the activation annealing 172 may be used to enable the dopant ions to relax to positions of the lattices, and, thus, to be activated.
- the activation annealing 172 may be a spike annealing process at an annealing temperature in a range of approximately 950° C.-1050° C. In another embodiment, the activation annealing may be a laser annealing process at an annealing temperature in a range of approximately 1150° C.-1350° C. The annealing temperature of the activation annealing 172 cannot be too high nor too low.
- the thermal budget may be too high and may cause adverse effects on the remaining first stress layer 141 , thus, a stress-released issue of the remaining first stress layer 141 may be likely to occur, and the dopant ions in the first stress layer 141 may diffuse to cause the deterioration of the short-channel effect.
- the annealing temperature of the activation annealing 172 is too low, the activation of the dopant ions in the anti-leakage doped region 170 may be affected, and, thus, the leakage current suppression function of the anti-leakage doped region 170 may be affected to degrade the performance of the formed semiconductor structure.
- FIG. 16 illustrates a corresponding semiconductor structure.
- a second stress layer 142 may be formed in the opening 143 (illustrated in FIG. 13 ).
- the second stress layer 142 may be used as a portion of the source and drain doped region of the formed semiconductor structure, and together with the first stress layer 141 , may exert a stress to the channel of the formed semiconductor structure, to increase the carrier mobility in the channel.
- the second stress layer 142 may be formed after forming the gate structure 160 .
- the gate structure 160 may be a metal gate structure, and the formation process of the metal gate structure may include multiple thermal processes, such that the thermal budget of the formation process of the gate structure 160 may be large. Therefore, by forming the second stress layer 142 after forming the gate structure 160 , the influence of the formation process of the gate structure 160 on the second stress layer 142 may be effectively reduced. In particular, the second stress layer 142 may not be affected by the thermal process during the formation of the gate structure 160 , and the probability of the occurrence of the stress-released issue of the second stress layer 142 may be effectively reduced. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved.
- the anti-leakage doped region 170 may be formed and the activation annealing may be performed. Therefore, thermal budget of the second stress layer 142 may be effectively reduced, facilitating reducing the probability of the occurrence of the stress-released issue of the second stress layer 142 , and improving the performance of the formed semiconductor structure.
- the formed semiconductor structure may be used to form an NMOS device
- the second stress layer 142 may be made of carbon silicon for exerting tensile stress on the channel of the formed semiconductor structure.
- the first stress layer 141 may be made of carbon silicon or silicon
- the content of carbon in the second stress layer 142 may be greater than or equal to the content of carbon in the first stress layer 141 .
- the stress layer may exert stress on the channel of the formed semiconductor structure through a principle of lattice mismatch, because the content of carbon in the second stress layer 142 is higher, the second stress layer 142 may exert a greater stress on the channel of the formed semiconductor structure. Therefore, the mobility of carriers in the channel of the formed semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure.
- the formed semiconductor structure may be used to form an NMOS device, the first stress layer 141 may be made of carbon silicon or silicon, and the second stress layer 142 may be made of carbon silicon.
- the first stress layer may be made of silicon germanium or silicon, and the second stress layer may be made of silicon germanium.
- the second stress layer may be made of silicon germanium, and the content of germanium in the second stress layer may be greater than or equal to the content of germanium in the first stress layer. Therefore, the second stress layer may exert a greater stress on the channel of the formed semiconductor structure to improve the performance of the formed semiconductor structure.
- the second stress layer 142 may be a doped stress layer, and a doping type of the second stress layer 142 may be the same as a doping type of the first stress layer 141 .
- the formed semiconductor structure may be used to form an NMOS device, and the first stress layer 141 may be an N-type doped stress layer, thus, the second stress layer 142 may be made of N-type doped carbon silicon or silicon.
- the dopant ions in the second stress layer 142 may be N-type ions, such as P, As, or Sb, etc.
- a doping concentration of the second stress layer 142 may be greater than or equal to a doping concentration of the first stress layer 141 .
- Use of the second stress layer 142 having the doping concentration greater than or equal to the first stress layer 141 may effectively reduce a contact resistance between a subsequently formed plug and the second stress layer 142 .
- the second stress layer 142 may be located in the opening 143 , and the opening 143 may be located in the first stress layer 141 . That is, the second stress layer 142 may be located in the first stress layer 141 . In other words, in a plane parallel to the surface of the substrate 110 , the first stress layer 141 may surround the second stress layer 142 . Therefore, a portion of the first stress layer 141 may be disposed between the channel of the formed semiconductor structure and the second stress layer 142 , and the second stress layer 142 may be spaced a certain distance from the channel of the semiconductor structure. Therefore, the second stress layer 142 with a substantially large doping concentration may be prevented from causing a deterioration of the short-channel effect.
- the formation of the second stress layer 142 with a substantially large doping concentration may reduce the contact resistance between the plug and the second stress layer 142 , facilitating improving the performance of the formed semiconductor structure.
- forming the second stress layer 142 may include forming the second stress layer 142 in the opening 143 by an epitaxial growth process, where an in-situ self-doping process may be performed during the epitaxial growth of the second stress layer 142 .
- the formed semiconductor structure may be used to form an NMOS device, in-situ self-doped dopant ions may be P ions, and a doping concentration may be in a range of approximately 8.0 ⁇ 10 20 atoms/cm 3 -2.5 ⁇ 10 21 atoms/cm 3 .
- the formed semiconductor structure may be used to form a PMOS device, and the in-situ self-doped dopant ions may be B ions, and a doping concentration may be in a range of approximately 2.0 ⁇ 10 20 atoms/cm 3 -1.5 ⁇ 10 21 atoms/cm 3 .
- FIG. 17 illustrates a corresponding semiconductor structure.
- a plug 180 may be formed in the contact hole 181 (illustrated in FIG. 16 ).
- the plug 180 may be used to electrically connect the source and drain doped region of the formed semiconductor structure to an external circuit.
- the plug 180 may be made of tungsten.
- the source and drain doped region may include the first stress layer 141 and the second stress layer 142 , and, thus, the plug 180 may be disposed on the second stress layer 142 and penetrate through the first dielectric layer 151 and the second dielectric layer 152 over the second stress layer 142 .
- forming the plug 180 may include filling the contact hole 181 with a conductive material, where the conductive material may cover the second dielectric layer 152 ; and removing the conductive material above the second dielectric layer 152 to form the plug 180 .
- the opening may be formed in the first stress layer, and the second stress layer may be formed in the opening.
- the first stress layer and the second stress layer may together form the source and drain doped region of the semiconductor structure.
- Forming the second stress layer after forming the gate structure may effectively reduce the influence of the formation process of the gate structure on the second stress layer and the probability of the occurrence of the stress-released issue of the second stress layer. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved.
- the gate structure may be the metal gate structure.
- the dummy gate structure Before forming the first stress layer, the dummy gate structure may be formed on the base substrate. After forming the first stress layer and before forming the opening, the dummy gate structure may be removed, and the metal gate structure may be formed in the position where the dummy gate structure is previously located. Therefore, the opening and the second stress layer may be formed after forming the metal gate structure.
- the formation process of the opening may remove a portion of the first stress layer, thereby a portion of the first stress layer having a degraded performance may be removed.
- the second stress layer reformed in the opening may not be subject to the influence of the formation process of the metal gate structure, and, thus, may have desired performance. Therefore, the source and drain doped region formed by the second stress layer and the first stress layer may have desired performance, and may facilitate improving the performance of the formed semiconductor structure.
- the second stress layer When the second stress layer is made of silicon germanium, the content of germanium in the second stress layer may be greater than or equal to the content of germanium in the first stress layer.
- the second stress layer When the second stress layer is made of silicon carbon, the content of carbon in the second stress layer may be greater than or equal to the content of carbon in the first stress layer. Accordingly, the second stress layer may exert a greater stress on the channel of the formed semiconductor structure. Therefore, the mobility of carriers in the channel of the semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure.
- the doping concentration of the second stress layer may be greater than or equal to the doping concentration of the first stress layer. Accordingly, the contact resistance between the plug and the second stress layer may be effectively reduced.
- the second stress layer may be disposed in the first stress layer. In other words, a portion of the first stress layer may be disposed between the channel of the semiconductor structure and the second stress layer, and the second stress layer may be spaced a certain distance from the channel of the semiconductor structure. Therefore, the second stress layer with a substantially large doping concentration may be prevented from causing a deterioration of the short-channel effect. Therefore, under the premise of controlling the short-channel effect, the formation of the second stress layer with a substantially large doping concentration may reduce the contact resistance between the plug and the second stress layer, facilitating improving the performance of the semiconductor structure.
- the anti-leakage doped region may be formed in the base substrate under the first stress layer by performing the anti-leakage implantation along the opening. Because the opening is disposed in the first stress layer, by performing the anti-leakage implantation along the opening, the energy of the anti-leakage implantation may be effectively reduced, and the influence of the anti-leakage implantation on other semiconductor structures may be reduced, facilitating improving the performance of the formed semiconductor structure.
- the second stress layer may be formed after performing the anti-leakage implantation and the activation annealing, the thermal budget of the second stress layer may be effectively reduced, facilitating reducing the probability of the occurrence of the stress-released issue of the second stress layer, and improving the performance of the formed semiconductor structure.
- FIG. 17 illustrates a cross-sectional view of an exemplary semiconductor structure consistent with various disclosed embodiments of the present disclosure.
- the semiconductor structure may include a base substrate 100 , a gate structure 160 on the base substrate 100 , a first stress layer 141 in the base substrate 100 on both sides of the gate structure 160 , and a second stress layer 142 in the first stress layer 141 .
- the second stress layer 142 may be formed after forming the gate structure 160 .
- the second stress layer 142 may be located in the first stress layer 141 .
- the first stress layer 141 together with the second stress layer 142 may form a source and drain doped region of the semiconductor structure. Because the second stress layer 142 is formed after forming the gate structure 162 , the influence of the formation process of the gate structure 160 on the second stress layer 142 may be effectively reduced, and the probability of the occurrence of the stress-released issue of the second stress layer 142 may be effectively reduced. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved.
- the semiconductor structure may include a metal gate structure. That is, the gate structure 160 may be the metal gate structure.
- the formed semiconductor structure may be used to form an NMOS device, thus, the first stress layer 141 may be an N-type doped stress layer.
- the first stress layer 141 may be made of N-type doped carbon silicon or silicon.
- the dopant ions in the first stress layer 141 may be N-type ions, such as P, As, or Sb, etc.
- the second stress layer 142 may be used as a portion of the source and drain doped region of the formed semiconductor structure, and together with the first stress layer 141 , may exert a stress to the channel of the formed semiconductor structure, to improve the carrier mobility in the channel.
- the second stress layer 142 may be formed after forming the gate structure 160 .
- the gate structure 160 may be the metal gate structure, and the formation process of the metal gate structure may include multiple thermal processes, such that the thermal budget of the formation process of the gate structure 160 may be large. Therefore, by forming the second stress layer 142 after forming the gate structure 160 , the influence of the formation process of the gate structure 160 on the second stress layer 142 may be effectively reduced. In particular, the second stress layer 142 may not be affected by the thermal process during the formation of the gate structure 160 , and the probability of the occurrence of the stress-released issue of the second stress layer 142 may be effectively reduced. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved.
- the semiconductor structure may be used to form an NMOS device
- the second stress layer 142 may be made of carbon silicon for exerting tensile stress on the channel of the semiconductor structure.
- the first stress layer 141 may be made of carbon silicon or silicon.
- the content of carbon in the second stress layer 142 may be greater than or equal to the content of carbon in the first stress layer 141 .
- the stress layer may exert stress on the channel of the semiconductor structure through a principle of lattice mismatch, because the content of carbon in the second stress layer 142 is higher, the second stress layer 142 may exert a greater stress on the channel of the semiconductor structure. Therefore, the mobility of carriers in the channel of the semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure.
- the semiconductor structure may be used to form an NMOS device, the first stress layer 141 may be made of carbon silicon or silicon, and the second stress layer 142 may be made of carbon silicon.
- the first stress layer may be made of silicon germanium or silicon, and the second stress layer may be made of silicon germanium.
- the second stress layer may be made of silicon germanium, and the content of germanium in the second stress layer may be greater than or equal to the content of germanium in the first stress layer. Therefore, the second stress layer may exert a greater stress on the channel of the formed semiconductor structure to improve the performance of the semiconductor structure.
- the second stress layer 142 may be a doped stress layer, and a doping type of the second stress layer 142 may be the same as a doping type of the first stress layer 141 .
- the semiconductor structure may be used to form an NMOS device, and the first stress layer 141 may be an N-type doped stress layer, thus, the second stress layer 142 may be made of N-type doped carbon silicon.
- the dopant ions in the second stress layer 142 may be N-type ions, such as P, As, or Sb, etc.
- a doping concentration of the second stress layer 142 may be greater than or equal to a doping concentration of the first stress layer 141 .
- Use of the second stress layer 142 having a doping concentration greater than or equal to the first stress layer 141 may effectively reduce a contact resistance between a subsequently formed plug and the second stress layer 142 .
- the second stress layer 142 may be located in the first stress layer 141 .
- the first stress layer 141 may surround the second stress layer 142 . Therefore, a portion of the first stress layer 141 may be disposed between the channel of the semiconductor structure and the second stress layer 142 , and the second stress layer 142 may be spaced apart by a certain distance from the channel of the semiconductor structure. Therefore, the second stress layer 142 with a substantially large doping concentration may be prevented from causing a deterioration of the short-channel effect.
- the formation of the second stress layer 142 with a substantially large doping concentration may reduce the contact resistance between the plug and the second stress layer 142 , facilitating improving the performance of the semiconductor structure.
- the semiconductor structure may be formed by the disclosed fabrication method of a semiconductor structure. Therefore, the detailed technical solution of the semiconductor structure may be referred to various embodiments of the present disclosure for forming a semiconductor structure, and is not repeated herein.
- the second stress layer after forming the gate structure may effectively reduce the influence of the formation process of the gate structure on the second stress layer, and may effectively reduce the probability of the occurrence of the stress-released issue of the second stress layer. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved.
- the second stress layer may provide greater stress on the channel of the formed semiconductor structure, and the mobility of carriers in the channel of the formed semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure.
- the contact resistance between the plug and the second stress layer may be reduced, facilitating improving the performance of the formed semiconductor structure.
- the anti-leakage doped region formed in the base substrate under the first stress layer may effectively reduce the thermal budget of the second stress layer, facilitating reducing the probability of the occurrence of the stress-released issue of the second stress layer, and improving the performance of the formed semiconductor structure.
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Abstract
Description
- This application is a continuation application of U.S. patent application Ser. No. 16/008,855, filed on Jun. 14, 2018, which claims the priority of Chinese patent application No. 201710461421.8, filed on Jun. 16, 2017, the entirety of which is incorporated herein by reference.
- The present disclosure generally relates to the field of semiconductor technology and, more particularly, relates to a semiconductor structure and fabrication method thereof.
- With the rapid development of semiconductor manufacturing technology, semiconductor devices have been developed toward with higher component density and higher integration degree. Transistors, as the most basic semiconductor devices, have been widely used. With the increasing of the component density and the integration degree of the semiconductor devices, gate dimensions of a planar transistor are scaled down, and the control capability of the gate-to-channel current of the planar transistor becomes weak, leading to a short-channel effect and causing a leakage current issue, thus, affecting the electrical properties of the semiconductor devices.
- To overcome the short-channel effect of the transistor and to suppress the leakage current, fin field effect transistors (FinFET) have been developed. A FinFET is one of common multi-gate devices. In the FinFET, the gate electrode can control the fin from at least two sides. Thus, the FinFET has a much stronger gate-to-channel control capability than the planar device, and can well suppress the short-channel effect. Compared to other devices, the FinFET has better compatibility with existing integrated circuit (IC) fabrication processes.
- In addition, carrier mobility is one of the main factors that affect the performance of the transistor. Effectively increasing the carrier mobility has become one of focuses of the transistor device manufacturing process. Because stress can change an energy gap and the carrier mobility of a silicon material, the performance of the transistor is commonly improved by forming a stress layer. For example, a stress layer capable of providing tensile stress is formed in an N-type transistor to increase electron mobility, and a stress layer capable of providing compressive stress is formed in a P-type transistor to increase hole mobility.
- However, even after using the stress layer, the performance of the semiconductor structure still needs to be improved. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.
- One aspect of the present disclosure includes a method for fabricating a semiconductor structure. The method includes providing a base substrate, and forming a first stress layer in the base substrate. The method also includes forming a gate structure on the base substrate. The first stress layer in the base substrate is on both sides of the gate structure. In addition, the method includes after forming the gate structure, forming an opening in the first stress layer by back-etching the first stress layer. Further, the method includes forming a second stress layer in the opening of the first stress layer.
- Another aspect of the present disclosure includes a semiconductor structure. The semiconductor structure includes a gate structure on a base substrate, and a first stress layer in the base substrate on both sides of the gate structure. The semiconductor structure also includes a second stress layer in the first stress layer and surrounded by the first stress layer.
- Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
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FIGS. 1-2 illustrate semiconductor structures corresponding to certain stages for forming a semiconductor structure; -
FIGS. 3-17 illustrate semiconductor structures corresponding to certain stages for forming an exemplary semiconductor structure consistent with various disclosed embodiments of the present disclosure; and -
FIG. 18 illustrates an exemplary fabrication method for forming a semiconductor structure consistent with various disclosed embodiments of the present disclosure. - Reference will now be made in detail to exemplary embodiments of the disclosure, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or the alike parts.
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FIGS. 1-2 illustrate semiconductor structures corresponding to certain stages for forming the semiconductor structure. Referring toFIG. 1 , asubstrate 11 is provided, and a plurality ofdiscrete fins 12 are formed on thesubstrate 11. Agate structure 13 is formed on thefin 12, and thegate structure 13 is across a length portion of thefin 12 and covers a portion of each of a top surface and a sidewall of thefin 12. Astress layer 14 is formed in thefins 12 on both sides of thegate structure 13. An ion implantation process is performed on thestress layer 14 by an in-situ self-doping method. - To improve the performance of the formed semiconductor structure, a metal gate structure is used in the semiconductor structure. Therefore, the
gate structure 13 is a dummy gate structure. As shown inFIG. 2 , after forming thestress layer 14, aninterlayer dielectric layer 15 is formed on thesubstrate 11. Theinterlayer dielectric layer 15 exposes the dummy gate structure. The dummy gate structure is removed to form a gate opening (not illustrated) in theinterlayer dielectric layer 15. Ametal gate structure 16 is formed in the gate opening. - The activation of doping ions in the
stress layer 14 and the formation of themetal gate structure 16 are accompanied by the use of many thermal processes. Therefore, a thermal budget of the subsequent processes after forming thestress layer 14 is high. The high thermal budget will cause the stress layer 14 a stress-released issue, and affect the performance of the formed semiconductor structure. - Moreover, as the size of the device decreases, the size of the
stress layer 14 keeps decreasing. To reduce a contact resistance between thestress layer 14 and a subsequently formed plug, a doping concentration of thestress layer 14 keeps increasing. The increasing of the doping concentration of thestress layer 14 will enhance the short-channel effect of the formed semiconductor structure, and, thus, affect the performance of the formed semiconductor structure. - In addition, the reduction of the size of the
stress layer 14 will cause thestress layer 14 to reduce the stress applied on the channel of the formed semiconductor structure. Therefore, the mobility of carriers in the channel decreases, and the performance of the formed semiconductor structure degrades. - The present disclosure provides a semiconductor structure and fabrication method of the semiconductor structure. A first stress layer and a second stress layer may be formed before and after forming a gate structure, respectively. The first stress layer and the second stress layer may form a source and drain doped region of the semiconductor structure. The second stress layer may be formed after forming the gate structure, thereby the influence of the formation process of the gate structure on the second stress layer may be reduced, and the probability of the occurrence of a stress-released issue in the second stress layer may be effectively reduced, facilitating improving the performance of the formed semiconductor structure.
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FIG. 18 illustrates an exemplary fabrication method for forming a semiconductor structure consistent with various disclosed embodiments of the present disclosure; andFIGS. 3-17 illustrate semiconductor structures corresponding to certain stages of the exemplary fabrication method. - Referring to
FIGS. 3-11 , abase substrate 100 may be formed, and a gate structure 160 (illustrated inFIG. 11 ) may be formed on thebase substrate 100. A first stress layer 141 (illustrated inFIG. 11 ) may be formed in thebase substrate 100 on both sides of thegate structure 160. - As shown in
FIG. 18 , at the beginning of the fabrication method, a base substrate with certain structures may be formed (S101).FIG. 3 illustrates a corresponding semiconductor structure. - Referring to
FIG. 3 , abase substrate 100 may be formed. Thebase substrate 100 may provide an operation platform for subsequent processes. In one embodiment, the formed semiconductor structure may include a fin structure, and thebase substrate 100 may include asubstrate 110 and a plurality ofdiscrete fins 120 on thesubstrate 110. In another embodiment, the formed semiconductor structure may include a planar structure, and the base substrate may include a planar substrate. Thesubstrate 110 may provide an operation platform for subsequent processes. A channel of the formed semiconductor structure may be located in thefin 120. - In one embodiment, the
substrate 110 may be made of monocrystalline silicon. In another embodiment, the substrate may be made of polysilicon, amorphous silicon, amorphous germanium, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc. In certain embodiments, the substrate may be made of a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, a glass substrate, and other types of substrates. The substrate may be made of materials adapted to process requirements and easy integration. - In one embodiment, the
fin 120 may be made of a same material as thesubstrate 110. Both thefin 120 and thesubstrate 110 may be made of monocrystalline silicon. In another embodiment, the fin may be made of a material different from the substrate. The fin may be made of amorphous germanium, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc. - In one embodiment, the
substrate 110 and thefin 120 may be formed at the same time. Forming thesubstrate 110 and thefin 120 may include: providing an initial substrate; forming a patternedfin mask layer 121 on a surface of the initial substrate; and etching the initial substrate using thefin mask layer 121 as a mask to remove portions of the initial substrate, thereby thesubstrate 110 and thefin 120 protruding on thesubstrate 110 may be formed. In one embodiment, after forming thesubstrate 110 and thefin 120, thefin mask layer 121 may be retained to protect a top of thefin 120. In another embodiment, after forming the substrate and the fin, the fin mask layer may be removed to expose the top of the fin. - When forming the
substrate 110 and thefin 120, damages or minor roughness may occur on the surface of thesubstrate 110 and the sidewall of thefin 120. To improve the performance of the semiconductor structure, in one embodiment, aliner oxide layer 122 may be formed on the surface of thesubstrate 110 and the sidewall of thefin 120. Theliner oxide layer 122 may smooth sharp corners on the surface of thesubstrate 110 and the sidewall of thefin 120, and act as a buffer layer between the subsequently formed film layer and thesubstrate 110 and thefin 120 to reduce the lattice mismatch thereof. For example, theliner oxide layer 122 may be formed by a chemical vapor deposition process, or a thermal oxidation process, etc. In certain embodiments, the liner oxide layer may not be formed. The damages may be repaired by performing an annealing process on thesubstrate 110 and thefin 120. - Returning to
FIG. 18 , after forming the base substrate, an isolation layer may be formed (S102).FIGS. 4-5 illustrate corresponding semiconductor structures. - Referring to
FIG. 5 , anisolation layer 124 may be formed to fill a gap betweenadjacent fins 120. Theisolation layer 124 may cover a portion of the sidewall of thefin 120, and a top of theisolation layer 124 may be lower than the top of thefin 120. The isolation layer, as an isolation structure of the semiconductor structure, may electrically isolate adjacent devices and the adjacent fins. Theisolation layer 124 may be formed on thesubstrate 110 exposed by thefin 120, and a height of theisolation layer 124 may be lower than a height of thefin 120. In one embodiment, the isolation layer may be made of silicon oxide. In another embodiment, the isolation layer may be made of silicon nitride, silicon oxynitride, or other suitable insulating material(s). - In one embodiment, forming the
isolation layer 124 may include: forming an isolation material layer 123 (illustrated inFIG. 4 ) on thesubstrate 110 exposed by thefin 120, where theisolation material layer 123 may cover the top of thefin 120; removing theisolation material layer 123 above the top of thefin 120 by polishing; and removing a portion of the remaining isolation material layer along a thickness direction of the isolation material layer by back-etching to expose the top and a portion of the sidewall of thefin 120, thereby theisolation layer 124 may be formed. When the fin mask layer 121 (illustrated inFIG. 3 ) is retained after forming thesubstrate 110 and thefin 120, thefin mask layer 121 may protect the top of thefin 120 during the back-etching process. After forming theisolation layer 124, thefin mask layer 121 may be removed to expose the top of thefin 120. - The
gate structure 160 may be a gate structure of the formed semiconductor structure, and may be used to control turned-on and turned-off of the channel of the formed semiconductor structure. Thefirst stress layer 141 may be used as a portion of a source and drain doped region of the formed semiconductor structure, and may provide stress on the channel of the formed semiconductor structure to increase mobility of carriers in the channel. - In one embodiment, the formed semiconductor structure may include a metal gate structure. That is, the
gate structure 160 may be a metal gate structure. Thegate structure 160 may include a gate dielectric layer and a metal gate electrode. In another embodiment, the gate structure may be a polysilicon gate structure or other gate structures. - In one embodiment, referring to
FIGS. 6-11 , forming the first stress layer 141 (illustrated inFIG. 8 ) and the gate structure 160 (illustrated inFIG. 11 ) may include forming adummy gate structure 130 on thebase substrate 100 after forming thebase substrate 100; forming thefirst stress layer 141 in thebase substrate 100 on both sides of thedummy gate structure 130; forming a firstdielectric layer 151 after forming thefirst stress layer 141, where thefirst dielectric layer 151 may expose thedummy gate structure 130; forming a gate opening 161 (illustrated inFIG. 10 ) in thefirst dielectric layer 151 by removing the dummy gate structure 130 (illustrated inFIG. 9 ), and forming the metal gate structure (illustrated inFIG. 11 ) in thegate opening 161. - Returning to
FIG. 18 , after forming the isolation layer, a dummy gate structure may be formed (S103).FIGS. 6-7 illustrate corresponding semiconductor structures. - Referring to
FIG. 7 , adummy gate structure 130 may be formed on thebase substrate 100. Thedummy gate structure 130 may occupy a space for subsequently forming a metal gate structure. In one embodiment, thebase substrate 100 may include thesubstrate 110 and thefin 120. Therefore, thedummy gate structure 130 may be across a length portion of thefin 120 and cover a portion of each of the top surface and the sidewall of thefin 120. - In one embodiment, the
dummy gate structure 130 may be a stacked-layer structure. Thedummy gate structure 130 may include adummy oxide layer 1301 and adummy gate layer 1302 on thedummy oxide layer 1301. In another embodiment, the dummy gate structure may be a single-layer structure. Correspondingly, the dummy gate structure may include the dummy gate layer. - In one embodiment, the
dummy oxide layer 1301 may be made of silicon oxide. In another embodiment, the dummy oxide layer may be made of silicon oxynitride. In one embodiment, thedummy gate layer 1302 may be made of polysilicon. In another embodiment, the dummy gate layer may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon, etc. - In one embodiment, forming the
dummy gate structure 130 may include: forming an oxide material layer 125 (illustrated inFIG. 6 ) on the surface of thefin 120 exposed by theisolation layer 124; forming a dummy gate material layer (not illustrated) on theoxide material layer 125; forming apatterned gate mask 131 on a surface of the dummy gate material layer; and etching the dummy gate material layer until theoxide material layer 125 is exposed by using the patternedgate mask 131 as a mask to form thedummy gate layer 1302 on theoxide material layer 125. Thedummy gate layer 1302 may be across the length portion of thefin 120 and cover a portion of each of the top surface and the sidewall of thefin 120. Forming thedummy gate structure 130 may also include removing theoxide material layer 125 exposed by thedummy gate layer 1302 to expose the surface of thefin 120. The remainingoxide material layer 125 covered by thedummy gate layer 1302 may be used as thedummy oxide layer 1301. Thedummy oxide layer 1301 may be across the length portion of thefin 120 and cover a portion of each of the top surface and the sidewall of thefin 120. - In one embodiment, after forming the
dummy gate structure 130, thegate mask 131 on the top of thedummy gate structure 130 may be retained. In one embodiment, thegate mask 131 may be made of silicon nitride. In another embodiment, thegate mask 131 may be made of silicon oxynitride, silicon carbide, or boron nitride, etc. Thegate mask 131 may protect the top of thedummy gate structure 130 during subsequent processes. - After forming the
dummy gate structure 130, asidewall spacer 132 may be formed on the sidewall of thedummy gate structure 130. Thesidewall spacer 132 may protect thedummy gate structure 130 and define a position of a subsequently formed source and drain doped region. Thesidewall spacer 132 may be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, etc. The sidewall spacer may be a single-layer structure, or a stacked-layer structure. In one embodiment, thesidewall spacer 132 may be a single-layer structure, and may be made of silicon nitride. - Returning to
FIG. 18 , after forming the dummy gate structure, a first stress layer may be formed (S104).FIG. 8 illustrates a corresponding semiconductor structure. - Referring to
FIG. 8 , afirst stress layer 141 may be formed in thebase substrate 100 on both sides of thedummy gate structure 130. Thefirst stress layer 141 may be used as a portion of the source and drain doped region of the formed semiconductor structure. - In one embodiment, the formed semiconductor structure may be used to form an NMOS device, thus, the
stress layer 141 may be an N-type doped stress layer. Thefirst stress layer 141 may be made of N-type doped silicon carbon or silicon. The dopant ions in thefirst stress layer 141 may be N-type ions, such as P, As, or Sb, etc. - In certain embodiments, the formed semiconductor structure may be used to form a PMOS device, or a CMOS device. When the formed semiconductor structure is used to form a PMOS device, the first stress layer may be made of P-type doped silicon germanium or silicon. The dopant ions in the first stress layer may be P-type ions, such as B, Ga, or In, etc. When the formed semiconductor structure is used to form a CMOS device, the material and doped type of the first stress layer may be different according to different types of the semiconductor structure.
- In one embodiment, the
base substrate 100 may include thesubstrate 110 and thefin 120. Thefirst stress layer 141 may be formed in thefin 120 on both sides of thedummy gate structure 130. Therefore, forming thefirst stress layer 141 may include forming thefirst stress layer 141 in thefin 120 on both sides of thedummy gate structure 130. - To increase the effect of the
first stress layer 141 exerting stress on the channel of the formed semiconductor structure, in one embodiment, thefirst stress layer 141 may be disposed adjacent to thedummy gate structure 130. In one embodiment, thesidewall spacer 132 may be formed on the sidewall of thedummy gate structure 130, such that thefirst stress layer 141 may be in contact with thesidewall spacer 132. - In one embodiment, forming the
first stress layer 141 may include forming openings (not illustrated) in thefin 120 on both sides of thedummy gate structure 130; and forming thefirst stress layer 141 in the openings by an epitaxial growth process, where an in-situ self-doping may be performed during the epitaxial growth of thefirst stress layer 141. - In one embodiment, the formed semiconductor structure may be used to form an NMOS device, the in-situ self-doped dopant ions may be P ions, and a doping concentration may be in a range of approximately 8.0×1020 atoms/cm3-2.5×1021 atoms/cm3. In another embodiment, the formed semiconductor structure may be used to form a PMOS device, and the in-situ self-doped dopant ions may be B ions, and a doping concentration may be in a range of approximately 2.0×1020 atoms/cm3-1.5×1021 atoms/cm3.
- Returning to
FIG. 18 , after forming the first stress layer, a first dielectric layer may be formed (S105).FIG. 9 illustrates a corresponding semiconductor structure. - Referring to
FIG. 9 , after forming the first stress layer, a firstdielectric layer 151 may be formed on thebase substrate 100. Thefirst dielectric layer 151 may expose the top of thedummy gate structure 130. Thefirst dielectric layer 151, as a portion of an interlayer dielectric layer, may electrically isolate adjacent semiconductor structures. - In one embodiment, the
first dielectric layer 151 may be made of silicon oxide. In another embodiment, thefirst dielectric layer 151 may be made of silicon nitride, silicon oxynitride, or other suitable insulating material(s). - Forming the
first dielectric layer 151 may include: forming a dielectric material layer (not illustrated) on thesubstrate 110 exposed by thedummy gate structure 130, where the dielectric material layer may cover thedummy gate structure 130; removing the dielectric material layer above thedummy gate structure 130 by polishing, thereby thefirst dielectric layer 151 may be formed; and removing thegate mask 131 to expose the top of thedummy gate structure 130. - Returning to
FIG. 18 , after forming the first dielectric layer, a gate opening may be formed (S106).FIG. 10 illustrates a corresponding semiconductor structure. - Referring to
FIG. 10 , agate opening 161 may be formed in thefirst dielectric layer 151 by removing the dummy gate structure 130 (illustrated inFIG. 9 ). Thegate opening 161 may provide a process space for the formation of a metal gate structure. - In one embodiment, the
base substrate 100 may include thesubstrate 110 and thefin 120. Thedummy gate structure 130 may be across the length portion of thefin 120 and cover a portion of each of the top surface and the sidewall of thefin 120. Therefore, a bottom of thegate opening 161 may expose a portion of each of the top surface and the sidewall of thefin 120. - Returning to
FIG. 18 , after forming the gate opening, a gate structure may be formed (S107).FIG. 11 illustrates a corresponding semiconductor structure. - Referring to
FIG. 11 , agate structure 160 may be formed in the gate opening 161 (illustrated inFIG. 10 ). Thegate structure 160 may include a gate dielectric layer (not illustrated) and a metal gate electrode (not illustrated) on the gate dielectric layer. Forming thegate structure 160 in thegate opening 161 may include: forming the gate dielectric layer on thebase substrate 100 exposed at the bottom of thegate opening 161, and forming the metal gate electrode on the gate dielectric layer. - The gate dielectric layer may electrically isolate the
gate structure 160 and the channel in thebase substrate 100. The gate dielectric layer may be made of a high-K dielectric material, where the high-K dielectric material may be referred to a dielectric material having a relative dielectric constant greater than silicon oxide. In one embodiment, the gate dielectric layer may be made of HfO2. In certain embodiments, the gate dielectric layer may be made of ZrO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, or Al2O3, etc. - In one embodiment, the bottom of the
gate opening 161 may exposes a portion of each of the top surface and the sidewall of thefin 120. The gate dielectric layer may be across the length portion of thefin 120 and on a portion of each of the top surface and the sidewall of thefin 120. - The gate dielectric layer may be formed by an atomic layer deposition process. In certain embodiments, the gate dielectric layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, or other film deposition processes.
- The metal gate electrode may be configured as an electrode to achieve electrical connection to an external circuit. In one embodiment, the metal gate electrode may be made of W. In certain embodiments, the metal gate electrode may be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.
- In the disclosed embodiments, a high-K last metal gate last process sequence is described for illustrative purposes. In certain embodiments, a high-K first metal gate last process sequence, or a high-K first metal gate first process sequence may be used.
- Returning to
FIG. 18 , after forming the gate structure, an opening in the first stress layer may be formed (S108).FIGS. 12-13 illustrate corresponding semiconductor structures. - Referring to
FIG. 13 , after forming thegate structure 160, anopening 143 may be formed in thefirst stress layer 141 by back-etching thefirst stress layer 141. - In one embodiment, an interlayer dielectric layer may be formed on the
base substrate 100. Therefore, referring toFIG. 12 , before performing the back-etching process, asecond dielectric layer 152 may be formed on thefirst dielectric layer 151. Thesecond dielectric layer 152 may cover thegate structure 160. Thesecond dielectric layer 152, as a portion of the interlayer dielectric layer, may be used together with thefirst dielectric layer 151 to electrically isolate different semiconductor structures. In one embodiment, thesecond dielectric layer 152 may be made of silicon oxide. In another embodiment, the second dielectric layer may be made of silicon nitride, silicon oxynitride, or other suitable insulating material(s). - Forming the
opening 143 may include: referring toFIG. 12 , forming acontact hole 181 in the interlayer dielectric layer, where a bottom of the contact hole may expose thefirst stress layer 141; and referring toFIG. 13 , back-etching thefirst stress layer 141 along thecontact hole 181 to form theopening 143. - The
contact hole 181 may expose thefirst stress layer 141, and provide a process operation space for the formation of theopening 143 and a subsequent second stress layer. In one embodiment, thecontact hole 181 may also provide a process space for the subsequent formation of a plug. In one embodiment, the interlayer dielectric layer may include thefirst dielectric layer 151 and thesecond dielectric layer 152, thus, thecontact hole 181 may penetrate through thefirst dielectric layer 151 and thesecond dielectric layer 152. - In one embodiment, the
contact hole 181 may be formed by a dry etching process. The dry etching process may have strong anisotropic characteristics, effectively reduce the loss of the interlayer dielectric layer, and improve the quality of thecontact hole 181. - In one embodiment, after forming the
gate structure 160 and before forming thefirst dielectric layer 151, a contact etch stop layer (CESL) (not illustrated) may be formed. The contact etch stop layer may cover thebase substrate 100, thefirst stress layer 141, and thegate structure 160. The contact etch stop layer may protect thefirst stress layer 141 and thegate structure 160 from adverse effects caused by the formation process of thecontact hole 181. The contact etch stop layer may be made of silicon nitride. - Forming the
contact hole 181 may include: forming thecontact hole 181 to penetrate through the interlayer dielectric layer by a dry etching process, where the bottom of thecontact hole 181 may expose the contact etch stop layer on thefirst stress layer 141; and removing the exposed contact etch stop layer to expose thefirst stress layer 141 at the bottom of thecontact hole 181. - Referring to
FIG. 13 , the process of back-etching thefirst stress layer 141 may be used to remove a portion of thefirst stress layer 141, thereby thefirst stress layer 141 affected by the fabrication process of thegate structure 160 may be removed. Moreover, the process of back-etching thefirst stress layer 141 may form theopening 143 in thefirst stress layer 141, thereby providing a process space for the subsequent formation of a second stress layer. - Forming the
opening 143 by performing the back-etching process through thecontact hole 181 may reduce the process steps for forming the semiconductor structure, reduce the number of times of photolithography process, and avoid alignment issues of the fore and post lithography processes, thereby facilitating improving the performance and yield of the formed semiconductor structure. - In one embodiment, the
first stress layer 141 may be back-etched through a dry etching process. That is, a portion of thefirst stress layer 141 exposed at the bottom of thecontact hole 180 may be removed by a dry etching process along the contact hole 180 (illustrated inFIG. 12 ) to form theopening 143 in thefirst stress layer 141. - The
opening 143 may be used to subsequently form the second stress layer, thus, the size of theopening 143 may be related to the size of the subsequently formed second stress layer. Therefore, a depth of theopening 143 cannot be too small or too large. - If the depth of the
opening 143 is too large, the amount of the removedfirst stress layer 141 may be too large, thus, a volume of the second stress layer subsequently formed in theopening 143 may be substantially large, and a depth of the formed second stress layer may be too large. Therefore, a distance between the formed second stress layer and the channel of the formed semiconductor structure may be too small, causing the short-channel effect to be easily deteriorated, and an excessive leakage current issue may be likely to occur. If the depth of theopening 143 is too small, the amount of the removedfirst stress layer 141 may be too small, and the volume of the second stress layer subsequently formed in theopening 143 may be too small. Therefore, the effect of the formed second stress layer exerting stress on the channel of the formed semiconductor structure may not be effectively increased, the mobility of carriers in the channel may not be effectively improved, and the performance of the formed semiconductor structure may not be effectively improved. - In one embodiment, a ratio of the depth of the
opening 143 over an entire thickness of thefirst stress layer 141 may be in a range of approximately ⅓-⅔. That is, in a direction perpendicular to the surface of thesubstrate 110, the ratio of the size of theopening 143 over the size of thefirst stress layer 141 may be in a range of approximately ⅓-⅔. - Process parameters of the back-etching process may be selected within a reasonable range. By controlling an etching time of the back-etching process, the thickness of the removed
first stress layer 141 may be controlled, and, thus, the depth of theopening 143 may be controlled to enable the depth of theopening 143 to meet design requirements. - Returning to
FIG. 18 , after forming the opening in the first stress layer, an anti-leakage doped region may be formed (S109).FIG. 14 illustrates a corresponding semiconductor structure. - Referring to
FIG. 14 , in one embodiment, after forming theopening 143, an anti-leakagedoped region 170 may be formed in thebase substrate 100 under thefirst stress layer 141 by performing ananti-leakage implantation 171 along the opening 143 (illustrated inFIG. 13 ). - The
anti-leakage implantation 171 may be used to implant dopant ions into thebase substrate 100 under thefirst stress layer 141, thus, the anti-leakagedoped region 170 may be formed. The anti-leakagedoped region 170 may be used to suppress the leakage current of the formed semiconductor structure. - The
anti-leakage implantation 171 may be performed along the opening 143 (illustrated inFIG. 13 ) to form the anti-leakagedoped region 170 in thebase substrate 100 under thefirst stress layer 141. Because theopening 143 is disposed within thefirst stress layer 141, by performing theanti-leakage implantation 171 along theopening 143, an energy of theanti-leakage implantation 171 may be effectively reduced, and the influence of theanti-leakage implantation 171 on other semiconductor structures may be reduced, facilitating improving the performance of the formed semiconductor structure. - In one embodiment, the
base substrate 100 may include thesubstrate 110 and thefin 120, thus, the anti-leakagedoped region 170 may be located in thefin 120 under thefirst stress layer 141. Theopenings 143 may be located at the bottom of the contact hole 181 (illustrated inFIG. 12 ), and may be through-connected to thecontact hole 181. Thecontact hole 181 may penetrate through thefirst dielectric layer 151 and thesecond dielectric layer 152. Therefore, because theanti-leakage implantation 171 is performed along thecontact hole 181 and theopening 143, the energy required for theanti-leakage implantation 171 may be effectively reduced, and the damages on thefirst stress layer 141 and thefin 120 caused by theanti-leakage implantation 171 may be reduced, thereby facilitating improving the performance of the formed semiconductor structure. - In one embodiment, when the semiconductor structure is used to form an NMOS device, process parameters of the
anti-leakage implantation 171 may include the following. Implanted ions may be P ions, an implantation energy may be in a range of approximately 2 KeV-20 KeV, and an implantation dose may be in a range of approximately 2.0×1014 atoms/cm3-5.0×1015 atoms/cm3. - In another embodiment, when the semiconductor structure is used to form a PMOS device, the process parameters of the
anti-leakage implantation 171 may include the following. Implanted ions may be B ions or BF2 ions, an implantation energy may be in a range of approximately 2 KeV-20 KeV, and an implantation dose may be in a range of approximately 2.0×1013 atoms/cm3-3.0×1015 atoms/cm3. - Returning to
FIG. 18 , after forming the anti-leakage doped region, an activation annealing may be performed (S110).FIG. 15 illustrates a corresponding semiconductor structure. - Referring to
FIG. 15 , after performing theanti-leakage implantation 171, anactivation annealing 172 may be performed on the anti-leakagedoped region 170. Theactivation annealing 172 may be used to enable the dopant ions to relax to positions of the lattices, and, thus, to be activated. - In one embodiment, the
activation annealing 172 may be a spike annealing process at an annealing temperature in a range of approximately 950° C.-1050° C. In another embodiment, the activation annealing may be a laser annealing process at an annealing temperature in a range of approximately 1150° C.-1350° C. The annealing temperature of theactivation annealing 172 cannot be too high nor too low. - If the annealing temperature of the
activation annealing 172 is too high, the thermal budget may be too high and may cause adverse effects on the remainingfirst stress layer 141, thus, a stress-released issue of the remainingfirst stress layer 141 may be likely to occur, and the dopant ions in thefirst stress layer 141 may diffuse to cause the deterioration of the short-channel effect. If the annealing temperature of theactivation annealing 172 is too low, the activation of the dopant ions in the anti-leakagedoped region 170 may be affected, and, thus, the leakage current suppression function of the anti-leakagedoped region 170 may be affected to degrade the performance of the formed semiconductor structure. - Returning to
FIG. 18 , after performing the activation annealing, a second stress layer may be formed (S111).FIG. 16 illustrates a corresponding semiconductor structure. - Referring to
FIG. 16 , asecond stress layer 142 may be formed in the opening 143 (illustrated inFIG. 13 ). Thesecond stress layer 142 may be used as a portion of the source and drain doped region of the formed semiconductor structure, and together with thefirst stress layer 141, may exert a stress to the channel of the formed semiconductor structure, to increase the carrier mobility in the channel. - The
second stress layer 142 may be formed after forming thegate structure 160. Thegate structure 160 may be a metal gate structure, and the formation process of the metal gate structure may include multiple thermal processes, such that the thermal budget of the formation process of thegate structure 160 may be large. Therefore, by forming thesecond stress layer 142 after forming thegate structure 160, the influence of the formation process of thegate structure 160 on thesecond stress layer 142 may be effectively reduced. In particular, thesecond stress layer 142 may not be affected by the thermal process during the formation of thegate structure 160, and the probability of the occurrence of the stress-released issue of thesecond stress layer 142 may be effectively reduced. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved. - In addition, in one embodiment, before forming the
second stress layer 142, the anti-leakagedoped region 170 may be formed and the activation annealing may be performed. Therefore, thermal budget of thesecond stress layer 142 may be effectively reduced, facilitating reducing the probability of the occurrence of the stress-released issue of thesecond stress layer 142, and improving the performance of the formed semiconductor structure. - In one embodiment, the formed semiconductor structure may be used to form an NMOS device, the
second stress layer 142 may be made of carbon silicon for exerting tensile stress on the channel of the formed semiconductor structure. In one embodiment, thefirst stress layer 141 may be made of carbon silicon or silicon, and the content of carbon in thesecond stress layer 142 may be greater than or equal to the content of carbon in thefirst stress layer 141. The stress layer may exert stress on the channel of the formed semiconductor structure through a principle of lattice mismatch, because the content of carbon in thesecond stress layer 142 is higher, thesecond stress layer 142 may exert a greater stress on the channel of the formed semiconductor structure. Therefore, the mobility of carriers in the channel of the formed semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure. - In one embodiment, the formed semiconductor structure may be used to form an NMOS device, the
first stress layer 141 may be made of carbon silicon or silicon, and thesecond stress layer 142 may be made of carbon silicon. In another embodiment, when the formed semiconductor structure is used to form a PMOS device, the first stress layer may be made of silicon germanium or silicon, and the second stress layer may be made of silicon germanium. The second stress layer may be made of silicon germanium, and the content of germanium in the second stress layer may be greater than or equal to the content of germanium in the first stress layer. Therefore, the second stress layer may exert a greater stress on the channel of the formed semiconductor structure to improve the performance of the formed semiconductor structure. - The
second stress layer 142 may be a doped stress layer, and a doping type of thesecond stress layer 142 may be the same as a doping type of thefirst stress layer 141. In one embodiment, the formed semiconductor structure may be used to form an NMOS device, and thefirst stress layer 141 may be an N-type doped stress layer, thus, thesecond stress layer 142 may be made of N-type doped carbon silicon or silicon. The dopant ions in thesecond stress layer 142 may be N-type ions, such as P, As, or Sb, etc. - In one embodiment, a doping concentration of the
second stress layer 142 may be greater than or equal to a doping concentration of thefirst stress layer 141. Use of thesecond stress layer 142 having the doping concentration greater than or equal to thefirst stress layer 141 may effectively reduce a contact resistance between a subsequently formed plug and thesecond stress layer 142. - The
second stress layer 142 may be located in theopening 143, and theopening 143 may be located in thefirst stress layer 141. That is, thesecond stress layer 142 may be located in thefirst stress layer 141. In other words, in a plane parallel to the surface of thesubstrate 110, thefirst stress layer 141 may surround thesecond stress layer 142. Therefore, a portion of thefirst stress layer 141 may be disposed between the channel of the formed semiconductor structure and thesecond stress layer 142, and thesecond stress layer 142 may be spaced a certain distance from the channel of the semiconductor structure. Therefore, thesecond stress layer 142 with a substantially large doping concentration may be prevented from causing a deterioration of the short-channel effect. - Therefore, under the premise of controlling the short-channel effect, the formation of the
second stress layer 142 with a substantially large doping concentration may reduce the contact resistance between the plug and thesecond stress layer 142, facilitating improving the performance of the formed semiconductor structure. - In one embodiment, forming the
second stress layer 142 may include forming thesecond stress layer 142 in theopening 143 by an epitaxial growth process, where an in-situ self-doping process may be performed during the epitaxial growth of thesecond stress layer 142. - In one embodiment, the formed semiconductor structure may be used to form an NMOS device, in-situ self-doped dopant ions may be P ions, and a doping concentration may be in a range of approximately 8.0×1020 atoms/cm3-2.5×1021 atoms/cm3. In another embodiment, the formed semiconductor structure may be used to form a PMOS device, and the in-situ self-doped dopant ions may be B ions, and a doping concentration may be in a range of approximately 2.0×1020 atoms/cm3-1.5×1021 atoms/cm3.
- Returning to
FIG. 18 , after forming the second stress layer, a plug may be formed (S112).FIG. 17 illustrates a corresponding semiconductor structure. - Referring to
FIG. 17 , in one embodiment, after forming thesecond stress layer 142, aplug 180 may be formed in the contact hole 181 (illustrated inFIG. 16 ). Theplug 180 may be used to electrically connect the source and drain doped region of the formed semiconductor structure to an external circuit. - In one embodiment, the
plug 180 may be made of tungsten. In one embodiment, the source and drain doped region may include thefirst stress layer 141 and thesecond stress layer 142, and, thus, theplug 180 may be disposed on thesecond stress layer 142 and penetrate through thefirst dielectric layer 151 and thesecond dielectric layer 152 over thesecond stress layer 142. - In one embodiment, forming the
plug 180 may include filling thecontact hole 181 with a conductive material, where the conductive material may cover thesecond dielectric layer 152; and removing the conductive material above thesecond dielectric layer 152 to form theplug 180. - In the disclosed embodiments, the opening may be formed in the first stress layer, and the second stress layer may be formed in the opening. The first stress layer and the second stress layer may together form the source and drain doped region of the semiconductor structure. Forming the second stress layer after forming the gate structure may effectively reduce the influence of the formation process of the gate structure on the second stress layer and the probability of the occurrence of the stress-released issue of the second stress layer. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved.
- The gate structure may be the metal gate structure. Before forming the first stress layer, the dummy gate structure may be formed on the base substrate. After forming the first stress layer and before forming the opening, the dummy gate structure may be removed, and the metal gate structure may be formed in the position where the dummy gate structure is previously located. Therefore, the opening and the second stress layer may be formed after forming the metal gate structure. The formation process of the opening may remove a portion of the first stress layer, thereby a portion of the first stress layer having a degraded performance may be removed. The second stress layer reformed in the opening may not be subject to the influence of the formation process of the metal gate structure, and, thus, may have desired performance. Therefore, the source and drain doped region formed by the second stress layer and the first stress layer may have desired performance, and may facilitate improving the performance of the formed semiconductor structure.
- When the second stress layer is made of silicon germanium, the content of germanium in the second stress layer may be greater than or equal to the content of germanium in the first stress layer. When the second stress layer is made of silicon carbon, the content of carbon in the second stress layer may be greater than or equal to the content of carbon in the first stress layer. Accordingly, the second stress layer may exert a greater stress on the channel of the formed semiconductor structure. Therefore, the mobility of carriers in the channel of the semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure.
- The doping concentration of the second stress layer may be greater than or equal to the doping concentration of the first stress layer. Accordingly, the contact resistance between the plug and the second stress layer may be effectively reduced. The second stress layer may be disposed in the first stress layer. In other words, a portion of the first stress layer may be disposed between the channel of the semiconductor structure and the second stress layer, and the second stress layer may be spaced a certain distance from the channel of the semiconductor structure. Therefore, the second stress layer with a substantially large doping concentration may be prevented from causing a deterioration of the short-channel effect. Therefore, under the premise of controlling the short-channel effect, the formation of the second stress layer with a substantially large doping concentration may reduce the contact resistance between the plug and the second stress layer, facilitating improving the performance of the semiconductor structure.
- After forming the opening and before forming the second stress layer, the anti-leakage doped region may be formed in the base substrate under the first stress layer by performing the anti-leakage implantation along the opening. Because the opening is disposed in the first stress layer, by performing the anti-leakage implantation along the opening, the energy of the anti-leakage implantation may be effectively reduced, and the influence of the anti-leakage implantation on other semiconductor structures may be reduced, facilitating improving the performance of the formed semiconductor structure. Further, the second stress layer may be formed after performing the anti-leakage implantation and the activation annealing, the thermal budget of the second stress layer may be effectively reduced, facilitating reducing the probability of the occurrence of the stress-released issue of the second stress layer, and improving the performance of the formed semiconductor structure.
- The present disclosure also provides a semiconductor structure.
FIG. 17 illustrates a cross-sectional view of an exemplary semiconductor structure consistent with various disclosed embodiments of the present disclosure. Referring toFIG. 17 , the semiconductor structure may include abase substrate 100, agate structure 160 on thebase substrate 100, afirst stress layer 141 in thebase substrate 100 on both sides of thegate structure 160, and asecond stress layer 142 in thefirst stress layer 141. Thesecond stress layer 142 may be formed after forming thegate structure 160. - The
second stress layer 142 may be located in thefirst stress layer 141. Thefirst stress layer 141 together with thesecond stress layer 142 may form a source and drain doped region of the semiconductor structure. Because thesecond stress layer 142 is formed after forming the gate structure 162, the influence of the formation process of thegate structure 160 on thesecond stress layer 142 may be effectively reduced, and the probability of the occurrence of the stress-released issue of thesecond stress layer 142 may be effectively reduced. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved. - In one embodiment, the semiconductor structure may include a metal gate structure. That is, the
gate structure 160 may be the metal gate structure. In one embodiment, the formed semiconductor structure may be used to form an NMOS device, thus, thefirst stress layer 141 may be an N-type doped stress layer. Thefirst stress layer 141 may be made of N-type doped carbon silicon or silicon. The dopant ions in thefirst stress layer 141 may be N-type ions, such as P, As, or Sb, etc. - The
second stress layer 142 may be used as a portion of the source and drain doped region of the formed semiconductor structure, and together with thefirst stress layer 141, may exert a stress to the channel of the formed semiconductor structure, to improve the carrier mobility in the channel. - The
second stress layer 142 may be formed after forming thegate structure 160. Thegate structure 160 may be the metal gate structure, and the formation process of the metal gate structure may include multiple thermal processes, such that the thermal budget of the formation process of thegate structure 160 may be large. Therefore, by forming thesecond stress layer 142 after forming thegate structure 160, the influence of the formation process of thegate structure 160 on thesecond stress layer 142 may be effectively reduced. In particular, thesecond stress layer 142 may not be affected by the thermal process during the formation of thegate structure 160, and the probability of the occurrence of the stress-released issue of thesecond stress layer 142 may be effectively reduced. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved. - In one embodiment, the semiconductor structure may be used to form an NMOS device, the
second stress layer 142 may be made of carbon silicon for exerting tensile stress on the channel of the semiconductor structure. In one embodiment, thefirst stress layer 141 may be made of carbon silicon or silicon. The content of carbon in thesecond stress layer 142 may be greater than or equal to the content of carbon in thefirst stress layer 141. The stress layer may exert stress on the channel of the semiconductor structure through a principle of lattice mismatch, because the content of carbon in thesecond stress layer 142 is higher, thesecond stress layer 142 may exert a greater stress on the channel of the semiconductor structure. Therefore, the mobility of carriers in the channel of the semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure. - In one embodiment, the semiconductor structure may be used to form an NMOS device, the
first stress layer 141 may be made of carbon silicon or silicon, and thesecond stress layer 142 may be made of carbon silicon. In another embodiment, when the semiconductor structure is used to form a PMOS device, the first stress layer may be made of silicon germanium or silicon, and the second stress layer may be made of silicon germanium. The second stress layer may be made of silicon germanium, and the content of germanium in the second stress layer may be greater than or equal to the content of germanium in the first stress layer. Therefore, the second stress layer may exert a greater stress on the channel of the formed semiconductor structure to improve the performance of the semiconductor structure. - The
second stress layer 142 may be a doped stress layer, and a doping type of thesecond stress layer 142 may be the same as a doping type of thefirst stress layer 141. In one embodiment, the semiconductor structure may be used to form an NMOS device, and thefirst stress layer 141 may be an N-type doped stress layer, thus, thesecond stress layer 142 may be made of N-type doped carbon silicon. The dopant ions in thesecond stress layer 142 may be N-type ions, such as P, As, or Sb, etc. - In one embodiment, a doping concentration of the
second stress layer 142 may be greater than or equal to a doping concentration of thefirst stress layer 141. Use of thesecond stress layer 142 having a doping concentration greater than or equal to thefirst stress layer 141 may effectively reduce a contact resistance between a subsequently formed plug and thesecond stress layer 142. - The
second stress layer 142 may be located in thefirst stress layer 141. In other words, in a plane parallel to the surface of thesubstrate 110, thefirst stress layer 141 may surround thesecond stress layer 142. Therefore, a portion of thefirst stress layer 141 may be disposed between the channel of the semiconductor structure and thesecond stress layer 142, and thesecond stress layer 142 may be spaced apart by a certain distance from the channel of the semiconductor structure. Therefore, thesecond stress layer 142 with a substantially large doping concentration may be prevented from causing a deterioration of the short-channel effect. - Therefore, under the premise of controlling the short-channel effect, the formation of the
second stress layer 142 with a substantially large doping concentration may reduce the contact resistance between the plug and thesecond stress layer 142, facilitating improving the performance of the semiconductor structure. - In the disclosed embodiments, the semiconductor structure may be formed by the disclosed fabrication method of a semiconductor structure. Therefore, the detailed technical solution of the semiconductor structure may be referred to various embodiments of the present disclosure for forming a semiconductor structure, and is not repeated herein.
- Accordingly, by forming the second stress layer after forming the gate structure may effectively reduce the influence of the formation process of the gate structure on the second stress layer, and may effectively reduce the probability of the occurrence of the stress-released issue of the second stress layer. Therefore, the performance of the source and drain doped region of the formed semiconductor structure may be improved, and the performance of the formed semiconductor structure may be improved. In the disclosed embodiments, by increasing the content of germanium or carbon in the second stress layer, the second stress layer may provide greater stress on the channel of the formed semiconductor structure, and the mobility of carriers in the channel of the formed semiconductor structure may be effectively improved, thereby facilitating improving the performance of the formed semiconductor structure. In addition, under the premise of controlling the short-channel effect, by increasing the doping concentration of the second stress layer, the contact resistance between the plug and the second stress layer may be reduced, facilitating improving the performance of the formed semiconductor structure. Further, the anti-leakage doped region formed in the base substrate under the first stress layer may effectively reduce the thermal budget of the second stress layer, facilitating reducing the probability of the occurrence of the stress-released issue of the second stress layer, and improving the performance of the formed semiconductor structure.
- The above detailed descriptions only illustrate certain exemplary embodiments of the present disclosure, and are not intended to limit the scope of the present disclosure. Those skilled in the art can understand the specification as whole and technical features in the various embodiments can be combined into other embodiments understandable to those persons of ordinary skill in the art. Any equivalent or modification thereof, without departing from the spirit and principle of the present disclosure, falls within the true scope of the present disclosure.
Claims (11)
Priority Applications (1)
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CN107799421B (en) * | 2016-09-05 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
CN109148578B (en) * | 2017-06-16 | 2021-09-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US11296225B2 (en) | 2018-06-29 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
CN113053747B (en) * | 2019-12-26 | 2022-09-09 | 株洲中车时代半导体有限公司 | Method for improving warpage of SiC wafer and preparation method of SiC semiconductor device |
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CN116504718B (en) * | 2023-06-25 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure |
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