CN107045984B - Method for forming transistor - Google Patents

Method for forming transistor Download PDF

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CN107045984B
CN107045984B CN201610083791.8A CN201610083791A CN107045984B CN 107045984 B CN107045984 B CN 107045984B CN 201610083791 A CN201610083791 A CN 201610083791A CN 107045984 B CN107045984 B CN 107045984B
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forming
layer
substrate
gate structure
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CN107045984A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L29/772—Field effect transistors
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a transistor, comprising: forming a substrate, and forming a gate structure on the substrate, wherein the substrate comprises a first area, and the gate structure positioned in the first area is a first gate structure; forming a first doped layer; forming an opening in the first doped layer; performing diffusion-preventing injection on the first doping layer exposed from the bottom and the side wall of the opening; carrying out pre-drying treatment; filling a first semiconductor material into the opening to form a first stress layer; and carrying out ion doping on the first stress layer to form a source region or a drain region. According to the invention, after the opening is formed, diffusion implantation is carried out on the first doping layer exposed at the bottom and the side wall of the opening, ions for preventing diffusion implantation can be combined with the doping ions in the first doping layer to form clusters, so that the loss of the doping ions in the first doping layer in the follow-up pre-drying treatment process is inhibited, the implantation dosage loss of the doping ions in the first doping layer is reduced, and the performance of the formed transistor is improved.

Description

Method for forming transistor
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a transistor forming method.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. A transistor is currently being widely used as the most basic semiconductor device, and therefore as the element density and integration of the semiconductor device are increased, the gate size of the transistor becomes shorter than ever. However, the gate size of the transistor becomes such that short channel effects occur in the transistor, which in turn causes leakage current, which ultimately affects the electrical performance of the semiconductor device.
The prior art has been to improve semiconductor device performance, primarily by improving carrier mobility. When the mobility of the carrier is improved, the driving current of the transistor is improved, the leakage current in the transistor is reduced, and a key element for improving the mobility of the carrier is to improve the stress in the channel region of the transistor, so that the performance of the transistor can be greatly improved by improving the stress of the channel region of the transistor.
One method for improving the stress of the channel region of a transistor in the prior art is as follows: and forming stress layers in a source region and a drain region of the transistor. The stress layer material of the P-type transistor is a germanium-silicon material (SiGe), and as the germanium-silicon and the silicon have the same lattice structure and the lattice constant of the germanium-silicon is larger than that of the silicon at room temperature, lattice mismatch exists between the silicon and the germanium-silicon, so that the stress layer can provide compressive stress for the channel region, and the carrier mobility of the channel region of the P-type transistor is improved. The stress layer material of the corresponding N-type transistor is a carbon-silicon material, and as the lattice constant of the carbon-silicon material at room temperature is smaller than that of silicon, the lattice mismatch between silicon and carbon-silicon can improve the tensile stress to the channel, thereby improving the performance of the N-type transistor.
However, the transistor with the stress layer formed in the prior art has a problem of poor performance.
Disclosure of Invention
The invention provides a method for forming a transistor, which is used for improving the performance of the formed transistor with a stress layer.
In order to solve the above problems, the present invention provides a method for forming a transistor, including:
a substrate is formed, and a first substrate,
forming a gate structure on the substrate, wherein the substrate comprises a first region for forming a first type transistor, and the gate structure positioned in the first region is a first gate structure;
performing a light doping leakage process on the substrate on two sides of the first gate structure to form a first doping layer, wherein the first doping layer contains first type ions;
forming an opening in the first doped layer;
performing diffusion-preventing implantation on the first doping layer exposed from the bottom and the side wall of the opening;
carrying out pre-drying treatment;
filling a first semiconductor material into the opening to form a first stress layer;
and carrying out ion doping on the first stress layer to form a source region or a drain region.
Optionally, in the step of performing diffusion implantation prevention, an inclination angle of the diffusion implantation prevention is in a range of 10 ° to 20 °, and the inclination angle is an included angle between an implantation direction and a normal line of the substrate surface.
Optionally, the first type transistor is a P-type transistor, and in the step of forming the first doping layer, the first type ions are P-type ions.
Optionally, the first type of ions are boron ions.
Optionally, the step of performing diffusion-prevention implantation includes: the implanted ions are carbon ions, fluorine ions or nitrogen ions.
Optionally, in the step of performing the diffusion preventing implantation, an implantation energy of the diffusion preventing implantation is in a range of 5KeV to 20KeV, and an implantation dose is 1.0E13atom/cm2To 3.0E15atom/cm2Within the range.
Optionally, in the step of forming the opening, the opening is shaped like a "sigma".
Optionally, in the step of forming the first stress layer, the first semiconductor material includes a silicon germanium material.
Optionally, the gate structure includes a gate sidewall; after the step of forming the opening and before the step of performing the diffusion preventing implantation, the forming method further includes: and removing part of the thickness of the grid side wall to expose part of the surface of the substrate covered by the grid side wall of the first grid structure.
Optionally, after the step of removing the partial thickness of the gate sidewall, the thickness of the gate sidewall is within a range from 50nm to 300 nm.
Optionally, the step of removing a part of the thickness of the gate sidewall spacer includes: and removing part of the thickness of the grid side wall by adopting a back etching process.
Optionally, the step of performing diffusion-prevention implantation further comprises: a spike anneal process is performed after the ion implantation.
Optionally, the step of performing a pre-baking process includes: and carrying out the pre-drying treatment in a hydrogen pre-drying mode.
Optionally, the step of performing a pre-baking process includes: the temperature of the pre-baking treatment is in the range of 780 ℃ to 850 ℃.
Optionally, in the step of forming the gate structure on the substrate, the substrate further includes a second region for forming a second type transistor, and the gate structure located in the second region is a second gate structure; the forming method further includes: after the step of forming the gate structure on the substrate and before the step of forming the opening, performing a light doping drain process on the substrate on two sides of the second gate structure to form a second doping layer, wherein the second doping layer contains second type ions; after the step of forming the first stress layer, the forming method further comprises: and forming a second stress layer in the second doping layer at two sides of the second gate structure.
Optionally, in the step of forming the second doping layer, the second type ions are N type ions; and in the step of forming the second stress layer, the material of the second stress layer comprises a carbon-silicon material.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, after the opening is formed, diffusion implantation is carried out on the first doping layer exposed from the bottom and the side wall of the opening, ions for preventing diffusion implantation can be combined with the doping ions in the first doping layer to form clusters, so that the loss of the doping ions in the first doping layer in the follow-up pre-baking treatment process is inhibited, the implantation dosage loss of the doping ions in the first doping layer is reduced, and the performance of the formed transistor is improved.
Drawings
FIGS. 1 and 2 are schematic structural diagrams of steps of a transistor forming method in the prior art;
fig. 3 to 9 are schematic structural diagrams of steps of a transistor forming method according to an embodiment of the invention.
Detailed Description
As is clear from the background art, the transistor having the stress layer in the related art has a problem of poor performance. The reason for the poor performance of the transistor is now analyzed in combination with the process of forming the transistor with the stress layer in the prior art:
referring to fig. 1 and 2, schematic structural diagrams of steps of a transistor forming method in the prior art are shown.
As shown in fig. 1, providing a substrate 10, wherein a gate structure 20 is formed on a surface of the substrate 10; forming openings 30 at two sides of the gate structure 20; referring to fig. 2 in combination, a semiconductor material is filled into the opening 30 to form a stress layer 40.
In the prior art, after the gate structure 20 is formed and before the opening 30 is formed, a Light Doped Drain (LDD) implantation is performed on the substrate 10 at two sides of the gate structure 20 to form the first Doped region 11 in the substrate 10 at two sides of the gate structure 20, the implantation of the dopant ions in the first Doped region 11 forms an amorphous state on the substrate surface, and the combination of the dopant ions in the first Doped region 11 and the amorphous state formed on the substrate surface helps to maintain a shallow junction and help to suppress the leakage current of the transistor.
Before filling the semiconductor material to form the stress layer 40, a hydrogen pre-baking process is often performed in the prior art to remove carbon and oxygen remaining on the surface of the substrate 10, so as to clean the surface of the substrate 10 and improve the quality of the formed stress layer 40. However, during the hydrogen pre-baking process, the sidewall and the bottom of the opening 30 expose the first doped region 11, and the hydrogen during the pre-baking process may increase the loss of the dopant ions in the first doped region 11, thereby increasing the resistance of the transistor and causing poor performance of the formed crystal.
In order to solve the technical problem, the invention provides a method for forming a transistor, which comprises the following steps:
forming a substrate, and forming a gate structure on the substrate, wherein the substrate comprises a first region for forming a first type transistor, and the gate structure positioned in the first region is a first gate structure; performing a light doping leakage process on the substrate on two sides of the first gate structure to form a first doping layer, wherein the first doping layer contains first type ions; forming an opening in the first doped layer; performing diffusion-preventing implantation on the first doping layer exposed from the bottom and the side wall of the opening; carrying out pre-drying treatment; filling a first semiconductor material into the opening to form a first stress layer; and carrying out ion doping on the first stress layer to form a source region or a drain region.
According to the invention, after the opening is formed, diffusion implantation is carried out on the first doping layer exposed from the bottom and the side wall of the opening, ions for preventing diffusion implantation can be combined with the doping ions in the first doping layer to form clusters, so that the loss of the doping ions in the first doping layer in the follow-up pre-baking treatment process is inhibited, the implantation dosage loss of the doping ions in the first doping layer is reduced, and the performance of the formed transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 3 to fig. 9, schematic structural diagrams of steps of an embodiment of a transistor forming method provided by the present invention are shown.
Referring to fig. 3 and 4, wherein fig. 4 is a view along direction a in fig. 3, a substrate 100 is formed.
In this embodiment, the transistor is a fin field effect transistor. However, the implementation of the finfet is merely an example, and the present invention is not limited thereto.
In this embodiment, the substrate 100 includes a substrate 101 and a fin portion 102 located on a surface of the substrate 101. Specifically, the step of forming the substrate 100 includes: providing a semiconductor substrate; and etching the semiconductor substrate to form a substrate 101 and a fin part 102 on the surface of the substrate 101.
The semiconductor substrate is used for providing a process operation platform and is also used for etching and forming the fin portion 102. The material of the semiconductor substrate is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the semiconductor substrate may also be other semiconductor materials. The invention is not limited in this regard. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, and therefore the substrate 101 and the fin portion 102 are both made of single crystal silicon.
In other embodiments of the present invention, the semiconductor substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure. Specifically, the semiconductor substrate may include a substrate and a semiconductor layer on a surface of the substrate. The semiconductor layer may be formed on the substrate surface using a selective epitaxial deposition process. The substrate can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate; the material of the semiconductor layer is silicon, germanium, silicon carbide, silicon germanium or the like. The selection of the substrate and the semiconductor layer is not limited, and the substrate suitable for the process requirement or easy integration and the material suitable for forming the fin part can be selected. And the thickness of the semiconductor layer can be controlled through an epitaxial process, so that the height of the formed fin part can be accurately controlled.
The forming of the fin 102 includes: forming a first patterned mask on the surface of the semiconductor substrate, wherein the first patterned mask is used for defining the position and the size of the fin portion 102; and etching the semiconductor substrate by taking the patterned first mask as a mask to form the substrate 101 and the fin part 102 on the surface of the substrate 101.
A patterned first mask is used to define the location and dimensions of the fin 102. The step of forming a patterned first mask includes: forming a first mask material layer on the surface of the semiconductor substrate; forming a first patterning layer on the surface of the first mask material layer; and etching the first mask material layer by taking the first patterning layer as a mask until the surface of the semiconductor substrate is exposed to form a patterned first mask.
The first patterning layer may be a patterned photoresist layer, and is formed by a coating process and a photolithography process. In addition, in order to reduce the feature size of the fins and the distance between adjacent fins, the first patterning layer can be formed by adopting a multi-patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned triple patterning (Self-aligned triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
As shown in fig. 4, the process of etching the semiconductor substrate may be an anisotropic dry etching process. The sidewalls of the formed fin 102 are therefore perpendicular or oblique with respect to the surface of the substrate 101, and when the sidewalls of the fin 102 are oblique with respect to the substrate 101 surface, the bottom dimension of the fin 102 is larger than the top dimension. Specifically, in this embodiment, the sidewall of the fin 102 forms a certain angle with the surface of the substrate 101, and the bottom dimension of the fin 102 is greater than the top dimension.
In this embodiment, the substrate 100 further includes an isolation layer 103 on the surface of the substrate 101 and filled between adjacent fins. The isolation layer 103 functions to electrically isolate the fins 102 from each other and from other semiconductor structures. The top surface of the isolation layer 103 is lower than the top surface of the fin 102 to expose the sidewalls of the fin 102, so that a subsequently formed gate structure can cover the sidewalls of the fin 102.
The forming step of the isolation layer 103 includes: forming an isolation material layer, wherein the isolation material layer is filled between adjacent fins 102, and the top surface of the isolation material layer is higher than the top surface of each fin 102; and removing part of the thickness of the top of the isolation material layer to expose part of the sidewall of the fin 102 to form an isolation layer 103.
With continued reference to fig. 3 and 4, a gate structure 110 is formed on the substrate, the substrate 100 includes a first region 100p for forming a first type transistor, and the gate structure 110 located in the first region 100p is the first gate structure 110 p.
The gate structure 110 includes a gate dielectric layer (not shown) and a gate electrode (not shown) sequentially disposed on a surface of the substrate 100.
In this embodiment, the transistor is a fin field effect transistor. Therefore, the gate structure 110 crosses over the fin 102, and the gate structure 110 is located on a portion of the surface of the isolation layer 103 and also covers a portion of the surface of the top and sidewalls of the fin 102.
The gate dielectric layer is made of a high-K material, and specifically comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide or other materials. The material of the gate electrode may be metal or polysilicon.
The forming step of the gate structure 110 includes: forming a gate material layer on the surface of the substrate 100, wherein the gate material layer comprises a gate dielectric material layer and a gate electrode material layer; a patterned photoresist layer is formed on the surface of the gate material layer, and the gate material layer is etched until the surface of the substrate 100 is exposed by using the patterned photoresist layer as a mask, so as to form a gate structure 110.
Wherein the step of forming the gate material layer comprises: a gate dielectric material layer and a gate electrode material layer are sequentially formed on the surface of the substrate 100 by a chemical vapor deposition, physical vapor deposition or atomic layer deposition process. The patterned photoresist is formed through a coating process and an exposure and development process. And the process for etching the grid material layer is an anisotropic dry etching process.
In order to reduce the size of the gate structure 110 and the size of the formed transistor, the gate structure 110 may also be formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned triple patterning (Self-aligned triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
It should be noted that, since the forming process of the Gate structure may be divided into a "Gate First" process and a "Gate First" process, the "Gate First" process is taken as an example in this embodiment for description, but the invention is not limited thereto. The invention does not limit the sequence of the steps of forming the gate structure 110 and the steps of forming the source region or the drain region of the transistor.
In other embodiments of the present invention, the transistor may be formed using a "gate last" process. Specifically, when a gate structure of the transistor is formed by adopting a gate last process, the gate structure is a dummy gate structure, and a metal material is refilled into the dummy gate structure by removing the dummy gate structure to form a metal gate structure.
The gate structure 110 further includes a gate sidewall spacer 111. The gate sidewall 111 is used for preventing the subsequent process from affecting the channel region of the formed transistor and reducing the source-drain punch-through phenomenon. The gate sidewall spacers 111 may be made of nitride or oxide. In this embodiment, the sidewall spacer 111 is made of silicon nitride.
The substrate 100 includes a first region 100p for forming a first type transistor, and a gate structure 110 located in the first region 100p is a first gate structure 110 p.
In this embodiment, the first region 100P is used to form a P-type transistor, that is, the first type transistor is a P-type transistor, and the gate structure 110 located in the first region 100P is a first gate structure 110P.
The substrate 100 further includes a second region 100n for forming a transistor of a second type, and the gate structure 110 located in the second region 100n is a second gate structure 110 n. In this embodiment, the second region 100N is used to form an N-type transistor, that is, the second-type transistor is an N-type transistor.
Referring to fig. 5, a light-doping drain process is performed on the substrate 100 at two sides of the first gate structure 110p to form a first doping layer 104p, wherein the first doping layer 104p contains first type ions.
The first doped layer 104p is used to form a shallow junction to suppress leakage current of the formed transistor. In this embodiment, the first type transistor is a P-type transistor, so the first doped layer 104P is a P-type doped region, that is, in the step of forming the first doped layer 104P, the first type ions in the first doped layer 104P are P-type ions.
Specifically, the P-type ions are boron ions. Since the atomic weight of boron ions is small, the boron ions are prone to diffusion during semiconductor processing resulting in implant dose loss.
In this embodiment, with the first gate structure 110p as a mask, a first lightly doped drain implantation is performed on the top of the fin 102 on both sides of the first gate structure 110p, so as to form a first doped layer 104p in the fin 102 in the first region 100 p.
Specifically, the process parameters of the first lightly doped drain implantation are as follows: the process gas comprises ion implantation with an implantation energy in the range of 1KeV to 6KeV and an implantation dose of 5.0E13atom/cm2To 2.0E15atom/cm2In the range of 10 to 20, the implantation angle being the angle between the implantation direction and the substrate surface of the substrate 100.
In this embodiment, the substrate 100 further includes a second region 100N for forming an N-type transistor. Accordingly, the forming method further includes: and performing a light doping drain process on the substrate 100 at two sides of the second gate structure 110n to form a second doping layer 104n, wherein the second doping layer 104n contains second type ions.
The second doped layer 104n is used to form a shallow junction to suppress leakage current of the formed transistor. In this embodiment, the second region 100N is used to form an N-type transistor, so the second doped layer 104N is an N-type doped region, that is, the second type ions in the second doped layer 104N are N-type ions. Specifically, the N-type ions may be arsenic ions.
In this embodiment, with the second gate structure 110n as a mask, a second lightly doped drain implantation is performed on the top of the fin 102 on both sides of the second gate structure 110n, so as to form a second doped layer 104n in the fin 102 in the second region 100 n.
Specifically, the process parameters of the second lightly doped drain implantation are as follows: the process gas comprises ion implantation with an implantation energy in the range of 1KeV to 8KeV and an implantation dose of 4.0E13atom/cm2To 2.0E15atom/cm2In the range of 10 to 20, the implantation angle being the angle between the implantation direction and the substrate surface of the substrate 100.
It should be noted that, as the size of a semiconductor device is reduced, the channel size of a transistor is shorter and shorter, bottom punch-through (punch through) is likely to occur at the bottom of the source region and the drain region of the transistor, and a leakage current is generated at the bottom of the source region and the drain region. Particularly for fin field effect transistors, the probability of punch-through occurring between the source and drain regions within the fin is also greater due to the small size of the fin.
In order to overcome the bottom punch-through phenomenon, in this embodiment, after the step of forming the gate structure 110 and before the step of forming the first doped layer 104p and the second doped layer 104n, the forming method further includes forming a first punch-through prevention layer (not shown) in the fin 102 of the first region 100p and forming a second punch-through prevention layer (not shown) in the fin 102 of the second region 100 n. Specifically, the substrate 100 of the first region 100p and the second region 100n may be subjected to a punch-through prevention implantation to form the first punch-through prevention layer and the second punch-through prevention layer, respectively.
Referring to fig. 6, an opening 120 is formed in the first doped layer 104 p.
The opening 120 is used for filling a semiconductor material to form a stress layer, so as to form a raised source region or a raised drain region. In this embodiment, the transistor is a fin field effect transistor, and therefore, the opening 120 is located in the fin 102 at two sides of the first gate structure 110 p.
In addition, the first region 100P is used to form a P-type transistor. Therefore, in the step of forming the opening 120, the shape of the opening 120 is "Σ" shape, and the stress layer formed by subsequently filling the opening 120 with the "Σ" shape can have a tip protrusion in the channel region, so that a larger compressive stress is introduced in the channel region, which can be beneficial to improving the mobility of carriers in the channel region.
Since the opening 120 is located in the first doped layer 104p, the bottom and the sidewall of the opening 120 are exposed out of the first doped layer 104 p. Therefore, in the subsequent pre-baking process for removing the surface impurities, the adopted hydrogen gas is easy to react with the doping ions in the first doping layer 104p, so that the implantation dose of the first doping layer 104p is lost, and the performance of the formed device is affected.
It should be noted that, in order to avoid the influence of the semiconductor process performed on the first region 100p on the second region 100n, in this embodiment, a mask layer covering the second region is further formed before the step of forming the opening 120. The material of the mask layer may be photoresist.
Referring to fig. 7, the first doping layer 104p exposed at the bottom and the sidewall of the opening 120 is implanted with a diffusion prevention implant.
In this embodiment, the first type transistor is a P-type transistor, and therefore the doping ions in the first doping layer 104P are P-type ions, specifically, boron ions. Therefore, the ions for preventing diffusion implantation are carbon ions, nitrogen ions or fluorine ions.
It should be noted that, in this embodiment, the gate structure 110 further includes a gate sidewall 111 (as shown in fig. 4). Therefore, after the step of forming the opening 120 and before the step of performing the diffusion preventing implantation, the forming method further includes: removing a part of the thickness of the gate sidewall 111 of the gate structure 110 to expose a part of the surface of the substrate 100 covered by the gate sidewall 111 of the first gate structure 110p, so as to expose more of the first doping layer 104p for performing anti-diffusion implantation.
Specifically, a partial thickness of the gate sidewall 111 may be removed by etching back. After the etching back process, the thickness of the gate sidewall 111 is within a range of 50nm to 300 nm.
The ions injected by diffusion prevention can be combined with the doped ions in the first doped layer 104p to form a cluster with lower free energy, so that the diffusion of the doped ions in the first doped layer 104p is inhibited, the reaction of the doped ions and hydrogen in the subsequent pre-baking process is avoided, and the injection dose loss of the first doped layer 104p is reduced. Thereby improving the performance of the resulting device.
Specifically, in the step of performing the anti-diffusion implantation, the energy of the anti-diffusion implantation is in the range of 5KeV to 20KeV, and the implantation dose is 1.0E13atom/cm2To 3.0E15atom/cm2Within the range. In addition, since the opening 120 is a "Σ" shaped opening, the tilt angle of the diffusion preventing implant is in the range of 10 ° to 20 °, and the tilt angle is the angle between the implant direction and the normal of the surface of the substrate 100, so that the ions of the diffusion preventing implant can well enter the first doping layer 104 p.
In this embodiment, the step of performing the first diffusion preventing implantation further includes: a spike anneal process is performed to activate the diffusion-resistant implanted ions to combine them with the dopant ions in the first doped layer 104 p.
Referring to fig. 8, a pre-bake process is performed.
The pre-baking treatment is used to remove residual carbon atoms and oxygen atoms on the sidewall and bottom surface of the opening 120, and provide a clean process surface for subsequent epitaxial growth formation, so as to improve the quality of the formed stress layer. Specifically, the pre-baking treatment may be performed by using a hydrogen pre-baking method. In this embodiment, the temperature value of the pre-baking process is in the range of 780 ℃ to 850 ℃.
During the hydrogen pre-baking process, the ions implanted for diffusion prevention and the doped ions in the first doped layer 104p can combine to form clusters, so that the loss of the implantation dose of the doped ions in the first doped layer 104p can be suppressed, and the performance of the formed device can be improved.
Referring to fig. 9, a first semiconductor material is filled into the opening 120 to form a first stress layer 130 p.
The first stress layer 130p is used to form a source region or a drain region of the first region 100p transistor. Specifically, the first region 100P is used to form a P-type transistor, and the opening 120 is a "sigma" shaped opening, so that the first semiconductor material is a germanium-silicon material, that is, the first stress layer 130P is made of a germanium-silicon material, and the opening 120 may be filled with the germanium-silicon material by epitaxial growth to form the first stress layer 130P. The middle part of the sigma-shaped germanium-silicon stress layer is provided with a tip protrusion pointing to the channel region, the germanium-silicon material with the tip protrusion is closer to the channel region, larger compressive stress is introduced into the channel region, and the mobility of carriers in the channel can be improved more favorably.
In this embodiment, the substrate 100 further includes a second region 100N for forming an N-type transistor, and after the step of forming the first stress layer 130p, the forming method further includes: and forming a second stress layer 130n in the second doped layer 104n on two sides of the second gate structure 110 n.
The second stress layer 130n is used for forming a source region or a drain region of the second area transistor. Specifically, the step of forming the second stress layer 130n includes: etching the fin parts at two sides of the first gate structure 110n by taking the second gate structure 110n as a mask, and forming a second opening in the second doping layer 104 n; and filling a second semiconductor material into the second opening through an epitaxial process to form the second stress layer 130 n.
Since the second region 100N is used for forming an N-type transistor, the second stress layer 130N is square, and the second semiconductor material filling the second stress layer 130N includes a carbon-silicon material, so as to introduce a tensile stress into the channel region below the second gate structure 110N, and improve the mobility of carriers in the channel.
With continued reference to fig. 9, the first stress layer 130p is ion doped to form a source or drain region
Specifically, the first region 100P is used for forming a P-type transistor, so the step of performing ion doping includes: p-type ions are implanted into the first stress layer 130P to form a source region or a drain region of the P-type transistor.
In this embodiment, the substrate 100 further includes a second region 100N for forming an N-type transistor, and a second stress layer 130N is formed in the second region 100N, so that the step of performing ion doping further includes: and injecting N-type ions into the second stress layer 130N to form a source region or a drain region of the N-type transistor.
In summary, after the opening is formed, diffusion implantation is performed on the first doping layer exposed at the bottom and the side wall of the opening, and ions for preventing diffusion implantation can be combined with the doping ions in the first doping layer to form a cluster, so that loss of the doping ions in the first doping layer in a subsequent pre-baking treatment process is inhibited, the implantation dose loss of the doping ions in the first doping layer is reduced, and the performance of the formed transistor is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of forming a transistor, comprising:
a substrate is formed, and a first substrate,
forming a gate structure on the substrate, wherein the substrate comprises a first region for forming a first type transistor, and the gate structure positioned in the first region is a first gate structure;
performing a light doping leakage process on the substrate on two sides of the first gate structure to form a first doping layer, wherein the first doping layer contains first type ions;
forming an opening in the first doped layer;
performing diffusion-preventing implantation on the first doping layer exposed from the bottom and the side wall of the opening;
the step of performing an anti-diffusion implant further comprises: performing spike annealing treatment after ion implantation;
carrying out pre-drying treatment;
filling a first semiconductor material into the opening to form a first stress layer;
and carrying out ion doping on the first stress layer to form a source region or a drain region.
2. The method of claim 1, wherein the step of performing the anti-diffusion implant is performed at an angle in a range of 10 ° to 20 ° relative to a normal to the substrate surface.
3. The method according to claim 1, wherein the first type transistor is a P-type transistor, and wherein the step of forming the first doped layer includes forming the first type ions as P-type ions.
4. The method of forming of claim 1, wherein the first type of ions are boron ions.
5. The method of forming as claimed in claim 4 wherein the step of performing an anti-diffusion implant comprises: the implanted ions are carbon ions, fluorine ions or nitrogen ions.
6. The method of claim 5, wherein the step of performing an anti-diffusion implant has an implant energy in a range of 5KeV to 20KeV and an implant dose of 1.0E13atom/cm2To 3.0E15atom/cm2Within the range.
7. The method of claim 3, wherein in the step of forming the opening, the opening is shaped like a "sigma".
8. The method of claim 3, wherein in the step of forming the first stress layer, the first semiconductor material comprises a silicon germanium material.
9. The method of forming of claim 1, wherein the gate structure comprises a gate sidewall;
after the step of forming the opening and before the step of performing the diffusion preventing implantation, the forming method further includes: and removing part of the thickness of the grid side wall to expose part of the surface of the substrate covered by the grid side wall of the first grid structure.
10. The method of claim 9, wherein after the step of removing the portion of the thickness of the gate sidewall spacers, the thickness of the gate sidewall spacers is in a range of 50nm to 300 nm.
11. The method of claim 9, wherein the step of removing a portion of the thickness of the gate sidewall spacers comprises: and removing part of the thickness of the grid side wall by adopting a back etching process.
12. The method of forming as claimed in claim 1, wherein said step of performing a pre-bake process comprises: and carrying out the pre-drying treatment in a hydrogen pre-drying mode.
13. The method of forming as claimed in claim 12, wherein said step of performing a pre-bake process comprises: the temperature of the pre-baking treatment is in the range of 780 ℃ to 850 ℃.
14. The method of claim 1, wherein in the step of forming the gate structure on the substrate, the substrate further comprises a second region for forming a transistor of a second type, the gate structure in the second region being a second gate structure;
the forming method further includes:
after the step of forming the gate structure on the substrate and before the step of forming the opening, performing a light doping drain process on the substrate on two sides of the second gate structure to form a second doping layer, wherein the second doping layer contains second type ions;
after the step of forming the first stress layer, the forming method further comprises: and forming a second stress layer in the second doping layer at two sides of the second gate structure.
15. The forming method according to claim 14, wherein in the step of forming the second doping layer, the second type ions are N type ions;
and in the step of forming the second stress layer, the material of the second stress layer comprises a carbon-silicon material.
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