CN108257916B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN108257916B
CN108257916B CN201611242214.5A CN201611242214A CN108257916B CN 108257916 B CN108257916 B CN 108257916B CN 201611242214 A CN201611242214 A CN 201611242214A CN 108257916 B CN108257916 B CN 108257916B
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forming
source
substrate
drain doped
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CN108257916A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped regions positioned in the substrate at two sides of the gate structure, and an interlayer dielectric layer positioned on the substrate and covering the top of the gate structure, and the substrate comprises a first region for forming a P-type device and a second region for forming an N-type device; forming a first contact opening exposing the source-drain doped region in the interlayer dielectric layers on two sides of the grid structure; carrying out a P-type doping isolation Schottky doping process on the source-drain doped regions exposed out of the first contact openings in the first region and the second region; forming a metal silicide layer at the bottom of the first contact opening; a first contact hole plug is formed within the first contact opening. According to the invention, the doping concentration of the source-drain doped region of the second region can be adjusted, so that a photomask is avoided when a P-type doping isolation Schottky doping process is carried out, the reduction of the process cost is realized, and the influence on an N-type device is small.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of integrated circuit manufacturing technology, the critical dimension of the device becomes smaller, and accordingly, many problems occur. For example, the contact resistance between the contact hole plug and the source/drain doped region is increased, which results in a decrease in the response speed of the device, a delay in the signal generation, a decrease in the driving current, and a deterioration in the performance of the semiconductor device.
In order to reduce the contact resistance between the contact hole plug and the source-drain doped region, a metal silicide process is introduced, and the metal silicide has lower resistivity, so that the contact resistance can be obviously reduced, and the driving current is improved.
With the continuous reduction of the key size of the device, the contact resistance is difficult to meet the process requirement after the metal silicide process is adopted, so that a doped isolated Schottky (DSS) injection process is introduced at present; the source and drain doped regions are subjected to a DSS (direct sequence deposition) injection process to reduce the Schottky Barrier Height (SBH) of the source and drain doped regions and the channel region, so that the contact resistance is reduced, and the driving current is further improved.
Although the DSS implantation process can effectively reduce the schottky barrier height, the process cost is high.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can effectively reduce the height of a Schottky barrier and reduce the process cost.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped regions positioned in the substrates at two sides of the gate structure, and an interlayer dielectric layer positioned on the substrate and covering the top of the gate structure, and the substrate comprises a first region for forming a P-type device and a second region for forming an N-type device; forming a first contact opening exposing the source-drain doped region in the interlayer dielectric layers on two sides of the grid structure; carrying out a P-type doping isolation Schottky doping process on the source-drain doped region exposed out of the first contact opening in the first region and the second region; after the P-type doping isolation Schottky treatment is finished, a metal silicide layer is formed at the bottom of the first contact opening; and after the metal silicide layer is formed, filling a conductive material into the first contact opening, and forming a first contact hole plug in the first contact opening.
Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a substrate, a grid structure positioned on the substrate, source-drain doped regions positioned in the substrates at two sides of the grid structure and an interlayer dielectric layer positioned on the substrates and covering the top of the grid structure, wherein the substrate comprises a first region with a P-type device and a second region with an N-type device; and the contact opening is positioned in the interlayer dielectric layers at two sides of the grid structure and exposes the source-drain doped region, wherein the source-drain doped region exposed by the contact opening in the first region and the second region is subjected to a P-type doping isolation Schottky doping process in the same step.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the step of forming the substrate, the substrate comprises a substrate, a grid structure positioned on the substrate, source and drain doped regions positioned in the substrates at two sides of the grid structure and an interlayer dielectric layer positioned on the substrates and covering the top of the grid structure, wherein the substrate comprises a first region for forming a P-type device and a second region for forming an N-type device; after first contact openings exposing the source-drain doped regions are formed in the interlayer dielectric layers on the two sides of the grid structure, carrying out a P-type doping isolation Schottky doping process on the source-drain doped regions exposed by the first contact openings in the first region and the second region; that is to say, when the P-type doping isolation schottky doping process is performed, a pattern layer for protecting the second region is not formed in the second region, but the P-type doping isolation schottky doping process is performed on the source drain doping regions of the first region and the second region at the same time, the P-type doping isolation schottky doping process is used for reducing schottky barrier heights of the source drain doping regions and the channel region of the first region, and when the source drain doping regions of the second region are formed, the doping ion concentration of the source drain doping regions of the second region is correspondingly adjusted according to the parameters of the P-type doping isolation schottky doping process so as to reduce the influence on the performance of an N-type device; therefore, according to the scheme provided by the invention, on one hand, the Schottky barrier height of the source-drain doped region and the channel region of the first region can still be reduced, so that the contact resistance of the first region is reduced, and the driving current of the P-type device is further improved; on the other hand, compared with the scheme of only carrying out the P-type doping isolation Schottky doping process on the source-drain doped region of the first region, the scheme provided by the invention can avoid the use of a photomask, realize the reduction of the process cost and has small influence on an N-type device.
In an alternative, after forming the first contact opening and before forming the metal silicide layer, the forming method further includes: performing pre-amorphization treatment on the source-drain doped regions in the first region and the second region; through the pre-amorphization treatment, the Schottky barrier heights of the source-drain doped region and the channel region of the first region can be reduced, and the Schottky barrier heights of the source-drain doped region and the channel region of the second region can also be reduced, so that the contact resistance of the first region and the second region can be reduced, and the driving currents of a P-type device and an N-type device can be improved; in addition, the pre-amorphization treatment is also beneficial to improving the forming quality uniformity of the metal silicide layer.
The semiconductor structure comprises a contact opening, wherein the contact opening is positioned in an interlayer dielectric layer at two sides of a grid structure and exposes a source-drain doped region, and the source-drain doped region exposed by the contact opening in a first region and a second region is subjected to a P-type doping isolation Schottky doping process in the same step; therefore, by adjusting the doping concentration of the source-drain doped region of the second region in the semiconductor structure to a reasonable value, the P-type doping isolation schottky doping process can be avoided from being additionally adopted by a photomask, so that the manufacturing cost of the semiconductor structure is low, and the influence on an N-type device is small; and simultaneously, the Schottky barrier height of the source-drain doped region and the channel region of the first region can still be reduced, so that the contact resistance of the first region is reduced, and the driving current of the P-type device is further improved.
Drawings
Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, although the Schottky barrier height can be effectively reduced by the doped isolated Schottky (DSS) implantation process, the process cost is high. The reason for this analysis is:
when DSS implantation technology is carried out, the ion type and the P type implanted into the source drain doped region of the N type regionThe types of ions implanted into the region source-drain doped regions are different, for example, when the N-type DSS implantation is performed on the N-type region source-drain doped region, the ion implantation source is P or As, and when the P-type DSS implantation is performed on the P-type region source-drain doped region, the ion implantation source is B or BF2Therefore, 2 masks are needed to perform the N-type DSS implantation and the P-type DSS implantation respectively, which results in a high process cost.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, wherein in the step of forming a substrate, the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped regions positioned in the substrates at two sides of the gate structure, and an interlayer dielectric layer positioned on the substrate and covering the top of the gate structure, wherein the substrate comprises a first region for forming a P-type device and a second region for forming an N-type device; and after first contact openings exposing the source-drain doped regions are formed in the interlayer dielectric layers on the two sides of the grid structure, carrying out a P-type doping isolation Schottky doping process on the source-drain doped regions exposed by the first contact openings in the first region and the second region. That is to say, when the P-type doping isolation schottky doping process is performed, a pattern layer for protecting the second region is not formed in the second region, but the P-type doping isolation schottky doping process is performed on the source drain doping regions of the first region and the second region at the same time, the P-type doping isolation schottky doping process is used for reducing schottky barrier heights of the source drain doping regions and the channel region of the first region, and when the source drain doping regions of the second region are formed, the doping ion concentration of the source drain doping regions of the second region is correspondingly adjusted according to the parameters of the P-type doping isolation schottky doping process so as to reduce the influence on the performance of an N-type device; therefore, according to the scheme provided by the invention, on one hand, the Schottky barrier height of the source-drain doped region and the channel region of the first region can still be reduced, so that the contact resistance of the first region is reduced, and the driving current of the P-type device is further improved; on the other hand, compared with the scheme of only carrying out the P-type doping isolation Schottky doping process on the source-drain doped region of the first region, the scheme provided by the invention can avoid the use of a photomask, realize the reduction of the process cost and has small influence on an N-type device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
With reference to fig. 1 to 5, fig. 1 is a perspective view (only two fin portions are illustrated), fig. 2 is a schematic cross-sectional structure view of a cutting line perpendicular to an extending direction of a fin portion (as illustrated by a cutting line AA1 in fig. 1), fig. 4 is a schematic cross-sectional structure view of a cutting line along an extending direction of a fin portion (as illustrated by a cutting line BB1 in fig. 1), a base is formed, the base includes a substrate 100, a gate structure (not labeled) located on the substrate 100, source and drain doped regions (not labeled) located in the bases on both sides of the gate structure, and an interlayer dielectric layer 103 (as illustrated in fig. 5) located on the base and covering a top of the gate structure, and the substrate 100 includes a first region I for forming a P-type device and a second region II for forming an N-type device.
The steps for forming the substrate will be described in detail below with reference to the accompanying drawings.
Referring collectively to fig. 1 and 2, the substrate 100 provides a process platform for subsequent formation of semiconductor devices.
In this embodiment, the substrate is used to form a finfet, and therefore the substrate further includes a discrete fin (not shown) on the substrate 100. In other embodiments, the substrate is used to form a planar transistor, and accordingly, the substrate is a planar substrate.
In this embodiment, the substrate 100 includes a first region I for forming a P-type device and a second region II for forming an N-type device. Accordingly, the fin on the first region I substrate 100 is a first fin 110 (as shown in fig. 2), and the fin on the second region II substrate 100 is a second fin 120 (as shown in fig. 2). In other embodiments, the substrate may also be used to form only P-type devices or only N-type devices.
The first region I and the second region II may be adjacent regions, or may not be adjacent regions. In this embodiment, the first region I and the second region II are adjacent regions.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin is the same as the material of the substrate 100. In this embodiment, the fin portion is made of silicon, that is, the first fin portion 110 and the second fin portion 120 are made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Specifically, the process steps for forming the substrate 100 and the fin portion include: providing an initial substrate; forming a patterned fin mask layer 200 on the initial substrate surface (as shown in fig. 2); and etching the initial substrate by taking the fin part mask layer 200 as a mask, taking the etched residual initial substrate as a substrate 100, and taking a protrusion on the substrate 100 as a fin part.
In this embodiment, after the substrate 100 and the fin portion are formed, the fin portion mask layer 200 on the top of the fin portion is remained. The fin mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the fin mask layer 200 is used for defining a stop position of the planarization process and plays a role in protecting the top of the fin.
With reference to fig. 3, it should be noted that after the substrate 100 and the fin portion are formed, the forming method further includes: and forming an isolation structure 101 on the substrate 100 with the exposed fin portion, wherein the isolation structure 101 covers part of the side wall of the fin portion, and the top of the isolation structure 101 is lower than the top of the fin portion.
The isolation structure 101 serves as an isolation structure of a semiconductor device and is used for isolating adjacent devices and fins. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Specifically, the process steps for forming the isolation structure 101 include: filling an isolation film on the substrate 100 with the exposed fin, wherein the top of the isolation film is higher than the top of the fin mask layer 200 (shown in fig. 2); grinding to remove the isolation film higher than the top of the fin mask layer 200; etching back the residual isolation film with partial thickness to form an isolation structure 101; the fin mask layer 200 is removed.
Referring to fig. 4, a gate structure (not labeled) is formed on the substrate 100.
In this embodiment, the base includes a substrate 100 and a discrete fin portion located on the substrate 100, so that the gate structure crosses over the fin portion and covers a portion of a sidewall surface and a top surface of the fin portion.
Specifically, the gate structure in the first region I is a first gate structure 610 (as shown in fig. 4), and the first gate structure 610 spans the first fin 110 and covers a portion of the sidewall surface and the top surface of the first fin 110; the gate structure in the second region II is a second gate structure 620 (as shown in fig. 4), and the second gate structure 620 spans the second fin 120 and covers a portion of the sidewall surface and the top surface of the second fin 120.
In this embodiment, the gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate), so before forming the gate structure, the forming method further includes: forming a dummy gate structure (dummy gate) which crosses the fin part and covers the top surface and the side wall surface of the fin part; forming source drain doped regions (not marked) in the fin parts at two sides of the pseudo gate structure; after the source-drain doped region is formed, forming a bottom dielectric layer 102 (as shown in fig. 4) on the substrate exposed out of the dummy gate structure, wherein the bottom dielectric layer 102 covers the source-drain doped region, and the bottom dielectric layer 102 is exposed out of the top of the dummy gate structure; after the bottom dielectric layer 102 is formed, the dummy gate structure is removed, and an opening (not shown) is formed in the bottom dielectric layer 102.
The substrate 100 includes a first region I and a second region II, and correspondingly, the source-drain doped regions in the first fin portions 110 on both sides of the dummy gate structure of the first region I are first source-drain doped regions (not shown), and the source-drain doped regions in the second fin portions 120 on both sides of the dummy gate structure of the second region are second source-drain doped regions (not shown); the opening in the first region I bottom dielectric layer 102 is a first opening (not shown), and the opening in the second region II bottom dielectric layer 102 is a second opening (not shown).
The dummy gate structure occupies a spatial position for forming the first gate structure 610 and the second gate structure 620. The pseudo gate structure is a single-layer structure or a laminated structure. The dummy gate structure comprises a dummy gate layer; or the pseudo gate structure comprises a pseudo oxide layer and a pseudo gate layer positioned on the pseudo oxide layer. The pseudo gate layer is made of polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the pseudo oxide layer is made of silicon oxide or silicon oxynitride.
The first source-drain doped region is used as a source region or a drain region of a subsequently formed P-type device, and the second source-drain doped region is used as a source region or a drain region of a subsequently formed N-type device. In this embodiment, the first source-drain doped region and the second source-drain doped region are formed by a selective Epitaxial Process (EPI).
Specifically, the step of forming the first source-drain doped region includes: forming a first epitaxial layer 112 (as shown in fig. 4) in the first fin portion 110 on both sides of the first region I pseudo-gate structure, and in the process of forming the first epitaxial layer 112, in-situ self-doping P-type ions to form the first source drain doped region. The material of the first epitaxial layer 112 may be Si or SiGe, and the P-type ions include one or more of B, Ga and In. In this embodiment, the material of the first epitaxial layer 112 is Si; the P-type ions are Ge ions, namely the doping ions of the first source drain doping region are Ge ions. The doping concentration of Ge ions is determined according to the actual process requirements, and in the present embodiment, the content of Ge ions in atomic percentage is 35% to 65%.
Specifically, the step of forming the second source-drain doped region includes: forming a second epitaxial layer 122 (as shown in fig. 4) in the second fin portion 120 on two sides of the second region II pseudo gate structure, and in the process of forming the second epitaxial layer 122, in-situ self-doping N-type ions to form the second source-drain doped region. The material of the second epitaxial layer 122 may be Si or SiC, and the N-type ions include one or both of P and As. In this embodiment, the material of the second epitaxial layer 122 is Si; the N-type ions are P, namely the doping ions of the second source drain doping region are P ions.
It should be noted that the subsequent steps include performing a P-type doped isolated Schottky (DSS) doping process on the first source/drain doped region, where the doping ions of the doping process are P-type ions, and the doping process is used to reduce the Schottky Barrier Height (SBH) of the first source/drain doped region and the channel region of the P-type device; in order to save a photomask, the second source-drain doped region is exposed in the environment of the P-type doping isolation schottky doping process, namely the second source-drain doped region is influenced by P-type ion doping, so that in order to reduce the influence on the electrical performance of a subsequently formed N-type device, the P-ion doping concentration of the second source-drain doped region is increased to a reasonable value according to the actual process requirement and the doping concentration of the subsequent P-type doping isolation schottky doping process. In this example, the doping concentration of P ions was 1E21atom/cm3To 3E21atom/cm3。
It should be further noted that by increasing the P ion doping concentration of the second source-drain doped region, the schottky barrier height of the first source-drain doped region and the channel region is also favorably reduced, so that the contact resistance of the second region II is favorably reduced, and the driving current of the N-type device is further improved.
In this embodiment, the first source-drain doped region and the second source-drain doped region are formed by a selective epitaxial process. In other embodiments, the first source-drain doped region and the second source-drain doped region may also be formed in a non-epitaxial layer manner by ion doping, that is, the first source-drain doped region may be formed by directly performing an ion doping process on the first fin portions on both sides of the first region pseudo gate structure, and the second source-drain doped region may be formed by directly performing an ion doping process on the second fin portions on both sides of the second region pseudo gate structure.
The material of the bottom dielectric layer 102 is an insulating material. In this embodiment, the bottom dielectric layer 102 is made of silicon oxide. In other embodiments, the material of the bottom dielectric layer may also be silicon nitride or silicon oxynitride.
It should be noted that, after the dummy gate structure is formed and before the source-drain doped region is formed, the forming method further includes: and forming a side wall 130 on the side wall of the pseudo gate structure. The sidewall spacers 130 may be used to define the positions of the first source-drain doped region and the second source-drain doped region. The material of the sidewall 130 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 130 may be a single-layer structure or a stacked structure. In this embodiment, the sidewall spacer 130 has a single-layer structure, and the material of the sidewall spacer 130 is silicon nitride.
In this embodiment, the first gate structure 610 is formed in the first opening (not shown), the second gate structure 620 is formed in the second opening (not shown), and the tops of the first gate structure 610 and the second gate structure 620 are flush with the top of the bottom dielectric layer 102.
Specifically, the step of forming the first gate structure 610 and the second gate structure 620 includes: forming a gate dielectric layer 310 on the side wall and the bottom of the first opening and the side wall and the bottom of the second opening, wherein the gate dielectric layer 310 also covers the top of the bottom dielectric layer 102; forming a cap layer 410 on the gate dielectric layer 310; forming a P-type work function layer 320 on the cap layer 410; removing the P-type work function layer 320 of the second region II to expose the cap layer 410; forming an N-type work function layer 330 on the P-type work function layer 320 of the first region I and the cap layer 410 of the second region II; forming a gate blocking layer 420 on the N-type work function layer 330; forming a metal layer 510 on the gate barrier layer 420 to fill the first and second openings; removing the metal layer 510 higher than the bottom dielectric layer 102, and also removing the gate blocking layer 420, the N-type work function layer 330, the P-type work function layer 320, the cap layer 410 and the gate dielectric layer 310 higher than the bottom dielectric layer 102; the gate dielectric layer 310, the cap layer 410, the P-type work function layer 320, the N-type work function layer 330, the gate blocking layer 420 and the metal layer 510 in the first opening are used to form the first gate structure 610, and the gate dielectric layer 310, the cap layer 410, the N-type work function layer 330, the gate blocking layer 420 and the metal layer 510 in the second opening are used to form the second gate structure 620.
Correspondingly, the first source-drain doped region is located in the first fin portion 110 at two sides of the first gate structure 610, and the second source-drain doped region is located in the second fin portion 120 at two sides of the second gate structure 620.
In this embodiment, the gate dielectric layer 310 includes an Interfacial layer (I L, Interfacial L eye) (not labeled) and a high-k gate dielectric layer (not labeled) on the surface of the Interfacial layer.
The interface layer provides a good interface foundation for forming the high-k gate dielectric layer, so that the quality of the high-k gate dielectric layer is improved, the interface state density between the high-k gate dielectric layer and the fin portion is reduced, and adverse effects caused by direct contact of the high-k gate dielectric layer and the fin portion are avoided. The interface layer is made of silicon oxide or silicon oxynitride.
The high-k gate dielectric layer is made of a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
The cap layer 410 not only protects the gate dielectric layer 310, but also prevents metal ions of the N-type work function layer 330 and the P-type work function layer 320 from diffusing into the gate dielectric layer 310; the cap layer 410 can also prevent oxygen ions in the gate dielectric layer 310 from diffusing into the N-type work function layer 330 and the P-type work function layer 320, so as to avoid the problem of increasing the oxygen vacancy content in the gate dielectric layer 310. In this embodiment, the capping layer 410 is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN or TaN.
In one aspect, the gate blocking layer 420 is configured to protect the N-type work function layer 330 and the P-type work function layer 320, and prevent easily-diffused ions in the metal layer 510 from diffusing into the N-type work function layer 330 and the P-type work function layer 320; on the other hand, the deposition effect of the metal layer 510 on the gate blocking layer 420 is better, and the gate blocking layer 420 can improve the formation quality of the metal layer 510. In this embodiment, the gate blocking layer 420 is made of TiN. In other embodiments, the material of the gate barrier layer may also be TiSiN.
The material of the P-type work function layer 320 is a P-type work function material having a work function in a range of 5.1eV to 5.5eV, for example, 5.2eV, 5.3eV, or 5.4 eV. The P-type work function layer 320 is made of one or more of Ta, TiN, TaN, TaSiN, or TiSiN, and the P-type work function layer 320 may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The material of the N-type work function layer 330 is an N-type work function material, and the work function of the N-type work function material ranges from 3.9eV to 4.5eV, such as 4eV, 4.1eV, or 4.3 eV. The material of the N-type work function layer 330 may be one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN, and the N-type work function layer 330 may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the metal layer 510 is made of W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.
Referring to fig. 5, an interlayer dielectric layer 103 is formed on the substrate, wherein the interlayer dielectric layer 103 covers the top of the gate structure (not shown) and the top of the bottom dielectric layer 102.
Specifically, the step of forming the interlayer dielectric layer 103 includes: forming an interlayer dielectric film covering the top of the gate structure (not labeled) and the top of the bottom dielectric layer 102; and carrying out a planarization process on the interlayer dielectric film to form an interlayer dielectric layer 103, wherein the top of the interlayer dielectric layer 103 is higher than the top of the gate structure.
The interlayer dielectric layer 103 is made of an insulating material. In this embodiment, in order to improve process compatibility, the material of the interlayer dielectric layer 103 is the same as that of the bottom dielectric layer 102, and the material of the interlayer dielectric layer 103 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be silicon nitride or silicon oxynitride.
In other embodiments, the gate structure may be formed by a process of forming a high-k gate dielectric layer first and forming a gate electrode layer (high-k first gate first). Accordingly, the step of forming the substrate comprises: providing an initial substrate; etching the initial substrate to form a substrate and a discrete fin part on the substrate, wherein the substrate comprises a first area for forming a P-type device and a second area for forming an N-type device; forming a grid electrode structure which stretches across the fin part and covers the top surface and the side wall surface of the fin part; forming source and drain doped regions in the fin parts on two sides of the grid structure; and forming an interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the top of the interlayer dielectric layer is higher than that of the grid structure.
Referring to fig. 6, a first contact opening 155 exposing the source/drain doped region (not labeled) is formed in the interlayer dielectric layer 103 on both sides of the gate structure (not labeled).
The first contact opening 155 of the first region I exposes the first source-drain doped regions on both sides of the first gate structure 610, and the first contact opening 155 of the second region II exposes the second source-drain doped regions on both sides of the second gate structure 620. In this embodiment, the first contact opening 155 of the first region I penetrates through the interlayer dielectric layer 103 and the bottom dielectric layer 102 of the first region I, and the first contact opening 155 of the second region II penetrates through the interlayer dielectric layer 103 and the bottom dielectric layer 102 of the second region II.
The first contact opening 155 provides a spatial location for a contact hole plug to be subsequently formed to contact the first source drain doped region and the second source drain doped region. Specifically, the interlayer dielectric layer 103 and the bottom dielectric layer 102 above the first source-drain doped region and above the second source-drain doped region are removed by means of dry etching.
In this embodiment, the first contact opening 155 is formed by a non-self-aligned process. Therefore, before the interlayer dielectric layer 103 and the bottom dielectric layer 102 are etched, a pattern layer is also formed on part of the interlayer dielectric layer 103; in the step of forming the first contact opening 155, etching is performed with the pattern layer as a mask. In other embodiments, the first contact opening may also be formed by a self-aligned process.
It should be further noted that, during the process of forming the first contact opening 155, a partial thickness of the first epitaxial layer 112 and the second epitaxial layer 122 is also removed.
Referring to fig. 7, a P-type doping isolation schottky doping process is performed on the source and drain doped regions (not shown) exposed by the first contact openings 155 in the first region I and the second region II.
The P-type doping isolation Schottky doping process is used for doping P-type ions into the first source drain doping region; and when a metal layer is deposited on the first source drain doped region to form a metal silicide (silicide) layer, in the process of forming the metal silicide layer by reacting the metal layer with silicon through an annealing process, the annealing process also drives the P-type ions to be segregated at the interface of the formed metal silicide layer and the silicon, so that the Schottky barrier height of the first source drain doped region and the channel region can be reduced.
Therefore, In the step of performing the P-type doped isolated schottky doping process, the doping ions include one or more of B, Al, Ga, and In.
In this embodiment, the P-type doped isolation schottky doping process is an ion implantation process, the doping ions of the P-type doped isolation schottky doping process are B, and parameters of the ion implantation process are determined according to actual process requirements. In this embodiment, the parameters of the ion implantation process include: implanted ionsWhen the source is B, the energy of implanted ions is 500eV to 3KeV, and the dose of implanted ions is 1E14atom/cm2To 5E15atom/cm2(ii) a The ion source being BF2The energy of the implanted ions is 1KeV to 10KeV, and the dose of the implanted ions is 1E14atom/cm2To 5E15atom/cm2。
In this embodiment, in order to save a photomask, the P-type doped isolation schottky doping process is performed in a maskless manner, and correspondingly, the P-type doped isolation schottky doping process further dopes the second source-drain doped region.
It should be noted that, in order to reduce the schottky barrier height of the first source-drain doped region and the channel region and the schottky barrier height of the second source-drain doped region and the channel region, after the first contact opening 155 is formed, the forming method further includes: and performing Pre-amorphization (PAI) treatment on the source and drain doped regions in the first region I and the second region II, namely performing the Pre-amorphization treatment on the first source and drain doped region and the second source and drain doped region.
The pre-amorphization treatment is beneficial to reducing the Schottky barrier height; the thickness of the first epitaxial layer 112 and the second epitaxial layer 122 at the bottom of the first contact opening 155 can also be converted into the amorphous silicon layer 630, thereby being beneficial to improving the formation quality and quality uniformity of the subsequent metal silicide layer.
In this embodiment, the pre-amorphization process is an ion implantation process; the ion implantation process has Ge ion as implanted ion, implanted ion energy of 3-10 KeV and implanted ion dosage of 1E14atom/cm2To 3E15atom/cm2。
It should be noted that, in this embodiment, the pre-amorphization process is performed first, and then the P-type doped isolation schottky doping process is performed. In other embodiments, the P-type doped isolation schottky doping process may be performed first, and then the pre-amorphization process may be performed.
In addition, with reference to fig. 8, after the pre-amorphization process and the P-type doped isolated schottky doping process are completed, the forming method further includes: a second contact opening 156 is formed in the interlayer dielectric layer 103 above the gate structure (not labeled) to expose the top of the gate structure.
The second contact opening 156 provides a spatial location for the subsequent formation of a second contact hole plug electrically connected to the gate structure. The second contact opening 156 located in the first region I penetrates through the interlayer dielectric layer 103 above the first gate structure 610 and exposes the top of the first gate structure 610, and the second contact opening 156 located in the second region II penetrates through the interlayer dielectric layer 103 above the second gate structure 620 and exposes the top of the second gate structure 620.
Specifically, a filling layer 210 is formed in the first contact opening 155 (as shown in fig. 7), and the filling layer 210 also covers the top of the interlayer dielectric layer 103; forming a patterned photoresist layer (not shown) on the filling layer 210; etching the filling layer 210 and the interlayer dielectric layer 103 by using the photoresist layer as a mask, and forming a second contact opening 156 in the interlayer dielectric layer 103 above the first gate structure 610 and the interlayer dielectric layer 103 above the second gate structure 620; after the second contact opening 156 is formed, the photoresist layer and the filling layer 210 are removed.
In this embodiment, the material of the filling layer 210 is an organic dielectric material, a bottom anti-reflection layer material, a deep ultraviolet light absorbing silicon oxide material, or amorphous carbon.
Referring to fig. 9, after the P-type doped isolated schottky doping process is completed, a metal silicide layer 640 is formed at the bottom of the first contact opening 155.
The subsequent steps include forming a first contact hole plug in the first contact opening 155 of the first region I and the second region II, the first contact hole plug being used for electrically connecting with the source and drain doped region, and the metal silicide layer 640 being used for reducing the contact resistance of the contact region.
In this embodiment, the step of forming the metal silicide layer 640 includes: conformally covering a metal layer (not shown) on the surface of the first contact opening 155; after the metal layer is formed, the substrate is annealed to react the metal layer with the Si-containing substrate and convert the metal layer to a metal silicide layer 640. Specifically, the metal layer reacts with the first epitaxial layer 112 and the second epitaxial layer 122 to form the metal silicide layer 640.
In this embodiment, the metal layer is made of Ti, and the first epitaxial layer 112 and the second epitaxial layer 122 are made of Si, so during the annealing process, Ti atoms in the metal layer and Si atoms in the first epitaxial layer 112 and the second epitaxial layer 122 diffuse and react with each other, thereby forming the metal silicide layer 640 made of TiSi. In other embodiments, the metal layer may also be Ni, and accordingly, the material of the metal silicide layer formed is NiSi.
In this embodiment, the annealing treatment is a laser annealing treatment, and a process pressure of the laser annealing treatment is a standard atmospheric pressure. In other embodiments, the annealing process may also be a rapid thermal annealing process.
In order to ensure the reaction effect between the metal layer and the first epitaxial layer 112 and the second epitaxial layer 122, the thickness and quality of the formed metal silicide layer 640 meet the process requirements, and avoid adverse effects on the existing doped ions in the substrate, in this embodiment, the annealing temperature is 700 ℃ to 1000 ℃.
It should be further noted that the thickness of the metal silicide layer 640 affects the contact resistance of the contact region; when the thickness of the metal silicide layer 640 is too large, the coverage of the metal layer on the surface of the first contact opening 155 is poor, and a void (void) defect is likely to occur in the metal layer, so that the quality of the formed metal silicide layer 640 is reduced, and the electrical performance of the formed semiconductor device is affected. Therefore, in order to make the electrical performance of the formed semiconductor device meet the process requirement, in the embodiment, the thickness of the metal silicide layer 640 is
Figure BDA0001195679470000141
To
Figure BDA0001195679470000142
In this embodiment, the metal layer is formed by a physical vapor deposition process, and is further located on the sidewall of the first contact opening 155 and is further located on the bottom and the sidewall of the second contact opening 156; in the step of forming the metal silicide layer 640, the metal layer at the bottom of the first contact opening 155 reacts with silicon, and after the metal silicide layer 640 is formed, the metal layers at the sidewall of the first contact opening 155, the bottom of the second contact opening 156, and the sidewall remain. In other embodiments, the process of forming the metal layer may also be a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, in order to improve the formation quality of the metal silicide layer 640, the metal silicide layer 640 and the source/drain doped region may be electrically connected well, and before the metal layer is formed, the forming method further includes: a precleaning process is performed on the first contact opening 155.
Through the pre-cleaning process, a native oxide (native oxide) in the first contact opening 155 can be removed, so as to provide a good interface state for forming the metal layer. In this embodiment, the pre-cleaning process may be a SiCoNi process or a vapor etching process of hydrofluoric acid.
In this embodiment, after forming the metal layer and before performing an annealing process on the substrate, the forming method further includes: a barrier layer 800 is formed on the metal layer.
The barrier layer 800 functions to: on one hand, the reactant used in the subsequent formation of the first contact plug in the first contact opening 155 can be prevented from reacting with the first epitaxial layer 112 and the second epitaxial layer 122, and can also be prevented from reacting with the formed metal silicide layer 640; on the other hand, the barrier layer 800 is used to improve adhesion of a conductive material in the first contact opening 155 when a first contact hole plug is formed later, and the barrier layer 800 may function as a contact hole liner layer. In this embodiment, the material of the barrier layer 800 is TiN.
In addition, second contact openings 156 are formed in the interlayer dielectric layer 103 above the first gate structure 610 and in the interlayer dielectric layer 103 above the second gate structure 620, so that the pre-cleaning process is also performed on the second contact openings 156 in the step of performing the pre-cleaning process on the first contact openings 155; in the step of forming the barrier layer 800, the barrier layer 800 is also formed on the metal layer within the second contact opening 156.
Referring to fig. 10, after the metal silicide layer 640 is formed, a conductive material is filled into the first contact opening 155 (shown in fig. 9), and a first contact hole plug 850 is formed in the first contact opening 155.
The first contact hole plug 850 is electrically connected to the source-drain doped region, and is used for electrical connection in a semiconductor device and electrical connection between devices.
Specifically, the step of forming the first contact hole plug 850 includes: filling the first contact opening 155 with a conductive material, wherein the conductive material is also located on the top of the interlayer dielectric layer 103; and performing planarization treatment on the conductive material, removing the conductive material higher than the top of the interlayer dielectric layer 103, and forming the first contact hole plug 850 in the first contact opening 155.
In this embodiment, the material of the first contact hole plug 850 is W, and the first contact hole plug 850 may be formed by a chemical vapor deposition process, a sputtering process, or an electroplating process. In other embodiments, the material of the first contact hole plug may also be a metal material such as Al, Cu, Ag, or Au.
It should be noted that, since the second contact opening 156 is formed in the interlayer dielectric layer 103 above the first gate structure 610 and in the interlayer dielectric layer 103 above the second gate structure 620 (as shown in fig. 9), in the step of filling the first contact opening 155 with the conductive material, the second contact opening 156 is further filled with the conductive material, and the second contact hole plug 860 is formed in the second contact opening 156.
The second contact hole plug 860 is electrically connected to the gate structure for electrical connection within the semiconductor device and also for electrical connection between devices.
Referring to fig. 11, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown. Accordingly, the present invention also provides a semiconductor structure comprising:
the substrate comprises a substrate 900, a gate structure (not marked) located on the substrate 900, source-drain doped regions (not shown) located in the substrates on two sides of the gate structure, and a dielectric layer 902 located on the substrate and covering the top of the gate structure, wherein the substrate 900 comprises a first region I with a P-type device and a second region II with an N-type device; and a contact opening 950 which is located in the dielectric layer 902 on both sides of the gate structure and exposes the source/drain doped region, wherein the source/drain doped region exposed by the contact opening 950 in the first region I and the second region II is subjected to a P-type doping isolation schottky doping process in the same step.
In this embodiment, the semiconductor structure is a finfet, and thus the base further includes a discrete fin (not shown) on the substrate 900. In other embodiments, the semiconductor structure is a planar transistor and, correspondingly, the substrate is a planar substrate.
In this embodiment, the substrate 900 includes a first region I with P-type devices and a second region II with N-type devices. Correspondingly, the fin on the first region I substrate 900 is a first fin 910, and the fin on the second region II substrate 900 is a second fin 920. In other embodiments, the substrate may also include only the first region with P-type devices or only the second region with N-type devices.
The first region I and the second region II may be adjacent regions, or may not be adjacent regions. In this embodiment, the first region I and the second region II are adjacent regions.
The gate structure in the first region I is therefore a first gate structure 941, the first gate structure 941 crosses over the first fin 910 and covers a portion of the sidewall surface and the top surface of the first fin 910; the gate structure in the second region II is a second gate structure 942, and the second gate structure 942 spans the second fin 920 and covers a portion of the sidewall surface and the top surface of the second fin 920.
Correspondingly, the source-drain doped regions in the first fin portion 910 on both sides of the first gate structure 941 are first source-drain doped regions (not shown), and the source-drain doped regions in the second fin portion 920 on both sides of the second gate structure 942 are second source-drain doped regions (not shown); the contact opening 950 located in the first region I exposes the first source drain doped region, and the contact opening 950 located in the second region II exposes the second source drain doped region.
In this embodiment, the substrate 900 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin is made of the same material as the substrate 900. In this embodiment, the fin portion is made of silicon, that is, the first fin portion 910 and the second fin portion 920 are made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the semiconductor structure further includes: and the isolation structures 901 are positioned on the substrate 900 between the adjacent fins, the isolation structures 901 cover part of the side walls of the fins, and the tops of the isolation structures 901 are lower than the tops of the fins.
The isolation structure 901 serves as an isolation structure of a semiconductor device, and is used for isolating adjacent devices and fins. In this embodiment, the isolation structure 901 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
In this embodiment, the semiconductor structure further includes: a first epitaxial layer 912 in the first fin 910 on two sides of the first gate structure 941, and a second epitaxial layer 922 in the second fin 920 on two sides of the second gate structure 942; the first source-drain doped region is located in the first epitaxial layer 912, and the second source-drain doped region is located in the second epitaxial layer 922.
The material of the first epitaxial layer 912 may be Si or SiGe, and the dopant ions of the first source-drain doped region include one or more of B, Ga and In. In this embodiment, the material of the first epitaxial layer 912 is Si; and the doping ions of the first source drain doping region are Ge ions. The doping concentration of Ge ions is determined according to the actual process requirements, and in the present embodiment, the content of Ge ions in atomic percentage is 35% to 65%.
The material of the second epitaxial layer 922 may be Si or SiC, and the doping ions of the second source-drain doping region include one or two of P and As. In this embodiment, the material of the second epitaxial layer 922 is Si; and the doping ions of the second source drain doping region are P ions.
In this embodiment, the source-drain doped regions exposed by the contact openings 950 in the first region I and the second region II undergo a P-type doped isolated Schottky (DSS) doping process in the same step, that is, both the first source-drain doped region and the second source-drain doped region undergo a P-type doped isolated Schottky doping process; the doping ions of the doping process are P-type ions and are used for reducing the Schottky Barrier Height (SBH) of the first source-drain doping region and the channel region of the P-type device, and correspondingly, the second source-drain doping region is also influenced by the doping of the P-type ions; therefore, in order to reduce the influence on the electrical performance of the N-type device, the P ion doping concentration of the second source/drain doped region is higher than that of the second source/drain doped region which is not influenced by the P-type doping isolation schottky doping process.
Specifically, the P ion doping concentration of the second source-drain doping region is determined according to actual process requirements and the doping concentration of the P-type doping isolation schottky doping process. In this embodiment, the P ion doping concentration of the second source/drain doping region is 1E21atom/cm3To 3E21atom/cm3。
It should be further noted that by increasing the P ion doping concentration of the second source-drain doped region, the schottky barrier height of the first source-drain doped region and the channel region is also favorably reduced, so that the contact resistance of the second region II is favorably reduced, and the driving current of the N-type device is further improved.
In other embodiments, the first fin portions on two sides of the first gate structure may not have a first epitaxial layer therein, and the second fin portions on two sides of the second gate structure may not have a second epitaxial layer therein; therefore, the first source-drain doped region may be located in the first fin portion, and the second source-drain doped region may be located in the second fin portion.
In the actual process, when a metal layer is deposited on the first source-drain doped region to form a metal silicide (silicide) layer, in the process of forming the metal silicide layer by reacting the metal layer and silicon through an annealing process, the annealing process also drives the P-type ions to be segregated at the interface between the formed metal silicide layer and the silicon, so that the schottky barrier height of the first source-drain doped region and the channel region can be reduced. Therefore, the doping ions of the P-type doping isolation schottky doping process include one or more of B, Al, Ga and In. In this embodiment, the doping ion of the P-type doped isolation schottky doping process is B.
It should be noted that the source/drain doped regions exposed by the contact openings 950 in the first region I and the second region II are further subjected to a Pre-amorphization (PAI) ion implantation process, that is, both the first source/drain doped region and the second source/drain doped region are subjected to a Pre-amorphization ion implantation process; the semiconductor structure thus further comprises: the amorphous silicon layer 960 is located at the bottom of the contact opening 950, the amorphous silicon layer 960 of the first region I is transformed from the first epitaxial layer 912, the amorphous silicon layer 960 of the second region II is transformed from the second epitaxial layer 922, and the amorphous silicon layer 960 is beneficial to improving the formation quality and quality uniformity of the metal silicide layer. In this embodiment, the implanted ions of the pre-amorphization ion implantation process are Ge ions.
In this embodiment, the gate structures are metal gate structures, that is, the first gate structure 941 and the second gate structure 942 are metal gate structures. The gate structure includes a gate dielectric layer (not labeled) that spans the fin and covers a portion of the top surface and sidewall surfaces of the fin, and a metal layer (not labeled) on the gate dielectric layer, and the gate structure is located within the dielectric layer 902.
In this embodiment, the gate dielectric layer includes an Interfacial layer (I L, Interfacial L eye) (not labeled) and a high-k gate dielectric layer (not labeled) on the surface of the Interfacial layer.
The interface layer provides a good interface foundation for forming the high-k gate dielectric layer, so that the quality of the high-k gate dielectric layer is improved, the interface state density between the high-k gate dielectric layer and the fin portion is reduced, and adverse effects caused by direct contact of the high-k gate dielectric layer and the fin portion are avoided. The interface layer is made of silicon oxide or silicon oxynitride.
The high-k gate dielectric layer is made of a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In this embodiment, the metal layer is made of W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.
In addition, the semiconductor structure further includes: and the side wall 930 is positioned on the side wall of the gate structure, and the side wall 930 is used for being positioned in the source-drain doped region. The sidewall 930 may be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the sidewall 930 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacers 930 are single-layer structures, and the material of the sidewall spacers 930 is silicon nitride.
The dielectric layer 902 is made of an insulating material, and the dielectric layer 902 provides a process platform for a contact hole plug forming process. In this embodiment, the dielectric layer 902 is made of silicon oxide. In other embodiments, the material of the dielectric layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the semiconductor structure includes a contact opening 950, the contact opening 950 is located in the dielectric layer 902 on both sides of the gate structure and exposes the source/drain doped region (not shown in the figure), wherein the source/drain doped region exposed by the contact opening 950 in the first region I and the second region II undergoes a P-type doping isolation schottky doping process in the same step; therefore, by adjusting the doping concentration of the source-drain doped region of the second region II in the semiconductor structure to a reasonable value, the P-type doping isolation Schottky doping process can be avoided by additionally adopting a photomask, so that the manufacturing cost of the semiconductor structure is low, and the influence on an N-type device is small; and simultaneously, the Schottky barrier height of the source-drain doped region and the channel region of the first region I can be still reduced, so that the contact resistance of the first region I is reduced, and the driving current of a P-type device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped regions positioned in the substrates at two sides of the gate structure, and an interlayer dielectric layer positioned on the substrate and covering the top of the gate structure, and the substrate comprises a first region for forming a P-type device and a second region for forming an N-type device;
forming a first contact opening exposing the source-drain doped region in the interlayer dielectric layers on two sides of the grid structure;
carrying out a P-type doping isolation Schottky doping process on the source-drain doped region exposed out of the first contact opening in the first region and the second region;
after the P-type doping isolation Schottky doping process is finished, forming a metal silicide layer at the bottom of the first contact opening;
after the metal silicide layer is formed, filling a conductive material into the first contact opening, and forming a first contact hole plug in the first contact opening;
wherein the step of forming the substrate further comprises: and forming a source-drain doped region of the second region, and adjusting the concentration of doped ions in the source-drain doped region of the second region according to the parameters of the P-type doped isolation Schottky doping process when the source-drain doped region of the second region is formed.
2. The method of claim 1, wherein In the step of performing the P-type dopant isolation schottky doping process, the dopant ions of the P-type dopant isolation schottky doping process comprise one or more of B, Al, Ga, and In.
3. The method as claimed in claim 1 or 2, wherein the P-type dopant isolation schottky doping process is an ion implantation process, and the dopant ions of the P-type dopant isolation schottky doping process are B;
the parameters of the ion implantation process include: the ion source is B, the energy of the implanted ions is 500eV to 3KeV, and the dose of the implanted ions is 1E14atom/cm2To 5E15atom/cm2(ii) a Alternatively, the ion source implanted is BF2The energy of the implanted ions is 1KeV to 10KeV, and the dose of the implanted ions is 1E14atom/cm2To 5E15atom/cm2。
4. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming the substrate, the source-drain doped region located in the first region is a first source-drain doped region, and the source-drain doped region located in the second region is a second source-drain doped region;
the doping ions of the first source drain doping region comprise Ge ions, and the atomic percentage content of the Ge ions is 35-65%;
the doping ions of the second source drain doping region comprise P ions, and the doping concentration of the P ions is 1E21atom/cm3To 3E21atom/cm3。
5. The method of forming a semiconductor structure of claim 1, wherein after forming the first contact opening and before forming the metal silicide layer, the method further comprises: and performing pre-amorphization treatment on the source-drain doped regions in the first region and the second region.
6. The method of claim 5, wherein the pre-amorphization process is an ion implantation process;
the ion implantation process has Ge ion as implanted ion, implanted ion energy of 3-10 KeV and implanted ion dosage of 1E14atom/cm2To 3E15atom/cm2。
7. The method of forming a semiconductor structure of claim 1, wherein the substrate is a Si-containing substrate, and the step of forming the metal silicide layer comprises: conformally covering a metal layer on the surface of the first contact opening; and after the metal layer is formed, annealing the substrate to enable the metal layer to react with the Si-containing substrate, and converting the metal layer into a metal silicide layer.
8. The method of forming a semiconductor structure of claim 7, wherein the annealing process is a laser annealing process or a rapid thermal annealing process.
9. The method of forming a semiconductor structure of claim 8, wherein the annealing process is a laser annealing process, and the parameters of the laser annealing process include: the annealing temperature is 700 ℃ to 1000 ℃, and the pressure is one standard atmospheric pressure.
10. The method of forming a semiconductor structure of claim 1, wherein the metal silicide layer has a thickness of
Figure FDA0002475908660000021
To
Figure FDA0002475908660000022
11. The method of forming a semiconductor structure of claim 1, wherein after completing the P-type dopant isolated schottky dopant process, the method further comprises, prior to forming a metal silicide layer at a bottom of the first contact opening: forming a second contact opening exposing the top of the grid structure in the interlayer dielectric layer above the grid structure;
and in the step of filling the first contact opening with a conductive material, filling the second contact opening with a conductive material, and forming a second contact hole plug in the second contact opening.
12. The method of claim 1, wherein in the step of forming a base, the base further comprises discrete fin portions on the substrate;
the grid electrode structure crosses the fin part and covers part of the side wall surface and the top surface of the fin part;
the source and drain doped regions are located in the fin portions on two sides of the grid structure.
13. The method of forming a semiconductor structure of claim 1, wherein the step of forming a substrate comprises: providing an initial substrate; etching the initial substrate to form a substrate and a discrete fin part on the substrate, wherein the substrate comprises a first area for forming a P-type device and a second area for forming an N-type device; forming a pseudo-gate structure which crosses the fin part and covers the top surface and the side wall surface of the fin part; forming source and drain doped regions in the fin parts on two sides of the pseudo gate structure; forming a bottom dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the bottom dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming an opening in the bottom dielectric layer; forming a gate structure in the opening, wherein the top of the gate structure is flush with the top of the bottom dielectric layer; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the top of the grid structure and the top of the bottom dielectric layer;
or,
the step of forming the substrate comprises: providing an initial substrate; etching the initial substrate to form a substrate and a discrete fin part on the substrate, wherein the substrate comprises a first area for forming a P-type device and a second area for forming an N-type device; forming a grid electrode structure which stretches across the fin part and covers the top surface and the side wall surface of the fin part; forming source and drain doped regions in the fin parts on two sides of the grid structure; and forming an interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the top of the interlayer dielectric layer is higher than that of the grid structure.
14. A semiconductor structure, comprising:
the substrate comprises a substrate, a grid structure positioned on the substrate, source-drain doped regions positioned in the substrates at two sides of the grid structure and an interlayer dielectric layer positioned on the substrates and covering the top of the grid structure, wherein the substrate comprises a first region with a P-type device and a second region with an N-type device;
the contact opening is positioned in the interlayer dielectric layers on two sides of the grid structure and exposes the source-drain doped region, wherein the source-drain doped region exposed by the contact opening in the first region and the second region is subjected to a P-type doping isolation Schottky doping process in the same step;
and the concentration of the doped ions in the source-drain doped region of the second region is adjusted according to the parameters of the P-type doped isolation Schottky doping process.
15. The semiconductor structure of claim 14, In which dopant ions of the P-type doped isolated schottky doping process comprise one or more of B, Al, Ga, and In.
16. The semiconductor structure of claim 14, wherein the source-drain doped region located in the first region is a first source-drain doped region, and the source-drain doped region located in the second region is a second source-drain doped region;
the doping ions of the first source drain doping region comprise Ge ions, and the atomic percentage content of the Ge ions is 35-65%;
the doping ions of the second source drain doping region comprise P ions, and the doping concentration of the P ions is 1E21atom/cm3To 3E21atom/cm3。
17. The semiconductor structure of claim 14, wherein the source and drain doped regions exposed by the first contact opening in the first and second regions are further subjected to a pre-amorphization ion implantation process, wherein the pre-amorphization ion implantation process comprises implanting Ge ions.
18. The semiconductor structure of claim 14, wherein the base further comprises a discrete fin on the substrate;
the grid electrode structure crosses the fin part and covers part of the side wall surface and the top surface of the fin part;
the source and drain doped regions are located in the fin portions on two sides of the grid structure.
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