CN110634802B

CN110634802B - Semiconductor structure and forming method thereof

Info

Publication number: CN110634802B
Application number: CN201810651232.1A
Authority: CN
Inventors: 于书坤
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-06-22
Filing date: 2018-06-22
Publication date: 2022-01-14
Anticipated expiration: 2038-06-22
Also published as: CN110634802A

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate comprising a device area, wherein the type of the device area comprises one or two of an NMOS area and a PMOS area, and the device areas of the same type are used for forming devices with different threshold voltages; forming a gate structure on a substrate; and forming source and drain doping layers in the substrate at two sides of the grid structure, wherein the doping ion concentrations of the source and drain doping layers corresponding to different threshold voltages are different in the same type of device region. According to the invention, by adjusting the concentration of the doped ions of each source-drain doped layer in the same type of device region, the threshold voltage of each device is easy to adjust respectively, the adverse effect of the process for forming the work function layer on the performance and yield of the device can be reduced, and the cross effect of the threshold voltage adjustment of any device on other devices is avoided.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

A Complementary Metal-Oxide Semiconductor (CMOS) device is one of the basic Semiconductor devices constituting an integrated circuit. With the rapid development of the integrated circuit manufacturing process, the feature size of the CMOS device is continuously reduced according to a certain proportion, and it is a trend of the integrated circuit development to adopt the gate dielectric layer of the high-k material to replace the gate dielectric layer of the conventional oxide material. However, there are still many problems to be solved when forming a metal gate on a high-k gate dielectric layer, one of which is work function matching. Because the work function will directly affect the Threshold Voltage (Vt) and device performance of the device, the work function must be adjusted to be within the proper operating range for CMOS devices.

In order to meet the requirement of improving the threshold voltage of an NMOS device and a PMOS device at the same time, different metal materials are generally used as Work Function (WF) layer materials of the NMOS device and the PMOS device, so that the NMOS device and the PMOS device have different threshold voltages, wherein the NMOS device has an N-type Work Function layer, and the PMOS device has a P-type Work Function layer.

However, the difficulty of the current process for adjusting the threshold voltage is large, and the adjustment of the threshold voltage easily causes the reduction of the performance and yield of the device.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can reduce the process difficulty of adjusting threshold voltage and improve the performance and yield of devices.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate comprising a device area, wherein the type of the device area comprises one or two of an NMOS area and a PMOS area, and the device areas of the same type are used for forming devices with different threshold voltages; forming a gate structure on the substrate; and forming source and drain doping layers in the substrate on two sides of the grid structure, wherein the doping ion concentrations of the source and drain doping layers corresponding to different threshold voltages are different in the same type of device region.

Accordingly, the present invention also provides a semiconductor structure comprising: the device comprises a substrate and a plurality of semiconductor chips, wherein the substrate comprises a device area, the type of the device area comprises one or two of an NMOS area and a PMOS area, and devices with different threshold voltages are respectively formed on the device areas with the same type; a metal gate structure on the substrate; and the source and drain doping layers are positioned in the substrates at two sides of the metal gate structure, and the doped ion concentrations of the source and drain doping layers corresponding to different threshold voltages are different in the same type of device region.

Compared with the prior art, the technical scheme of the invention has the following advantages:

when the same type devices (NMOS devices or PMOS devices) with different threshold voltages are formed, the doped ion concentrations of source and drain doped layers corresponding to different threshold voltages are different in the same type device regions, and the larger the doped ion concentration of the source and drain doped layers is, the smaller the external parasitic resistance (Rex) of the device is, the smaller the threshold voltage of the device is, so that the NMOS devices or PMOS devices with different threshold voltages are obtained by adjusting the doped ion concentration of each source and drain doped layer in the same type device region, and when a work function layer is formed subsequently, the same type device regions can share the same work function layer; therefore, compared with the scheme that source and drain doped layers with the same doped ion concentration are formed, and the threshold voltage is adjusted by adjusting the thickness of the work function layer, the threshold voltage of each device is easy to be respectively adjusted by adjusting the doped ion concentration, the process steps for forming the work function layer can be simplified, the times of photoetching, etching, ashing and cleaning processes are reduced, the adverse effect of the process for forming the work function layer on the performance and yield of the device can be correspondingly reduced, and the Cross effect (Cross Impact) of the threshold voltage adjustment of any device on other devices can be reduced; in conclusion, the scheme of the invention is beneficial to reducing the process difficulty of adjusting the threshold voltage and can also reduce the adverse effect of the adjustment of the threshold voltage on the performance and yield of the device.

In the alternative, the types of the device regions comprise an NMOS region and a PMOS region, and the threshold voltages of the PMOS device and the NMOS device are conveniently and respectively adjusted by adjusting the concentration of doped ions of source and drain doped layers in the same type of device region, so that the cross influence between the PMOS device and the NMOS device is prevented, the process difficulty of adjusting the threshold voltages is further reduced, and the performance and the yield of the device are improved.

Drawings

Fig. 1 to 7 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

fig. 8 to 29 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

Lightly Doped Drain (LDD) implantation is the main process for precisely adjusting the threshold voltage of a device, but as the feature size of CMOS devices is continuously reduced, semiconductor processes gradually start to transition from planar MOSFETs to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). After a Fin (Fin) structure is introduced into a semiconductor structure, the effect of adjusting the threshold voltage of the device through a lightly doped drain implantation Process is correspondingly deteriorated, so that the NMOS device and the PMOS device have different threshold voltages mainly through a Multi-Work Function Process (Multi-Work Function Process) at present.

In the multilayer work function layer process, the concentration of doped ions of the source and drain doped layers of each NMOS device is the same, the concentration of doped ions of the source and drain doped layers of each PMOS device is the same, and the threshold voltages of each NMOS device and each PMOS device are respectively adjusted to the process requirement value by forming corresponding metal materials (one or two of an N-type work function layer material and a P-type work function layer material) and work function layers with corresponding thicknesses in each region.

However, the difficulty of the current process for adjusting the threshold voltage is large, and the adjustment of the threshold voltage easily causes the reduction of the performance and yield of the device. The reason why it is difficult to adjust the threshold voltage is analyzed in conjunction with a method of forming a semiconductor structure.

Referring to fig. 1 to 7, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.

Referring to fig. 1, a substrate 10 is provided, which includes a first NMOS region 11N, a first PMOS region 11P, a second NMOS region 12N, and a second PMOS region 12P, wherein a device threshold voltage of the first NMOS region 11N is greater than a device threshold voltage of the second NMOS region 12N, and a device threshold voltage of the first PMOS region 11P is greater than a device threshold voltage of the second PMOS region 12P; a high-k gate dielectric Layer 11 is formed on the substrate 10, a Cap Layer (Cap Layer)12 is formed on the high-k gate dielectric Layer 11, and a first P-type work function Layer 21 is formed on the Cap Layer 12.

Referring to fig. 2, a first photoresist layer (not shown) is formed on the first P-type work function layer 21 of the second PMOS region 12P; etching and removing the first P-type work function layer 21 of the first NMOS region 11N, the first PMOS region 11P and the second NMOS region 12N by taking the first photoresist layer as a mask; and removing the first photoresist layer.

Referring to fig. 3, after the first P-type work function layer 21 of the first NMOS area 11N, the first PMOS area 11P, and the second NMOS area 12N is removed by etching, a second P-type work function layer 22 is formed on the substrate 10, and the second P-type work function layer 22 covers the remaining first P-type work function layer 21 and the cap layer 12 exposed from the remaining first P-type work function layer 21.

Referring to fig. 4, a second photoresist layer (not shown) is formed on the second P-type work function layer 22 of the first PMOS region 11P and the second PMOS region 12P; etching and removing the second P-type work function layer 22 of the first NMOS region 11N and the second NMOS region 12N with the second photoresist layer as a mask; and removing the second photoresist layer.

Referring to fig. 5, after removing the second P-type work function layer 22 in the first NMOS area 11N and the second NMOS area 12N by etching, a third P-type work function layer 23 is formed on the substrate 10, and the third P-type work function layer 23 covers the remaining second P-type work function layer 22 and the cap layer 12 exposed from the remaining second P-type work function layer 22.

Referring to fig. 6, a third photoresist layer (not shown) is formed on the third P-type work function layer 23 of the first PMOS region 11P, the second PMOS region 12P and the first NMOS region 11N; etching and removing the third P-type work function layer 23 of the second NMOS region 12N with the third photoresist layer as a mask; and removing the third photoresist layer.

Referring to fig. 7, after removing the third P-type work function layer 23 of the second NMOS area 12N by etching, an N-type work function layer 24 is formed on the substrate 10, and the N-type work function layer 24 covers the remaining third P-type work function layer 23 and the cap layer 12 exposed from the remaining third P-type work function layer 23.

Taking the first NMOS region 11N for forming an N-type standard threshold voltage (NSVT) device, the second NMOS region 12N for forming an N-type low threshold voltage (NLVT) device, the first PMOS region 11P for forming a P-type standard threshold voltage (PSVT) device, the second PMOS region 12P for forming a P-type low threshold voltage (PLVT) device as an example, the second P-type work function layer 22 affects the threshold voltages of the P-type standard threshold voltage devices and P-type low threshold voltage devices, the third P-type work function layer 23 affects the threshold voltages of the P-type standard threshold voltage devices, P-type low threshold voltage devices and N-type standard threshold voltage devices, the N-type work function layer 24 affects the threshold voltages of the four devices, and the adjustment of the work function layer affects the other devices in a cross manner, so that it is difficult to individually adjust the threshold voltage of any device through the work function layer.

In addition, in the process of the multilayer work function layer, three times of photolithography process and three times of etching process are required, the photoresist of the carbon-based (C-based) material has the problem of photoresist residue (PR Residual), C ions may diffuse into the work function layer through the contact surface of the photoresist layer and the work function layer, and the work function layer and the cap layer 12 may be damaged by multiple etching and ashing processes, thereby having adverse effects on the performance and yield of the device.

In order to solve the technical problem, when the same type of devices (NMOS devices or PMOS devices) with different threshold voltages are formed, the doped ion concentrations of source and drain doped layers corresponding to the different threshold voltages are different in the same type of device regions, and as the doped ion concentration of the source and drain doped layers is higher, the external parasitic resistance of the device is smaller, and the threshold voltage of the device is smaller, the NMOS devices or PMOS devices with different threshold voltages are obtained by adjusting the doped ion concentration of each source and drain doped layer in the same type of device regions, and when a work function layer is formed subsequently, the same type of device regions can share the same work function layer; therefore, compared with the scheme that source and drain doped layers with the same doped ion concentration are formed, and the threshold voltage is adjusted by adjusting the thickness of the work function layer, the threshold voltage of each device is easy to be respectively adjusted by adjusting the doped ion concentration, the process steps for forming the work function layer can be simplified, the times of photoetching, etching, ashing and cleaning processes are reduced, the adverse effect of the process for forming the work function layer on the performance and yield of the device can be correspondingly reduced, and the cross effect of the threshold voltage adjustment of any device on other devices can be reduced; in conclusion, the scheme of the invention is beneficial to reducing the process difficulty of adjusting the threshold voltage and can also reduce the adverse effect of the adjustment of the threshold voltage on the performance and yield of the device.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 8 to 10 in combination, fig. 8 is a perspective view (only four fins are shown), fig. 9 is a schematic cross-sectional view of different device regions in fig. 8 along a direction perpendicular to an extending direction of the fins (as indicated by Y1Y2 in fig. 8), fig. 10 is a schematic cross-sectional view of different device regions in fig. 8 along the extending direction of the fins (as indicated by X1X2 in fig. 8), a substrate 100 is provided, the substrate 100 includes device regions (not shown), the type of the device regions includes one or both of an NMOS region 110N and a PMOS region 110P, and the device regions of the same type are used for forming devices with different threshold voltages.

In this embodiment, the substrate 100 is used to form a finfet transistor, and therefore the substrate 100 includes a substrate 110 and a plurality of discrete fins 120 located on the substrate 110. In other embodiments, the base may also be used to form a planar transistor, and the base is accordingly a substrate.

In this embodiment, the substrate 110 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the fin 120 and the substrate 110 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

Therefore, in this embodiment, the material of the fin 120 is the same as the material of the substrate 110, and the material of the fin 120 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.

The types of the device regions include one or two of an NMOS region 110N and a PMOS region 110P, the NMOS region 110N being used to form NMOS devices of different threshold voltages, and the PMOS region 110P being used to form PMOS devices of different threshold voltages. In this embodiment, the types of the device regions include an NMOS region 110N and a PMOS region 110P.

It should be noted that the device regions of the same type may be any of a high threshold voltage region, a standard threshold voltage region, a low threshold voltage region, and an ultra-low threshold voltage region. That is, the PMOS region 110P may be any of a P-type high threshold voltage region, a P-type standard threshold voltage region, a P-type low threshold voltage region, and a P-type ultra-low threshold voltage region, and the NMOS region 110N may be any of an N-type high threshold voltage region, an N-type standard threshold voltage region, an N-type low threshold voltage region, and an N-type ultra-low threshold voltage region.

In this embodiment, the device regions of the same type include a first device region (not labeled) and a second device region (not labeled), and the device threshold voltage of the first device region is smaller than the device threshold voltage of the second device region.

Specifically, a first device region in the NMOS region 110N is a first NMOS region 111N (as shown in fig. 8), a second device region in the NMOS region 110N is a second NMOS region 112N (as shown in fig. 8), a first device region in the PMOS region 110P is a first PMOS region 111P (as shown in fig. 8), a second device region in the PMOS region 110P is a second PMOS region 112P (as shown in fig. 8), a device threshold voltage of the first NMOS region 111N is smaller than a device threshold voltage of the second NMOS region 112N, and a device threshold voltage of the first PMOS region 111P is smaller than a device threshold voltage of the second PMOS region 112P.

In this embodiment, the first PMOS region 111P is a P-type low threshold voltage region, the second PMOS region 112P is a P-type standard threshold voltage region, the first NMOS region 111N is an N-type low threshold voltage region, and the second NMOS region 112N is an N-type standard threshold voltage region are taken as examples for explanation.

It should be further noted that, for convenience of illustration, fig. 9 and fig. 10 only illustrate cross-sectional views of the NMOS region 110N and the PMOS region 110P, that is, fig. 9 and fig. 10 can be used to characterize any one of the first PMOS region 111P and the second PMOS region 112P, and any one of the first NMOS region 111N and the second NMOS region 112N.

Further, with continuing reference to fig. 8-10 in combination, the method of forming further includes: isolation structures 101 are formed on the substrate 100 (as shown in fig. 8).

The isolation structure 101 is used to isolate adjacent devices. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be other insulating materials such as silicon nitride or silicon oxynitride.

In this embodiment, the isolation structure 101 is formed on the substrate 110 exposed by the fin 120, the isolation structure 101 covers a portion of the sidewall of the fin 120, and the top of the isolation structure 101 is lower than the top of the fin 120.

Referring to fig. 11 and 12 in combination, fig. 11 is a schematic cross-sectional view based on fig. 9, and fig. 12 is a schematic cross-sectional view based on fig. 10, and a gate structure 130 is formed on the substrate 100 (shown in fig. 8).

In this embodiment, the Gate structure 130 is a Dummy Gate structure (Dummy Gate), and the Gate structure 130 is used to occupy a spatial position for a Metal Gate structure (Metal Gate) to be formed subsequently.

The gate structure 130 may be a stacked structure including a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer, and the gate structure 130 may also be a single-layer structure including a dummy gate layer. The material of the pseudo gate oxide layer can be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the material of the pseudo gate oxide layer can be silicon oxide or silicon oxynitride. In this embodiment, the gate structure 130 is a single-layer structure, and the dummy gate layer is made of polysilicon.

Specifically, the gate structure 130 crosses over the fin 120 and covers a portion of the top and a portion of the sidewall of the fin 120.

In this embodiment, the gate structure 130 is formed by a mask etching method, so a gate mask layer 200 is formed on the top of the gate structure 130, and the gate mask layer 200 is used as an etching mask for forming the gate structure 130.

The gate mask layer 200 is made of silicon nitride, and the gate mask layer 200 is also used for protecting the top of the gate structure 130 in the subsequent process.

After the gate structure 130 is formed, the method further includes: a sidewall spacer 140 is formed on the sidewall of the gate structure 130, and the sidewall spacer 140 further covers the sidewall of the gate mask layer 200.

The material of the sidewall 140 may be one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 140 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacers 140 have a single-layer structure, and the material of the sidewall spacers 140 is silicon nitride.

It should be noted that, unless otherwise specified, all drawings provided in the subsequent process are schematic cross-sectional views along the extending direction of the fin portion (as shown in the direction X1X2 in fig. 8).

Referring to fig. 13 to fig. 24, source and drain doped layers (not shown) are formed in the substrate 100 (as shown in fig. 8) on both sides of the gate structure 130, and the doped ion concentrations of the source and drain doped layers corresponding to different threshold voltages are different in the same type of device region.

In the same type of device region, the greater the concentration of doped ions of the source and drain doped layers is, the smaller the external parasitic resistance of the device is, and the smaller the threshold voltage of the device is, so that the adjustment of the threshold voltage of each device can be realized by adjusting the concentration of doped ions of each source and drain doped layer in the same type of device region, and when a work function layer is formed subsequently, the same type of device region can share the same work function layer; therefore, compared with the scheme that source and drain doped layers with the same doped ion concentration are formed, and the threshold voltage is adjusted by adjusting the thickness of the work function layer, the threshold voltage of each device is easy to be respectively adjusted by adjusting the doped ion concentration, the process steps for forming the work function layer can be simplified, the times of photoetching, etching, ashing and cleaning processes are reduced, the adverse effect of the process for forming the work function layer on the performance and yield of the device can be correspondingly reduced, and the cross effect of the threshold voltage adjustment of any device on other devices can be reduced; in conclusion, the scheme of the invention is beneficial to reducing the process difficulty of adjusting the threshold voltage and can also reduce the adverse effect of the adjustment of the threshold voltage on the performance and yield of the device.

In this embodiment, the device region includes an NMOS region 110N (as shown in fig. 8) and a PMOS region 110P (as shown in fig. 8), and accordingly, by adjusting the concentration of doped ions in each source-drain doped layer in the same type of device region, it is further convenient to adjust the threshold voltages of the PMOS device and the NMOS device, so as to prevent cross-talk between the PMOS device and the NMOS device, and further reduce the process difficulty of adjusting the threshold voltage, and improve the device performance and yield.

In this embodiment, in the step of forming the source-drain doping layers in the substrate 100 on both sides of the gate structure 130, the source-drain doping layer formed in the first device region (not labeled) is a first source-drain doping layer (not labeled), and the source-drain doping layer formed in the second device region (not labeled) is a second source-drain doping layer (not labeled).

In this embodiment, the source-drain doped layer formed in the PMOS region 110P is a P-type source-drain doped layer. Specifically, the first source-drain doping layer formed in the PMOS region 110P is a first P-type source-drain doping layer 160 (as shown in fig. 15), the second source-drain doping layer formed in the PMOS region 110P is a second P-type source-drain doping layer 170 (as shown in fig. 18), and the doping ion concentration of the first P-type source-drain doping layer 160 is greater than the doping ion concentration of the second P-type source-drain doping layer 170.

In this embodiment, the source-drain doped layer formed in the NMOS region 110N is an N-type source-drain doped layer. Specifically, the first source-drain doped layer formed in the NMOS region 110N is a first N-type source-drain doped layer 180 (as shown in fig. 21), and the second source-drain doped layer formed in the NMOS region 110N is a second N-type source-drain doped layer 190 (as shown in fig. 24).

In a semiconductor process, the source-drain doped layer of the NMOS region 110N is usually formed after the source-drain doped layer of the PMOS region 110P is formed, and therefore, in order to reduce the change of the process, the first N-type source-drain doped layer 180 and the second N-type source-drain doped layer 190 are formed after the first P-type source-drain doped layer 160 and the second P-type source-drain doped layer 170 are formed.

It should be noted that, in order to improve the process operability, source-drain doped layers with different doped ion concentrations are respectively formed in different process steps; that is, the processes of forming the source and drain doped layers with different dopant ion concentrations are sequential in the same type of device region.

In this embodiment, the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170, the first N-type source-drain doping layer 180, and the second N-type source-drain doping layer 190 are formed in sequence as an example for explanation. It should be noted that the process sequence for forming the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170, the first N-type source-drain doping layer 180, and the second N-type source-drain doping layer 190 is not limited to this, and the process sequence may be determined according to actual process conditions, for example, the first P-type source-drain doping layer, the first N-type source-drain doping layer, the second P-type source-drain doping layer, and the second N-type source-drain doping layer may be formed in sequence.

The following will describe in detail the process steps for forming the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170, the first N-type source-drain doping layer 180, and the second N-type source-drain doping layer 190 with reference to the accompanying drawings.

Referring to fig. 13 to 15 in combination, fig. 13 to 15 are schematic cross-sectional views of the first PMOS region and the second PMOS region along the extending direction of the fin portion, and a first groove (not labeled) is formed in the substrate 100 (as shown in fig. 8) at two sides of the gate structure 130 of the first PMOS region 111P; through a first epitaxial process, a first epitaxial layer (not labeled) is formed in the first groove, and in-situ self-doping is performed during the process of forming the first epitaxial layer, so as to form a first P-type source-drain doping layer 160 (as shown in fig. 15).

In this embodiment, the first recess formed in the first PMOS region 111P substrate 100 is a first P region recess 151 (as shown in fig. 14), the first epitaxial process is a first P-type epitaxial process, a first P-type epitaxial layer (not shown) is formed in the first P region recess 151 by the first P-type epitaxial process, and first P-type ions are self-doped in situ during the process of forming the first P-type epitaxial layer.

In this embodiment, the first P-region groove 151 is U-shaped. The sidewalls of the U-shaped first P-region groove 151 are perpendicular to the surface of the substrate 110, thereby advantageously reducing the influence of the process for forming the first P-region groove 151 on the channel region. In other embodiments, the first P-zone groove may also be bowl-shaped or Sigma-shaped in shape.

In this embodiment, the first P-type epitaxy process is a selective epitaxy process, and correspondingly, the top of the first P-type source-drain doping layer 160 is higher than the top of the first P-region groove 151. In other embodiments, the top of the first P-type source-drain doped layer may be flush with the top of the first P-region groove.

The first P-type epitaxial layer is made of SiGe, GeSn or GeSb, and provides a pressure stress effect for the channel region of the first PMOS region 111P, so that the carrier mobility of the first PMOS region 111P is improved.

In this embodiment, the first P-type ions are B ions. The Atomic Mass (Atomic Mass) of B is small, and the first P type epitaxial layer can be used as a gap atom, so that the influence of B ions on the compressive stress action of the first P type epitaxial layer is favorably prevented. In other embodiments, the first P-type ions may also be Ga ions or In ions.

In this embodiment, the first P-type epitaxial layer is made of SiGe, so that the first P-type source-drain doping layer 160 is made of SiGe doped with B ions, that is, the first P-type source-drain doping layer 160 is made of SiGeB. Correspondingly, the parameters of the first P-type epitaxial process include: carrier gasIs H₂The etching gas is HCl, and the silicon source gas comprises SiH₄、SiH₂Cl₂、SiH₃Cl and SiHCl₃The germanium source gas comprises GeH₄、GeH₃Cl、GeH₂Cl₂And GeHCl₃Wherein the boron source gas comprises BH₃、BH₂Cl and BHCl₃One or more of (a).

It should be noted that, in the first P-type source-drain doping layer 160, according to an actual process condition, the atomic number percentage content of Ge and the doping concentration of B ions are reasonably set, so that while the threshold voltage of the first PMOS region 111P is ensured to meet a process requirement, it is ensured that the subsequent PMOS region 110P (as shown in fig. 8) can share the same work function layer, and the threshold voltages of other devices in the PMOS region 110P can also meet the process requirement.

Therefore, in this embodiment, in the first P-type source/drain doping layer 160, the atomic number percentage content of Ge is 15% to 85%, and the doping concentration of B ions is 1.0E18atom/cm³To 5.0E22atom/cm³. Wherein, the content of Ge in atomic number percentage refers to the percentage of Ge in atomic number to the total atomic number of G and Si.

In this embodiment, the threshold voltage of the first PMOS region 111P is made to meet the process requirement by adjusting the atomic number percentage content of Ge, or adjusting the doping concentration of B ions, or adjusting the atomic number percentage content of Ge and the doping concentration of B ions together.

In this embodiment, in the step of forming the first P-type source-drain doping layer 160, the first P-type source-drain doping layer 160 is formed in the fin portions 120 on two sides of the first PMOS region 111P gate structure 130, and the first P region groove 151 is correspondingly formed in the fin portions 120 on two sides of the first PMOS region 111P gate structure 130.

Specifically, as shown in fig. 13, a first mask layer (not shown) is formed on the substrate 100 (as shown in fig. 8), where the first mask layer covers the top and sidewalls of the fin 120 of the first PMOS region 111P and the second PMOS region 112P, and also covers the top and sidewalls of the fin 120 of the first NMOS region 111N (as shown in fig. 8) and the second NMOS region 112N (as shown in fig. 8).

In this embodiment, in the step of forming the first P-type source-drain doping layer 160 (as shown in fig. 15), the first mask layer is a first P-region mask layer (i.e., PSR) 210.

The process of forming the first P-region mask layer 210 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the first P-region mask layer 210 is formed by an atomic layer deposition process, so that the first P-region mask layer 210 conformally covers the top and sidewalls of the fin 120 exposed by the gate structure 130, the top and sidewalls of the gate structure 130, and the isolation structure 101 exposed by the gate structure 130.

It should be noted that the material of the first P-region mask layer 210 is a material with a common process and high process compatibility, and the first P-region mask layer 210 needs to be removed subsequently, so that the material of the first P-region mask layer 210 is also a material that is easy to remove, and the process for removing the first P-region mask layer 210 has little influence on other film structures. Therefore, the material of the first P-region mask layer 210 may be silicon nitride, silicon oxide, boron nitride, or silicon oxynitride. In this embodiment, the first P-region mask layer 210 is made of silicon nitride.

Referring to fig. 14, the first P-region mask layer 210 on the fin portions 120 on the two sides of the first PMOS region 111P gate structure 130 is etched to expose the fin portions 120 on the two sides of the first PMOS region 111P gate structure 130, and the exposed fin portions 120 with a partial thickness are also etched, so as to form the first P-region groove 151 in the etched fin portions 120.

It should be noted that before the etching the first P-region mask layer 210, the method further includes: a first photoresist layer (not shown) is formed on the first PMOS region 111P, and the first photoresist layer covers the second PMOS region 112P, the first NMOS region 111N and the first P region mask layer 210 of the second NMOS region 112N, and exposes a portion of the first P region mask layer 210 at two sides of the first PMOS region 111P gate structure 130. The first photoresist layer is used to protect the second PMOS region 112P, the first NMOS region 111N, and the first P region mask layer 210 of the second NMOS region 112N, and the first photoresist layer may also cover an area of the first PMOS region 111P that is not desired to be etched.

Specifically, a dry etching process is adopted to etch and remove the first P region mask layer 210 on the tops of the fin portions 120 on two sides of the first PMOS region 111P gate structure 130; in the dry etching process, the first P region mask layer 210 on the top of the first PMOS region 111P gate structure 130 and on a part of the isolation structure 101 is further etched and removed; after the tops of the fins 120 on the two sides of the first PMOS region 111P gate structure 130 are exposed, the exposed materials of the fins 120 are etched continuously to form the first P region groove 151.

In this embodiment, after the first P-region groove 151 is formed, a wet stripping or ashing process is used to remove the first photoresist layer.

Referring to fig. 15, the first P-type source-drain doped layer 160 is formed in the first P-region groove 151 (shown in fig. 14).

The higher the doping concentration of the first P-type ions in the first P-type source-drain doping layer 160 is, the more obvious the pressure stress providing effect is correspondingly played; however, in the semiconductor process, the subsequent process further includes forming a metal silicide (silicide) layer on the first P-type source/drain doping layer 160, and forming a contact hole plug (CT) electrically connected to the metal silicide layer on the metal silicide layer, where the doping concentration of the first P-type ions is too high, which may also cause a problem of too large contact resistance.

Therefore, in order to ensure the compressive stress effect of the first P-type source-drain doped layer 160 and reduce the contact resistance, the step of forming the first P-type source-drain doped layer 160 in the first P-region groove 151 includes: a bottom first P-type source-drain doping layer 161 is formed in the first P-region groove 151, and a top first P-type source-drain doping layer 162 is formed on the bottom first P-type source-drain doping layer 161.

In this embodiment, in order to effectively reduce the contact resistance, the first P-type ions are not doped in the top first P-type source/drain doping layer 162, and the material of the top first P-type source/drain doping layer 162 is the same as the material of the first P-type epitaxial layer. In other embodiments, the first P-type source/drain doping layer on the top may also be doped with the first P-type ions, and the concentration of the doped ions in the first P-type source/drain doping layer on the top is relatively low.

In this embodiment, in order to facilitate formation of a subsequent film layer, after the first P-type source-drain doping layer 160 is formed, the first P-region mask layer 210 is removed, so that a larger spatial position is provided for subsequently forming a second P-region mask layer, the second P-region mask layer can cover the first P-type source-drain doping layer 160, and damage to the surface of the first P-type source-drain doping layer 160 caused by a subsequent process is avoided.

It should be noted that, in order to further protect the surface of the first P-type source/drain doping layer 160, after the first P-type source/drain doping layer 160 is formed, the method further includes: the surface of the first P-type source/drain doping layer 160 is oxidized, and a first oxide layer (not shown) is formed on the surface of the first P-type source/drain doping layer 160, where the oxidation may be dry oxygen oxidation, wet oxygen oxidation, or water vapor oxidation. In other embodiments, the first oxide layer may not be formed.

Referring to fig. 16 to 18 in combination, fig. 16 is a cross-sectional view based on fig. 15, wherein a second groove (not shown) is formed in the substrate 100 (shown in fig. 8) at two sides of the gate structure 130 of the second PMOS region 112P; through a second epitaxial process, a second epitaxial layer (not labeled) is formed in the second groove, and in-situ self-doping is performed during the process of forming the second epitaxial layer, so as to form a second P-type source-drain doping layer 170 (as shown in fig. 18).

In this embodiment, the second recess formed in the second PMOS region 112P substrate 100 is a second P region recess 152 (as shown in fig. 17), the second epitaxial process is a second P-type epitaxial process, a second P-type epitaxial layer (not shown) is formed in the second P region recess 152 by the second P-type epitaxial process, and second P-type ions are self-doped in situ during the process of forming the second P-type epitaxial layer.

It should be noted that, the shape and size of the second P-region groove 152 both affect the device performance, so in order to reduce the complexity of the process for forming the semiconductor structure and facilitate the adjustment of the device threshold voltage, the shape and size of the second P-region groove 152 are the same as those of the first P-region groove 151 (as shown in fig. 14).

In this embodiment, the second P-region groove 152 is U-shaped. In other embodiments, the shape of the second P-zone groove may also be bowl-shaped or Sigma-shaped.

In this embodiment, the second P-type epitaxy process is a selective epitaxy process, and correspondingly, the top of the second P-type source-drain doping layer 170 is higher than the top of the second P-region groove 152. In other embodiments, the top of the second P-type source-drain doped layer may be flush with the top of the second P-region groove.

The second P-type epitaxial layer is made of SiGe, GeSn or GeSb, and the second P-type ions can be B ions, Ga ions or In ions. In this embodiment, the second P-type epitaxial layer is made of SiGe, and the second P-type ions are B ions, so that the second P-type source/drain doping layer 170 is made of SiGe doped with B ions, the atomic number percentage content of Ge is 15% to 85%, and the doping concentration of B ions is 1.0E18atom/cm³To 5.0E22atom/cm³。

Correspondingly, the parameters of the second P-type epitaxial process include: the carrier gas is H₂The etching gas is HCl, and the silicon source gas comprises SiH₄、SiH₂Cl₂、SiH₃Cl and SiHCl₃The germanium source gas comprises GeH₄、GeH₃Cl、GeH₂Cl₂And GeHCl₃Wherein the boron source gas comprises BH₃、BH₂Cl and BHCl₃One or more of (a).

In this embodiment, the device threshold voltage of the second PMOS region 112P is greater than the device threshold voltage of the first PMOS region 111P, so that the doping ion concentration of the second P-type source-drain doping layer 170 is less than the doping ion concentration of the first P-type source-drain doping layer 160 (as shown in fig. 15).

The device threshold voltage of the second PMOS region 112P meets the process requirements by adjusting the atomic number percentage content of Ge, or adjusting the doping concentration of B ions, or adjusting the atomic number percentage content of Ge and the doping concentration of B ions together.

For a specific description of the second P-type source-drain doping layer 170, reference may be made to the corresponding description of the first P-type source-drain doping layer 160, and details are not repeated here.

In this embodiment, the second P-type source-drain doping layer 170 is formed in the fin portions 120 on two sides of the second PMOS region 112P gate structure 130, and the second P region groove 152 is correspondingly formed in the fin portions 120 on two sides of the second PMOS region 112P gate structure 130.

Specifically, the step of forming the second P-type source-drain doping layer 170 includes: as shown in fig. 16, a second mask layer (not labeled) is formed on the substrate 100 (as shown in fig. 8), where the second mask layer covers the top and the sidewall of the fin 120 in the first PMOS region 111P and the second PMOS region 112P, and the top and the sidewall of the fin 120 in the first NMOS region 111N (as shown in fig. 8) and the second NMOS region 112N (as shown in fig. 8), and the second mask layer also covers the first P-type source-drain doping layer 160; as shown in fig. 17, etching the second mask layer on the fin portions 120 on the two sides of the second PMOS region 112P gate structure 130 to expose the fin portions 120 on the two sides of the second PMOS region 112P gate structure 130, and also etching the exposed fin portions 120 with a partial thickness, so as to form the second P-region groove 152 in the etched fin portions 120; as shown in fig. 18, the second P-type source-drain doped layer 170 is formed in the second P-region groove 152 (shown in fig. 17).

In this embodiment, in the step of forming the second P-type source-drain doping layer 170, the second mask layer is a second P-region mask layer 220.

In this embodiment, the second P-region mask layer 220 is formed by an atomic layer deposition process, so that the second P-region mask layer 220 conformally covers the top and the sidewall of the fin 120 exposed by the gate structure 130, the top and the sidewall of the gate structure 130, the second P-type source/drain doping layer 170, and the isolation structure 101 exposed by the gate structure 130.

The second P-region mask layer 220 may be made of silicon nitride, silicon oxide, boron nitride, or silicon oxynitride. In this embodiment, the second P-region mask layer 220 is made of silicon nitride.

In order to reduce the contact resistance while ensuring the compressive stress effect of the second P-type source-drain doping layer 170, the step of forming the second P-type source-drain doping layer 170 includes: a bottom second P-type source-drain doping layer 171 is formed in the second P-region groove 152 (as shown in fig. 18), and a top second P-type source-drain doping layer 172 is formed on the bottom second P-type source-drain doping layer 171 (as shown in fig. 18).

For specific description of the bottom second P-type source-drain doping layer 171 and the top second P-type source-drain doping layer 172, reference may be made to the foregoing description of the bottom first P-type source-drain doping layer 161 (as shown in fig. 15) and the top first P-type source-drain doping layer 162 (as shown in fig. 15), and details are not repeated herein.

In this embodiment, after the second P-type source-drain doping layer 170 is formed, the second P-region mask layer 220 is removed, so that a larger spatial position is provided for the subsequent formation of a first N-region mask layer, and the first N-region mask layer can cover the first P-type source-drain doping layer 160 and the second P-type source-drain doping layer 170, thereby preventing the subsequent processes from damaging the surfaces of the first P-type source-drain doping layer 160 and the second P-type source-drain doping layer 170.

It should be further noted that, in order to further protect the surface of the second P-type source/drain doping layer 170, after the second P-type source/drain doping layer 170 is formed, the method further includes: and performing oxidation treatment on the surface of the second P-type source-drain doping layer 170 to form a second oxidation layer (not shown) on the surface of the second P-type source-drain doping layer 170, wherein the oxidation treatment may be dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation. In other embodiments, the second oxide layer may not be formed.

For a specific description of the process steps for forming the second P-type source/drain doping layer 170, reference may be made to the corresponding description of the process steps for forming the first P-type source/drain doping layer 170, and details are not repeated here.

Referring to fig. 19 to 21, fig. 19 to 21 are schematic cross-sectional views of the first NMOS region and the second NMOS region along the extending direction of the fin portion, and a first groove (not labeled) is formed in the substrate 100 (as shown in fig. 8) at two sides of the gate structure 130 of the first NMOS region 111N; through a first epitaxial process, a first epitaxial layer (not labeled) is formed in the first groove, and in-situ self-doping is performed during the process of forming the first epitaxial layer, so as to form a first N-type source-drain doping layer 180 (as shown in fig. 21).

In this embodiment, the first recess formed in the first NMOS region 111N substrate 100 is a first N region recess 153 (as shown in fig. 20), the first epitaxial process is a first N type epitaxial process, a first N type epitaxial layer (not shown) is formed in the first N region recess 153 by the first N type epitaxial process, and the first N type ions are self-doped in situ during the process of forming the first N type epitaxial layer.

In this embodiment, the first N-region groove 153 has a U-shape. In other embodiments, the first N region groove may also be bowl-shaped or Sigma-shaped.

In this embodiment, the first N-type epitaxy process is a selective epitaxy process, and correspondingly, the top of the first N-type source/drain doping layer 180 is higher than the top of the first N-region groove 153. In other embodiments, the top of the first N-type source/drain doping layer may be flush with the top of the first N-region groove.

The first N-type epitaxial layer is made of Si or SiC, and the first N-type ions can be P ions, As ions or Sb ions. In this embodiment, the first N-type epitaxial layer is made of Si, and the first N-type ions are P ions, so that the first N-type source/drain doping layer 180 is made of Si doped with P ions, that is, the first N-type source/drain doping layer 180 is made of SiP.

Correspondingly, the parameters of the first N-type epitaxial process include: the carrier gas is H₂The etching gas is HCl, and the silicon source gas comprises SiH₄、SiH₂Cl₂、SiH₃Cl and SiHCl₃Including a phosphorus source gas including PH₃、PH₂Cl and PHCl₂One ofOr a plurality thereof.

It should be noted that, in the first N-type source-drain doping layer 180, the doping concentration of P ions is set reasonably according to the actual process conditions, and while the threshold voltage of the device in the first NMOS region 111N is ensured to meet the process requirements, it is ensured that the subsequent NMOS region 110N (as shown in fig. 8) can share the same work function layer, and the threshold voltages of other devices in the NMOS region 110N can also meet the process requirements.

For this reason, in the present embodiment, the doping concentration of P ions in the first N-type source/drain doping layer 180 is 1.0E18atom/cm³To 5.0E22atom/cm³。

In this embodiment, the first N-type source/drain doping layer 180 is formed in the fin portions 120 on both sides of the first NMOS region 111N gate structure 130, and the first N region groove 153 is correspondingly formed in the fin portions 120 on both sides of the first NMOS region 111N gate structure 130.

Specifically, the step of forming the first N-type source-drain doping layer 180 includes: as shown in fig. 19, a first mask layer (not labeled) is formed on the substrate 100 (as shown in fig. 8), the first mask layer 230 covers the top and the sidewall of the fin 120 of the first PMOS region 111P (as shown in fig. 18) and the second PMOS region 112P (as shown in fig. 18), and the top and the sidewall of the fin 120 of the first NMOS region 111N and the second NMOS region 112N, and the first mask layer further covers the first P-type source-drain doping layer 160 and the second P-type source-drain doping layer 170; as shown in fig. 20, etching the first mask layer on the fin portions 120 on the two sides of the first NMOS region 111N gate structure 130 to expose the fin portions 120 on the two sides of the first NMOS region 111N gate structure 130, and also etching the exposed fin portions 120 with a partial thickness, so as to form the first N region groove 153 in the etched fin portions 120; as shown in fig. 21, the first N-type source/drain doped layer 180 is formed in the first N-region groove 153 (shown in fig. 20).

In this embodiment, in the step of forming the first N-type source/drain doping layer 180, the first mask layer is a first N-region mask layer (i.e., NSR) 230.

In this embodiment, the first N-region mask layer 230 is formed by an atomic layer deposition process, so that the first N-region mask layer 230 conformally covers the top and the sidewall of the fin 120 exposed from the gate structure 130, the top and the sidewall of the gate structure 130, the first P-type source/drain doping layer 160, the second P-type source/drain doping layer 170, and the isolation structure 101 exposed from the gate structure 130.

The first N-region mask layer 230 may be made of silicon nitride, silicon oxide, boron nitride, or silicon oxynitride. In this embodiment, the first N-region mask layer 230 is made of silicon nitride.

For a detailed description of the step of forming the first N-type source/drain doping layer 180, reference may be made to the corresponding description of forming the first P-type source/drain doping layer 160 (as shown in fig. 15), which is not described herein again.

In this embodiment, after the first N-type source-drain doping layer 180 is formed, the first N-region mask layer 230 is removed, so that a larger spatial position is provided for a subsequent formation of a second N-region mask layer, and the second N-region mask layer can cover the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170 and the first N-type source-drain doping layer 180, thereby preventing subsequent processes from damaging the surfaces of the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170 and the first N-type source-drain doping layer 180.

It should be further noted that, in order to further protect the surface of the first N-type source/drain doping layer 180, after the first N-type source/drain doping layer 180 is formed, the method further includes: and performing oxidation treatment on the surface of the first N-type source/drain doping layer 180 to form a third oxidation layer (not shown) on the surface of the first N-type source/drain doping layer 180, wherein the oxidation treatment may be dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation. In other embodiments, the third oxide layer may not be formed.

Referring to fig. 22 to 24 in combination, fig. 22 is a schematic cross-sectional view based on fig. 21, wherein a second recess (not shown) is formed in the substrate 100 (as shown in fig. 8) at two sides of the gate structure 130 of the second NMOS region 112N; through a second epitaxial process, a second epitaxial layer (not labeled) is formed in the second groove, and in-situ self-doping is performed in the process of forming the second epitaxial layer, so as to form a second N-type source-drain doping layer 190 (as shown in fig. 24).

In this embodiment, the second recess formed in the substrate 100 of the second NMOS region 112N is a second N-region recess 154 (as shown in fig. 23), the second epitaxial process is a second N-type epitaxial process, a second N-type epitaxial layer (not shown) is formed in the second N-region recess 154 by the second N-type epitaxial process, and second N-type ions are self-doped in situ during the process of forming the second N-type epitaxial layer.

It should be noted that the shape and size of the second N-region recess 154 may affect the device performance, and therefore, in order to reduce the complexity of the process for forming the semiconductor structure and facilitate the adjustment of the device threshold voltage, the shape and size of the second N-region recess 154 are the same as those of the first N-region recess 153 (as shown in fig. 20).

In this embodiment, the second N-region groove 154 has a U-shape. In other embodiments, the shape of the second N-region groove may also be bowl-shaped or Sigma-shaped.

In this embodiment, the second N-type epitaxy process is a selective epitaxy process, and correspondingly, the top of the second N-type source/drain doping layer 190 is higher than the top of the second N-region groove 154. In other embodiments, the top of the second N-type source/drain doping layer may be flush with the top of the second N-region groove.

The material of the second N-type epitaxial layer is Si or SiC, and the second N-type ions can be P ions, As ions or Sb ions. In this embodiment, the second N-type epitaxial layer is made of Si, and the second N-type ions are P ions, so that the second N-type source/drain doping layer 190 is made of Si doped with P ions, and the doping concentration of the P ions is 1.0E18atom/cm³To 5.0E22atom/cm³。

Correspondingly, the parameters of the second N-type epitaxy process include: the carrier gas is H₂The etching gas is HCl, and the silicon source gas comprises SiH₄、SiH₂Cl₂、SiH₃Cl and SiHCl₃Including a phosphorus source gas including PH₃、PH₂Cl and PHCl₂One ofOr a plurality thereof.

In this embodiment, the device threshold voltage of the second NMOS region 112N is greater than the device threshold voltage of the first NMOS region 111N, so that the doping ion concentration of the second N-type source-drain doping layer 190 is less than the doping ion concentration of the first N-type source-drain doping layer 180 (as shown in fig. 21). The doping concentration of the P ions is adjusted, so that the device threshold voltage of the second NMOS region 112N meets the process requirement.

For specific description of the second N-type source/drain doping layer 190, reference may be made to the corresponding description of the first N-type source/drain doping layer 180, which is not described herein again.

In this embodiment, the second N-type source/drain doping layer 190 is formed in the fin portions 120 on both sides of the second NMOS region 112N gate structure 130, and the second N-region recess 154 is correspondingly formed in the fin portions 120 on both sides of the second NMOS region 112N gate structure 130.

Specifically, the step of forming the second N-type source-drain doping layer 190 includes: as shown in fig. 22, forming a second mask layer (not labeled) on the substrate 100 (as shown in fig. 8), where the second mask layer covers the top and the sidewall of the fin 120 of the first PMOS region 111P (as shown in fig. 18) and the second PMOS region 112P (as shown in fig. 18), and the top and the sidewall of the fin 120 of the first NMOS region 111N and the second NMOS region 112N, and the second mask layer further covers the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170, and the first N-type source-drain doping layer 180; as shown in fig. 23, etching the second mask layer on the fin portions 120 on the two sides of the second NMOS region 112N gate structure 130 to expose the fin portions 120 on the two sides of the second NMOS region 112N gate structure 130, and also etching the exposed fin portions 120 with a partial thickness, so as to form the second N-region groove 154 in the etched fin portions 120; as shown in fig. 24, the second N-type source/drain doped layer 190 is formed in the second N-region recess 154 (shown in fig. 23).

In this embodiment, in the step of forming the second N-type source/drain doping layer 190, the second mask layer is a second N-region mask layer 240.

In this embodiment, the second N-region mask layer 240 is formed by an atomic layer deposition process, so that the second N-region mask layer 240 conformally covers the top and the sidewall of the fin 120 exposed by the gate structure 130, the top and the sidewall of the gate structure 130, the first P-type source/drain doping layer 160, the second P-type source/drain doping layer 170, the first N-type source/drain doping layer 180, and the isolation structure 101 exposed by the gate structure 130.

The second N-region mask layer 240 may be made of silicon nitride, silicon oxide, boron nitride, or silicon oxynitride. In this embodiment, the second N-region mask layer 240 is made of silicon nitride.

For a specific description of the process steps for forming the second N-type source/drain doping layer 190, reference may be made to the corresponding description of the process steps for forming the first N-type source/drain doping layer 180, which is not repeated herein.

In this embodiment, after the second N-type source-drain doping layer 190 is formed, the second N-region mask layer 240 is removed, so as to provide a larger spatial position for the subsequent formation of the high-k gate dielectric layer, the work function layer and other film layers, which is beneficial to improving the formation quality of the subsequent film layers. In other embodiments, the second N-region mask layer may be retained.

It should be noted that, in order to further protect the surface of the second N-type source/drain doping layer 190, after the second N-type source/drain doping layer 190 is formed, the method further includes: and performing oxidation treatment on the surface of the second N-type source/drain doping layer 190 to form a fourth oxidation layer (not shown) on the surface of the second N-type source/drain doping layer 190, where the oxidation treatment may be dry oxygen oxidation, wet oxygen oxidation, or water vapor oxidation. In other embodiments, the fourth oxide layer may not be formed.

It should be further noted that, in this embodiment, in the process of forming the first P-type source-drain doping layer 160 (as shown in fig. 18), the second P-type source-drain doping layer 170 (as shown in fig. 18), the first N-type source-drain doping layer 180 (as shown in fig. 24), and the second N-type source-drain doping layer 190 (as shown in fig. 24), the epitaxial growth and the in-situ doping are implemented in the same step as an example. In other embodiments, the following may also be: after an epitaxial layer is formed, the epitaxial layer is doped.

Specifically, the step of forming the first P-type source-drain doping layer and the second P-type source-drain doping layer includes: forming P-region grooves in the substrate at two sides of the gate structures of the first PMOS region and the second PMOS region; forming a P-type epitaxial layer in the P-region groove through a P-type epitaxial process; after the P-type epitaxial layer is formed, carrying out first P-type doping treatment on the P-type epitaxial layer of the first PMOS region to form a first P-type source drain doping layer, carrying out second P-type doping treatment on the P-type epitaxial layer of the second PMOS region to form a second P-type source drain doping layer, wherein the ion doping concentration of the second P-type doping treatment is smaller than that of the first P-type doping treatment.

Similarly, the step of forming the first N-type source/drain doping layer and the second N-type source/drain doping layer includes: forming N-region grooves in the substrate at two sides of the grid structures of the first NMOS region and the second NMOS region; forming an N-type epitaxial layer in the N-region groove through an N-type epitaxial process; after the N-type epitaxial layer is formed, carrying out first N-type doping treatment on the N-type epitaxial layer of the first NMOS area to form a first N-type source drain doping layer, carrying out second N-type doping treatment on the N-type epitaxial layer of the second NMOS area to form a second N-type source drain doping layer, wherein the ion doping concentration of the second N-type doping treatment is smaller than that of the first N-type doping treatment.

With reference to fig. 25 and 26, fig. 25 is a schematic cross-sectional view of a PMOS region and an NMOS region along a direction perpendicular to an extending direction of a fin portion, fig. 26 is a schematic cross-sectional view of a PMOS region and an NMOS region along a direction of extending a fin portion, an interlayer dielectric layer 102 is formed on the substrate 100 (shown in fig. 8) exposed by the gate structure 130 (shown in fig. 26), the interlayer dielectric layer 102 covers the source-drain doping layer (not shown), and the interlayer dielectric layer 102 exposes the top of the gate structure 130.

The interlayer dielectric layer 102 is used for realizing electrical isolation between adjacent devices, and the interlayer dielectric layer 102 is also used for defining the size and the position of a metal gate structure formed subsequently.

The interlayer dielectric layer 102 is made of an insulating material. In this embodiment, the interlayer dielectric layer 102 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

In this embodiment, the interlayer dielectric layer 102 is formed on the isolation structure 101 exposed by the gate structure 130, and the interlayer dielectric layer 102 covers the first P-type source-drain doping layer 160 (as shown in fig. 25), the second P-type source-drain doping layer 170 (as shown in fig. 25), the first N-type source-drain doping layer 180 (as shown in fig. 25), and the second N-type source-drain doping layer 190 (as shown in fig. 25).

In this embodiment, the gate mask layer 200 is formed on the top of the gate structure 130 (as shown in fig. 18 and 24), so that the gate mask layer 200 is also removed in the process of forming the interlayer dielectric layer 102, that is, the top of the interlayer dielectric layer 102 is flush with the top of the gate structure 130.

It should be noted that, for convenience of illustration, fig. 25 illustrates a cross-sectional view of the NMOS region 110N and the PMOS region 110P, that is, fig. 25 can be used to characterize any one of the NMOS regions in the first PMOS region 111P and the second PMOS region 112P, and any one of the PMOS regions in the first NMOS region 111N and the second NMOS region 112N.

Referring to fig. 27, fig. 27 is a cross-sectional view based on fig. 26, wherein the gate structure 130 (shown in fig. 26) is removed and a gate opening 105 is formed in the interlayer dielectric layer 102.

The gate opening 105 is used to provide a spatial location for the formation of a subsequent metal gate structure.

In this embodiment, the gate opening 105 crosses over the fin 120 and exposes a portion of the top and a portion of the sidewall of the fin 120.

Referring to fig. 28 to 29 in combination, fig. 28 is a schematic cross-sectional view based on fig. 27, and fig. 29 is an enlarged view of a dashed box a and a dashed box B in fig. 28, wherein a high-k gate dielectric layer 510 is formed on the bottom and sidewalls of the gate opening 105 (shown in fig. 27); forming a work function layer (not labeled) on the high-k gate dielectric layer 510; a gate electrode layer 550 is formed within the gate opening 105 in which the work function layer is formed, and the high-k gate dielectric layer 510, the work function layer, and the gate electrode layer 550 are used to form a metal gate structure (not shown).

The high-k gate dielectric layer 510 is made of a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 510 is HfO₂. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO₂Or Al₂O₃。

In this embodiment, the work function layer of the PMOS region 110P is a P-type work function layer 530, and the work function layer of the NMOS region 110N is an N-type work function layer 540.

The P-type work function layer 530 is used to adjust the threshold voltage of the plurality of PMOS devices. In this embodiment, the P-type work function layer 530 is used to adjust the threshold voltages of the P-type low threshold voltage device and the P-type standard threshold voltage device.

Correspondingly, the material of the P-type work function layer 530 is a P-type work function material. The material work function of the P-type work function layer 530 ranges from 5.1ev to 5.5ev, e.g., 5.2ev, 5.3ev, or 5.4 ev; the material of the P-type work function layer 530 is one or more of TiN, TaN, TaSiN, TiSiN, TaAlN or TiAlN. In this embodiment, the P-type work function layer 530 is made of TiN.

Specifically, the step of forming the P-type work function layer 530 includes: forming a P-type work function material layer on the high-k gate dielectric layer 510 of the PMOS region 110P and the NMOS region 110N; forming a fourth photoresist layer (not shown) on the P-type work function material layer of the PMOS region 110P to expose the P-type work function material layer of the NMOS region 110N; etching and removing the P-type work function material layer of the NMOS region 110N by using the fourth photoresist layer as a mask, and reserving the P-type work function material layer of the PMOS region 110P as the P-type work function layer 530; and removing the fourth photoresist layer by adopting a wet photoresist removing or ashing process.

The thickness of the P-type work function layer 530, the concentration of the doped ions of the first P-type source-drain doping layer 160, and the concentration of the doped ions of the second P-type source-drain doping layer 170 are matched with each other, so that the threshold voltage of each PMOS device can meet the process requirements. This implementationIn one example, the P-type work function layer 530 has a thickness of

To

The N-type work function layer 540 is used to adjust the threshold voltage of the NMOS device. In this embodiment, the N-type work function layer 540 is used to adjust the threshold voltages of the N-type standard threshold voltage device and the N-type low threshold voltage device.

Correspondingly, the material of the N-type work function layer 540 is an N-type work function material. The material work function of the N-type work function layer 540 ranges from 3.9ev to 4.5ev, such as 4ev, 4.1ev, or 4.3 ev; the material of the N-type work function layer 540 is one or more of TiAl, Mo, MoN, AlN or TiAl C. In this embodiment, the material of the N-type work function layer 540 is TiAl.

The thickness of the N-type work function layer 540, the concentration of the doped ions of the first N-type source drain doping layer 180, and the concentration of the doped ions of the second N-type source drain doping layer 190 are matched with each other, so that the threshold voltage of each NMOS device can meet the process requirements. In this embodiment, the thickness of the N-type work function layer 540 is

To

Specifically, the step of forming the N-type work function layer 540 includes: an N-type work function material layer is formed on the high-k gate dielectric layer 510 of the NMOS region 110N, the N-type work function material layer further covers the P-type work function layer 530, and the N-type work function material layer on the NMOS region 110N serves as the N-type work function layer 540.

In this embodiment, in order to reduce the process steps and save the mask, the N-type work function material layer in the PMOS region 110P is retained during the process of forming the N-type work function layer 540, i.e., the N-type work function layer 540 also covers the P-type work function layer 530.

Accordingly, the gate electrode layer 550 covers the N-type work function layer 540.

In this embodiment, the material of the gate electrode layer 550 is W. In other embodiments, the material of the gate electrode layer may also be a conductive material such as Al, Cu, Ag, Au, Pt, Ni, or Ti.

In this embodiment, the metal gate structure formed in the PMOS region 110P is a first metal gate structure 610, and the first metal gate structure 610 includes a high-k gate dielectric layer 510, a P-type work function layer 530, an N-type work function layer 540, and a gate electrode layer 550 located in the PMOS region 110P; the metal gate structure formed in the NMOS region 110N is a second metal gate structure 620, and the second metal gate structure 620 includes a high-k gate dielectric layer 510, an N-type work function layer 540, and a gate electrode layer 550, which are located in the NMOS region 110N.

Before forming the P-type work function layer 530 and the N-type work function layer 540, the method further includes: a capping layer 520 is formed on the high-k gate dielectric layer 510.

The cap layer 520 may protect the high-k gate dielectric layer 510, so as to prevent damage to the high-k gate dielectric layer 510 caused by a subsequent process, and the cap layer 520 may further facilitate blocking diffusion of easily diffusible ions in the gate electrode layer 550 into the high-k gate dielectric layer 510. In this embodiment, the capping layer 520 is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 28 to 29 together, there are shown structure diagrams of an embodiment of the semiconductor structure of the present invention, fig. 28 is a schematic cross-sectional view of a PMOS region and an NMOS region along a fin extending direction (indicated by X1X2 in fig. 8), and fig. 29 is an enlarged view of a dashed box a and a dashed box B in fig. 28.

Referring to fig. 28 to 29, in combination with fig. 18 and 24, the semiconductor structure includes: a substrate 100 (as shown in fig. 8), the substrate 100 including device regions (not labeled), the types of the device regions including one or both of an NMOS region 110N and a PMOS region 110P, the same type of the device regions being used to form devices with different threshold voltages; a metal gate structure (not labeled) on the substrate 100; and source and drain doping layers (not labeled) located in the substrate 100 at two sides of the metal gate structure, wherein the source and drain doping layers corresponding to different threshold voltages have different doping ion concentrations in the same type of device region.

In the present embodiment, the semiconductor structure is a finfet transistor, and thus the substrate 100 includes a substrate 110 and a plurality of discrete fins 120 on the substrate 110. In other embodiments, the semiconductor structure may also be a planar transistor, and the base is correspondingly a substrate.

Specifically, a first device region in the NMOS region 110N is a first NMOS region 111N, a second device region in the NMOS region 110N is a second NMOS region 112N, a first device region in the PMOS region 110P is a first PMOS region 111P, a second device region in the PMOS region 110P is a second PMOS region 112P, a device threshold voltage of the first NMOS region 111N is smaller than a device threshold voltage of the second NMOS region 112N, and a device threshold voltage of the first PMOS region 111P is smaller than a device threshold voltage of the second PMOS region 112P.

It should be further noted that, for convenience of illustration, fig. 28 and fig. 29 illustrate cross-sectional views of the NMOS region 110N and the PMOS region 110P, that is, fig. 28 and fig. 29 can be used to characterize any one of the first PMOS region 111P and the second PMOS region 112P, and any one of the first NMOS region 111N and the second NMOS region 112N.

Further, with continued reference to fig. 28, the semiconductor structure further comprises: and the isolation structure 101 is located on the substrate 110 where the fin portion 120 is exposed, the isolation structure 101 covers a part of the sidewall of the fin portion 120, and the top of the isolation structure 101 is lower than the top of the fin portion 120.

The metal gate structure crosses over the fin 120 and covers a portion of the top and a portion of the sidewalls of the fin 120. Specifically, the metal gate structure includes a high-k gate dielectric layer 510 (as shown in fig. 29) on the substrate 100, a work function layer (not labeled) on the high-k gate dielectric layer 510, and a gate electrode layer 550 (as shown in fig. 28 or 29) on the work function layer.

In this embodiment, the work function layer in the PMOS region 110P is a P-type work function layer 530 (as shown in fig. 29), and the work function layer in the NMOS region 110N is an N-type work function layer 540 (as shown in fig. 29).

The P-type work function layer 530 is used to adjust the threshold voltage at the PMOS device. In this embodiment, the P-type work function layer 530 is used to adjust the threshold voltages of the P-type low threshold voltage device and the P-type standard threshold voltage device.

In this embodiment, the thickness of the P-type work function layer 530 is

To

In this embodiment, the thickness of the N-type work function layer 540 is

To

It should be noted that, in the formation process of the semiconductor structure, in order to reduce the process steps and save the mask, when the N-type work function layer 540 is formed, the N-type work function layer 540 located in the PMOS region 110P is retained, that is, the N-type work function layer 540 also covers the P-type work function layer 530. Accordingly, the gate electrode layer 550 covers the N-type work function layer 540.

In this embodiment, the metal gate structure in the PMOS region 110P is a first metal gate structure 610 (as shown in fig. 29), where the first metal gate structure 610 includes a high-k gate dielectric layer 510, a P-type work function layer 530, an N-type work function layer 540, and a gate electrode layer 550 in the PMOS region 110P; the metal gate structure in the NMOS region 110N is a second metal gate structure 620 (as shown in fig. 29), and the second metal gate structure 620 includes a high-k gate dielectric layer 510, an N-type work function layer 540, and a gate electrode layer 550 in the NMOS region 110N.

It should be further noted that the semiconductor structure further includes: and a capping layer 520, which is located between the high-k gate dielectric layer 510 of the PMOS region 110P and the P-type work function layer 530, and between the high-k gate dielectric layer 510 of the NMOS region 110N and the N-type work function layer 540.

The cap layer 520 may protect the high-k gate dielectric layer 510, so as to prevent the high-k gate dielectric layer 510 from being damaged, and the cap layer 520 may further facilitate blocking diffusion of easily-diffusible ions in the gate electrode layer 550 into the high-k gate dielectric layer 510. In this embodiment, the capping layer 520 is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN.

In this embodiment, in the same type of device region, the source-drain doped layers corresponding to different threshold voltages have different dopant ion concentrations.

In the same type of device region, the greater the concentration of the doped ions of the source and drain doped layers is, the smaller the external parasitic resistance of the device is, and the smaller the threshold voltage of the device is, so that the adjustment of the threshold voltage of each device can be realized by adjusting the concentration of the doped ions of each source and drain doped layer in the same type of device region, and the same work function layer can be correspondingly shared by the same type of device region. Therefore, compared with the scheme that source-drain doped layers with the same doped ion concentration are formed, and the threshold voltage is adjusted by adjusting the thickness of the work function layer, the threshold voltage of each device is easy to be adjusted respectively by adjusting the doped ion concentration, the process steps for forming the work function layer can be simplified, the times of photoetching, etching, ashing and cleaning processes are reduced, the adverse effect of the process for forming the work function layer on the performance of the device can be correspondingly reduced, and the cross effect of the threshold voltage adjustment of any device on other devices can be reduced; in conclusion, the scheme of the invention is beneficial to reducing the process difficulty of adjusting the threshold voltage and can also reduce the adverse effect of the adjustment of the threshold voltage on the performance and yield of the device.

In this embodiment, the device region includes an NMOS region 110N and a PMOS region 110P, and accordingly, by adjusting the concentration of doped ions in each source-drain doped layer in the same type of device region, it is further convenient to adjust the threshold voltages of the PMOS device and the NMOS device, respectively, so as to prevent cross effects between the PMOS device and the NMOS device, and further reduce the process difficulty of adjusting the threshold voltage, and improve the device performance and yield.

In this embodiment, the source-drain doping layer located in the first device region (not labeled) is a first source-drain doping layer (not labeled), and the source-drain doping layer located in the second device region (not labeled) is a second source-drain doping layer (not labeled).

In this embodiment, the source-drain doping layer located in the PMOS region 110P is a P-type source-drain doping layer (not labeled), and the P-type source-drain doping layer is located in the fin portion 120 on both sides of the first metal gate structure 610.

Specifically, the first source-drain doping layer located in the PMOS region 110P is a first P-type source-drain doping layer 160 (as shown in fig. 18), the second source-drain doping layer located in the PMOS region 110P is a second P-type source-drain doping layer 170 (as shown in fig. 18), and the doping ion concentration of the first P-type source-drain doping layer 160 is greater than the doping ion concentration of the second P-type source-drain doping layer 170.

In this embodiment, the first P-type source/drain doping layer 160 includes a first P-type epitaxial layer (not labeled) doped with first P-type ions, the second P-type source/drain doping layer 170 includes a second P-type epitaxial layer (not labeled) doped with second P-type ions, and the doping concentration of the first P-type ions is greater than the doping concentration of the second P-type ions.

The first P-type epitaxial layer is made of SiGe, GeSn or GeSb, the second P-type epitaxial layer is made of SiGe, GeSn or GeSb, the first P-type epitaxial layer provides a pressure stress effect for the channel region of the first PMOS region 111P, and the second P-type epitaxial layer provides a pressure stress effect for the channel region of the second PMOS region 112P, so that the carrier mobility is improved.

In this embodiment, the first P-type ions and the second P-type ions are B ions. In other embodiments, the first P-type ions may also be Ga ions or In ions, and the second P-type ions may also be Ga ions or In ions.

In this embodiment, the first P-type epitaxial layer and the second P-type epitaxial layer are both made of SiGe, and therefore the first P-type source-drain doping layer 160 and the second P-type source-drain doping layer 170 are both made of SiGe doped with B ions.

It should be noted that, in the first P-type source-drain doping layer 160 and the second P-type source-drain doping layer 170, the atomic number percentage content of Ge and the doping concentration of B ions are reasonably set according to the actual process conditions, so that while the threshold voltages of the first PMOS region 111P and the second PMOS region 112P are ensured to meet the process requirements, the PMOS region 110P is ensured to share the same P-type work function layer 530, and the threshold voltages of other devices in the PMOS region 110P are also ensured to meet the process requirements.

Therefore, in the embodiment, in the P-type source/drain doping layer, the atomic number percentage content of Ge is 15% to 85%, and the doping concentration of B ions is 1.0E18atom/cm³To 5.0E22atom/cm³. Wherein, the content of Ge in atomic number percentage refers to the percentage of Ge in atomic number to the total atomic number of G and Si.

In this embodiment, the threshold voltage of the PMOS region 110P is made to meet the process requirement by adjusting the atomic number percentage content of Ge, or adjusting the doping concentration of B ions, or adjusting the atomic number percentage content of Ge and the doping concentration of B ions together.

It should be noted that the thickness of the P-type work function layer 530, the concentration of the doped ions of the first P-type source-drain doping layer 160, and the concentration of the doped ions of the second P-type source-drain doping layer 170 are matched with each other, so that the threshold voltage of each PMOS device can meet the process requirements when the process is realized.

It should be further noted that, the higher the doping concentration of the first P-type ions in the first P-type source-drain doping layer 160 is, the more obvious the pressure stress providing effect is correspondingly played; however, in the semiconductor process, the semiconductor structure further includes a metal silicide layer located on the first P-type source-drain doping layer 160, and a contact hole plug located on the metal silicide layer and electrically connected to the metal silicide layer, and the doping concentration of the first P-type ions is too high, which may cause a problem of too large contact resistance.

Therefore, in order to reduce the contact resistance while ensuring the compressive stress effect of the first P-type source-drain doped layer 160, the first P-type source-drain doped layer 160 includes: a bottom first P-type source-drain doping layer 161 (as shown in fig. 18) located in the fin 120 on both sides of the first PMOS region 111P and the first metal gate structure 610; the top first P-type source/drain doped layer 162 (as shown in fig. 18) is located on the bottom first P-type source/drain doped layer 161.

Similarly, the second P-type source-drain doped layer 170 includes: the bottom second P-type source-drain doping layer 171 is located in the fin portions 120 on two sides of the first metal gate structure 610 of the second PMOS region 112P; and the top second P-type source/drain doping layer 172 is located on the bottom second P-type source/drain doping layer 171.

In this embodiment, the second P-type ions are not doped in the second P-type source-drain doping layer 172 on the top, and the material of the second P-type source-drain doping layer 172 on the top is the same as the material of the second epitaxial layer. In other embodiments, the second P-type source/drain doping layer on the top may also be doped with the second P-type ions, and the concentration of the doped ions in the second P-type source/drain doping layer on the top is relatively low.

In this embodiment, the source-drain doping layer located in the NMOS region 110N is an N-type source-drain doping layer (not labeled), and the N-type source-drain doping layer is located in the fin portion 120 on both sides of the second metal gate structure 620.

Specifically, the first source-drain doping layer located in the NMOS region 110N is a first N-type source-drain doping layer 180 (as shown in fig. 24), the second source-drain doping layer located in the NMOS region 110N is a second N-type source-drain doping layer 190 (as shown in fig. 24), and the doping ion concentration of the first N-type source-drain doping layer 180 is greater than the doping ion concentration of the second N-type source-drain doping layer 190.

In this embodiment, the first N-type source/drain doping layer 180 includes a first N-type epitaxial layer (not labeled) doped with first N-type ions, the second N-type source/drain doping layer 190 includes a second N-type epitaxial layer (not labeled) doped with second N-type ions, and the doping concentration of the first N-type ions is greater than the doping concentration of the second N-type ions.

The first N-type epitaxial layer is made of Si or SiC, the second N-type epitaxial layer is made of Si or SiC, the first N-type epitaxial layer provides a pressure stress effect for the channel region of the first NMOS region 111N, and the second N-type epitaxial layer provides a pressure stress effect for the channel region of the second NMOS region 112N, so that the carrier mobility is improved.

In this embodiment, the first N-type ion and the second N-type ion are both P-type ions. In other embodiments, the first N-type ions may also be Ga ions or In ions, and the second N-type ions may also be Ga ions or In ions.

In this embodiment, the first N-type epitaxial layer and the second N-type epitaxial layer are both made of Si, and therefore the first N-type source/drain doping layer 180 and the second N-type source/drain doping layer 190 are both made of Si doped with P ions.

It should be noted that, in the first N-type source/drain doping layer 180 and the second N-type source/drain doping layer 190, the doping concentration of P ions is reasonably set, so that while it is ensured that the threshold voltages of the first NMOS region 111N and the second NMOS region 112N can meet the process requirement, it is ensured that the NMOS region 110N can share the same N-type work function layer 540, and the threshold voltages of other devices in the NMOS region 110N can also meet the process requirement.

Therefore, in the embodiment, the doping concentration of P ions in the N-type source/drain doping layer is 1.0E18atom/cm³To 5.0E22atom/cm³. By adjusting the doping concentration of the P ions, the threshold voltage of the NMOS region 110N can meet the process requirements.

It should be noted that, according to the actual process conditions, the thickness of the N-type work function layer 540, the concentration of the doped ions of the first N-type source/drain doping layer 180, and the concentration of the doped ions of the second N-type source/drain doping layer 190 are matched with each other, so that the threshold voltage of each NMOS device can meet the process requirements when the process can be realized.

In addition, the semiconductor structure further includes: and spacers 140 (shown in fig. 28) located on the sidewalls of the first metal gate structure 610 and the second metal gate structure 620.

The side wall 140 is used to define the formation positions of the first P-type source-drain doping layer 160, the second P-type source-drain doping layer 170, the first N-type source-drain doping layer 180, and the second N-type source-drain doping layer 190.

It should be further noted that the semiconductor structure further includes: and the interlayer dielectric layer 102 is positioned on the substrate 110 where the first metal gate structure 610 and the second metal gate structure 620 are exposed, and the interlayer dielectric layer 102 exposes the tops of the first metal gate structure 610 and the second metal gate structure 620.

The interlayer dielectric layer 102 is used for realizing electrical isolation between adjacent devices, and the interlayer dielectric layer 102 is further used for defining the sizes and positions of the first metal gate structure 610 and the second metal gate structure 620.

In this embodiment, the top of the interlayer dielectric layer 102 is flush with the top of the first metal gate structure 610 and the second metal gate structure 620. Correspondingly, the gate electrode layer 550 is located in the interlayer dielectric layer 102, the high-k gate dielectric layer 510 is located between the interlayer dielectric layer 102 and the gate electrode layer 550, and the substrate 100 and the gate electrode layer 550.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a device area, wherein the type of the device area comprises one or two of an NMOS area and a PMOS area, and the device areas of the same type are used for forming devices with different threshold voltages;

forming a grid structure on the substrate, wherein the grid structure is a pseudo grid structure;

forming source and drain doped layers in the substrate on two sides of the grid structure, wherein the doped ion concentrations of the source and drain doped layers corresponding to different threshold voltages are different in the same type of device region;

forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer covers the source-drain doping layer and is exposed out of the top of the pseudo gate structure;

removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer;

forming a high-k gate dielectric layer on the bottom and the side wall of the gate opening;

forming a work function layer on the high-k gate dielectric layer, wherein the same type of device regions share the same work function layer;

and forming a gate electrode layer in the gate opening formed with the work function layer, wherein the high-k gate dielectric layer, the work function layer and the gate electrode layer are used for forming a metal gate structure.

2. The method of claim 1, wherein the device region comprises a PMOS region, the work function layer of the PMOS region is a P-type work function layer, and the P-type work function layer has a thickness of

To

The device region comprises an NMOS region, the work function layer of the NMOS region is an N-type work function layer, and the thickness of the N-type work function layer is

To

3. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the device regions of the same type include a first device region and a second device region, a device threshold voltage of the first device region being less than a device threshold voltage of the second device region;

in the step of forming source-drain doping layers in the substrate on two sides of the gate structure, the source-drain doping layer formed in the first device region is a first source-drain doping layer, the source-drain doping layer formed in the second device region is a second source-drain doping layer, and the doping ion concentration of the first source-drain doping layer is greater than that of the second source-drain doping layer.

4. The method for forming the semiconductor structure according to claim 3, wherein the step of forming the first source-drain doping layer comprises: forming first grooves in the substrate on two sides of the grid structure of the first device area; forming a first epitaxial layer in the first groove through a first epitaxial process, and carrying out in-situ self-doping in the process of forming the first epitaxial layer;

the step of forming the second source-drain doping layer includes: forming second grooves in the substrate on two sides of the grid structure of the second device area; and forming a second epitaxial layer in the second groove by a second epitaxial process, and carrying out in-situ self-doping in the process of forming the second epitaxial layer.

5. The method for forming the semiconductor structure according to claim 4, wherein the device region includes a PMOS region, the source-drain doped layers formed in the PMOS region are P-type source-drain doped layers, the P-type source-drain doped layers are made of SiGe doped with B ions, and parameters of any one of the first epitaxial process and the second epitaxial process include: the carrier gas is H₂The etching gas is HCl, and the silicon source gas comprises SiH₄、SiH₂Cl₂、SiH₃Cl and SiHCl₃The germanium source gas comprises GeH₄、GeH₃Cl、GeH₂Cl₂And GeHCl₃Wherein the boron source gas comprises BH₃、BH₂Cl and BHCl₃One or more of;

alternatively, the first and second electrodes may be,

the device region comprises an NMOS region, a source-drain doping layer formed in the NMOS region is an N-type source-drain doping layer, the N-type source-drain doping layer is made of Si doped with P ions, and parameters of any one of the first epitaxy process and the second epitaxy process comprise: the carrier gas is H₂The etching gas is HCl, and the silicon source gas comprises SiH₄、SiH₂Cl₂、SiH₃Cl and SiHCl₃Including a phosphorus source gas including PH₃、PH₂Cl and PHCl₂One or more of (a).

6. The method for forming the semiconductor structure according to claim 4, wherein the step of forming the first source-drain doping layer and the second source-drain doping layer comprises: forming a first mask layer on the substrate;

etching the first mask layer on the substrate positioned on two sides of the grid structure of the first device area to expose the substrate on two sides of the grid structure of the first device area, etching the exposed substrate with partial thickness, and forming the first groove in the etched substrate;

forming a first source drain doping layer in the first groove;

after the first source-drain doping layer is formed, removing the first mask layer;

after the first mask layer is removed, forming a second mask layer on the substrate, wherein the second mask layer also covers the first source-drain doping layer;

etching the second mask layer on the substrate positioned on two sides of the grid structure of the second device area to expose the substrate on two sides of the grid structure of the second device area, etching the exposed substrate with partial thickness, and forming a second groove in the etched substrate;

and forming a second source-drain doping layer in the second groove.

7. The method for forming the semiconductor structure according to claim 3, wherein the step of forming the first source-drain doping layer and the second source-drain doping layer comprises: forming grooves in the substrate on two sides of the grid structures of the first device area and the second device area; forming an epitaxial layer in the groove; and after the epitaxial layer is formed, carrying out first doping treatment on the epitaxial layer of the first device region to form a first source drain doping layer, and carrying out second doping treatment on the epitaxial layer of the second device region to form a second source drain doping layer.

8. The method for forming the semiconductor structure according to claim 1, wherein the source-drain doping layer formed in the PMOS region is a P-type source-drain doping layer, the P-type source-drain doping layer is made of SiGe doped with B ions, the content of Ge in atomic number percentage is 15% to 85%, and the doping concentration of B ions is 1.0E18atom/cm³To 5.0E22atom/cm³；

The source drain doping layer formed in the NMOS region is an N-type source drain doping layer, the N-type source drain doping layer is made of Si doped with P ions, and the doping concentration of the P ions is 1.0E18atom/cm³To 5.0E22atom/cm³。

9. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a base, the base is a substrate; alternatively, the base includes a substrate and a plurality of discrete fin portions on the substrate.

10. The method of forming a semiconductor structure of claim 3, wherein in the step of providing a substrate, the types of the device regions include an NMOS region and a PMOS region, a first device region of the NMOS region is a first NMOS region, a second device region of the NMOS region is a second NMOS region, a first device region of the PMOS region is a first PMOS region, and a second device region of the PMOS region is a second PMOS region;

the first PMOS region is a P-type low threshold voltage region, and the second PMOS region is a P-type standard threshold voltage region;

the first NMOS region is an N-type low threshold voltage region, and the second NMOS region is an N-type standard threshold voltage region.

11. A semiconductor structure, comprising:

the device comprises a substrate and a plurality of semiconductor chips, wherein the substrate comprises a device area, the type of the device area comprises one or two of an NMOS area and a PMOS area, and devices with different threshold voltages are respectively formed on the device areas with the same type;

the metal gate structure is positioned on the substrate and comprises a high-k gate dielectric layer positioned on the substrate, a work function layer positioned on the high-k gate dielectric layer and a gate electrode layer positioned on the work function layer, and device regions of the same type share the same work function layer;

and the source and drain doping layers are positioned in the substrates at two sides of the metal gate structure, and the doped ion concentrations of the source and drain doping layers corresponding to different threshold voltages are different in the same type of device region.

12. The semiconductor structure of claim 11, wherein the device region comprises a PMOS region, the work function layer of the PMOS region being a P-type work function layer, the P-type work function layer having a thickness of

To

To

13. The semiconductor structure of claim 11, in which the device regions of the same type comprise a first device region and a second device region, a device threshold voltage of the first device region being less than a device threshold voltage of the second device region;

the source-drain doping layer located in the first device area is a first source-drain doping layer, the source-drain doping layer located in the second device area is a second source-drain doping layer, and the doping ion concentration of the first source-drain doping layer is larger than that of the second source-drain doping layer.

14. The semiconductor structure of claim 11, wherein the source and drain doped layers in the PMOS region are P-type source and drain doped layers, the P-type source and drain doped layers are made of SiGe doped with B ions, the content of Ge in atomic number percentage is 15% to 85%, and the doping concentration of B ions is 1.0E18atom/cm³To 5.0E22atom/cm³；

The source-drain doping layer positioned in the NMOS region is an N-type source-drain doping layer, the material of the N-type source-drain doping layer is Si doped with P ions, and the doping concentration of the P ions is 1.0E18atom/cm³To 5.0E22atom/cm³。

15. The semiconductor structure of claim 11, wherein the base is a substrate; alternatively, the first and second electrodes may be,

the base includes a substrate and a plurality of discrete fin portions on the substrate.

16. The semiconductor structure of claim 13, wherein the types of device regions comprise an NMOS region and a PMOS region, a first one of the NMOS regions being a first NMOS region, a second one of the NMOS regions being a second NMOS region, a first one of the PMOS regions being a first PMOS region, a second one of the PMOS regions being a second PMOS region;