CN108447823A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN108447823A CN108447823A CN201710084425.9A CN201710084425A CN108447823A CN 108447823 A CN108447823 A CN 108447823A CN 201710084425 A CN201710084425 A CN 201710084425A CN 108447823 A CN108447823 A CN 108447823A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 152
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 170
- 239000002184 metal Substances 0.000 claims abstract description 170
- 238000000576 coating method Methods 0.000 claims abstract description 157
- 239000011248 coating agent Substances 0.000 claims abstract description 154
- 239000012535 impurity Substances 0.000 claims abstract description 137
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 99
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 94
- 238000000034 method Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000009833 condensation Methods 0.000 claims abstract description 25
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- 238000000137 annealing Methods 0.000 claims description 23
- 238000011065 in-situ storage Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
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- 125000006850 spacer group Chemical group 0.000 description 34
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
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- 239000011521 glass Substances 0.000 description 8
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 7
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000012159 carrier gas Substances 0.000 description 6
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 229910052787 antimony Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
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- 229910000077 silane Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- -1 phosphorus Alkane Chemical class 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
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- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
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- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910000078 germane Inorganic materials 0.000 description 3
- 229910052986 germanium hydride Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
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- XYFCBTPGUUZFHI-UHFFFAOYSA-N phosphine group Chemical group P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
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- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
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- 150000002367 halogens Chemical class 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
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- PMTRSEDNJGMXLN-UHFFFAOYSA-N titanium zirconium Chemical compound [Ti].[Zr] PMTRSEDNJGMXLN-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of semiconductor devices of present invention offer and its manufacturing method and electronic device, the method includes：Semiconductor substrate is provided, active area and drain region is arranged in semiconductor substrate MOS device area in the semiconductor substrate in MOS device area；It is respectively formed on extension coating on the surface in source region and drain region, doped with impurity in extension coating；In the forming metal layer on surface of extension coating；It reacts at least partly extension coating to form metal silicide with metal layer, wherein the interface between the semi-conducting material that impurity fractional condensation is contacted to metal silicide and metal silicide.The method of the present invention, impurity is segregated to the interface between metal silicide and the semi-conducting material of Metal-silicides Contact, it captures the impurity being entrained in source region and drain region in interface, it forms dopant and detaches Schottky, schottky barrier height is reduced, has been also prevented from the impurity that is captured in extension coating to external diffusion.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technology
As semiconductor devices integrated level constantly increases, the relevant critical dimension of semiconductor devices constantly reduces, accordingly
There are many problems, if the sheet resistance and contact resistance of device source-drain area accordingly increase, the response speed of device is caused to drop
Low, signal postpones.Therefore, the interconnection structure of low-resistivity is critical to as manufacture highly intergrated semiconductor device one
Element.
In order to reduce the contact resistance of device source/drain regions, the process of metal silicide, usual metal silication are introduced
Object is formed on the surface of device source-drain area, and the metal silicide has lower resistivity, can be substantially reduced source/drain region
Contact resistance.Metal silicide and self-aligned metal silicate and formation process be widely used for reduce device source electrode and
The sheet resistance and contact resistance of drain electrode, to reduce the RC delays time.
For smaller nanotechnology process node, such as 7nm and its following nanotechnology process node, PMOS device can be with
Using Ge raceway grooves, and NMOS device can use Group III-V compound semiconductor (such as InGaAs) to be used as raceway groove, be carried with improving
Flow transport factor.And for the device of above-mentioned channel material, how in the surface of source-drain area formation metal silicide and metal
How application etc. is the main problem faced at present for silicide and contact process.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, one aspect of the present invention provides a kind of manufacturing method of semiconductor devices, the method
Including：
Semiconductor substrate is provided, the semiconductor substrate includes MOS device area, and described in the MOS device area is partly led
Active area and drain region are set in body substrate；
It is respectively formed on extension coating on the surface in the source region and the drain region, wherein in the extension coating
Doped with impurity；
In the forming metal layer on surface of the extension coating；
It reacts at least partly described extension coating to form metal silicide with the metal layer, wherein the doping
Interface between the semi-conducting material that impurity segregation is contacted to the metal silicide and the metal silicide.
Further, the MOS device area includes at least one of PMOS device area, NMOS device area；
The intratectal impurity of extension in the PMOS device area includes Sb and/or N；
The intratectal impurity of extension in the NMOS device area includes Ga and/or C.
Further, the extension coating of whole thickness is reacted with the metal layer and is formed as the metal silication
Object, the impurity fractional condensation is between the metal silicide and the source region and the metal silicide and the drain region
Interface；Alternatively,
The surface portion of the extension coating is reacted with the metal layer is formed as the metal silicide, the doping
Impurity segregation is to the interface between the metal silicide and the extension coating.
Further, further comprising the steps of before forming the extension coating：In the source region and the drain region
Stressor layers are formed, the extension coating is formed on the surface of the stressor layers.
Further, the method for forming the stressor layers includes：
Semiconductor substrate described in etching part, to form groove in the source region and the drain region；
The stressor layers adulterated in situ are epitaxially-formed in the groove.
Further, the MOS device area includes PMOS device area and NMOS device area, is forming the PMOS device area
Before extension coating, alternatively, after the extension coating for forming the PMOS device area, forming the PMOS device area
Before metal layer, the extension coating is formed in the source region in the NMOS device area and the surface in the drain region.
Further, the extension coating is made to react to form the metal silication with the metal layer by annealing
Object.
Another aspect of the present invention provides a kind of semiconductor devices, including：
Semiconductor substrate, the semiconductor substrate include MOS device area, in the semiconductor substrate in the MOS device area
Active area and drain region are set；
It is respectively formed on extension coating on the surface in the source region and the drain region, wherein in the extension coating
In doped with impurity；
It is formed with metal silicide on the surface of the extension coating, wherein the impurity fractional condensation to the gold
Belong to the interface between the semi-conducting material that silicide and the metal silicide are contacted.
Further, the MOS device area includes at least one of PMOS device area, NMOS device area；
The intratectal impurity of extension in the PMOS device area includes Sb and/or N；
The intratectal impurity of extension in the NMOS device area includes Ga and/or C.
Further, impurity fractional condensation to the metal silicide and the source region and the metal silicide and
Interface between the drain region；Alternatively,
The impurity is segregated to the interface between the metal silicide and the extension coating.
Further, stressor layers are formed in the source region and the drain region, the extension coating is formed in described answer
On the surface of power layer.
Further aspect of the present invention provides a kind of electronic device, and the electronic device includes semiconductor devices above-mentioned.
The manufacturing method of the present invention is respectively formed on outer in the source region of the semiconductor substrate in MOS device area and the surface in drain region
Prolong coating, wherein doped with impurity in the extension coating, metal is formed on the surface of the extension coating
Layer；At least partly described extension coating reacts to form metal silicide with the metal layer, wherein the impurity fractional condensation
Interface between the semi-conducting material contacted to the metal silicide and the metal silicide, and caught in interface
The impurity (such as n-type doping impurity or p-type impurity) in the source region and the drain region is caught, and then forms doping
Agent detaches Schottky (Dopant segregated Schottky, abbreviation DSS), to reduce schottky barrier height
(SBH), the contact resistance (Rc) of regions and source/drain is reduced so that the ectoparasitism resistance of transistor also accordingly reduces,
The impurity adulterated in the extension coating can also prevent to catch from the source region and the drain region in extension coating
The impurity of acquisition is caught to external diffusion, therefore, method of the invention can improve the performance of device.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A to Fig. 1 G shows the correlation step institute of the manufacturing method of the semiconductor devices of one embodiment of the present invention
The diagrammatic cross-section of the device of acquisition；
Fig. 2 shows the process flow charts of the manufacturing method of the semiconductor devices of one embodiment of the present invention；
Fig. 3 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, it is proposed by the present invention to illustrate
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have
There is other embodiment.
Embodiment one
In order to solve aforementioned technical problem, the present invention provides a kind of manufacturing method of semiconductor devices, as described in Figure 2,
It mainly includes the following steps that：
Step S1 provides semiconductor substrate, and the semiconductor substrate includes MOS device area, the institute in the MOS device area
It states and active area and drain region is set in semiconductor substrate；
Step S2 is respectively formed on extension coating, wherein cover in the extension on the surface in the source region and the drain region
Doped with impurity in cap rock；
Step S3, in the forming metal layer on surface of the extension coating；
At least partly described extension coating is reacted to form metal silicide, wherein institute by step S4 with the metal layer
State the interface between the semi-conducting material that impurity fractional condensation is contacted to the metal silicide and the metal silicide.
The manufacturing method of the present invention is respectively formed on outer in the source region of the semiconductor substrate in MOS device area and the surface in drain region
Prolong coating, wherein doped with impurity in the extension coating, metal is formed on the surface of the extension coating
Layer；At least partly described extension coating reacts to form metal silicide with the metal layer, wherein the impurity fractional condensation
Interface between the semi-conducting material contacted to the metal silicide and the metal silicide, and caught in interface
The impurity in the source region and the drain region is caught, and then forms dopant separation Schottky (Dopant segregated
Schottky, abbreviation DSS), to reduce schottky barrier height (SBH), reduce the contact resistance of regions and source/drain
(Rc) so that the ectoparasitism resistance of transistor also accordingly reduces, and the impurity adulterated in the extension coating may be used also
To prevent in extension coating to capture the impurity obtained to external diffusion, therefore, this hair from the source region and the drain region
Bright method can improve the performance of device.
In the following, being described in detail to the manufacturing method of the semiconductor devices of the present invention referring to figs. 1A to Fig. 1 G, wherein Figure 1A
The device that the correlation step of the manufacturing method of the semiconductor devices of one embodiment of the present invention is obtained is shown to Fig. 1 G
Diagrammatic cross-section.
First, step 1 is executed, provides semiconductor substrate, the semiconductor substrate includes PMOS device area, described
It is provided with first grid structure in the semiconductor substrate in PMOS device area, the PMOS described in first grid structure both sides
The first source region and the first drain region are provided in the semiconductor substrate of device region, wherein in first source region and the first drain region
Doped with p-type impurity.
Specifically, as shown in Figure 1A, semiconductor substrate 100 is body silicon substrate, can be in the following material being previously mentioned
At least one：Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compounds are partly led
Body further includes the multilayered structure etc. that these semiconductors are constituted, or for silicon is laminated on silicon-on-insulator (SOI), insulator
(SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on insulator
(GeOI) etc..
In one example, the semiconductor devices includes MOS device area, the MOS device area include PMOS device area,
At least one of NMOS device area.
In one example, the semiconductor substrate includes NMOS device area and PMOS device area, wherein in the PMOS
It is formed with first grid structure in the semiconductor substrate of device region, is formed in the semiconductor substrate in the NMOS device area
Two gate structures.
Wherein, the first grid structure and the second grid structure can be dummy gate structure, dummy gate structure packet
It includes dummy grid dielectric layer and dummy grid material layer to include the dummy gate structure being laminated from bottom to top.
Illustratively, first grid structure and second grid structure can also be metal gate structure.
Illustratively, the channel material below the first grid structure in the PMOS device area includes elemental semiconductor,
Wherein, elemental semiconductors can be any elemental semiconductor used well known to those skilled in the art, including but unlimited
Channel material below the second grid structure in Ge either Si or SiGe, the NMOS device area may include III-V
Compound semiconductor, for example, iii-v binary or ternary semiconductor, in the present embodiment, the iii-v
Conjunction object semiconductor is InGaAs, and in the present embodiment, the elemental semiconductor is Ge, using Group III-V compound semiconductor as
The raceway groove of NMOS device, and raceway groove of the elemental semiconductor as PMOS device is used, carrier mobility can be improved.
Further, the second source is set in the semiconductor substrate in NMOS device area described in second grid structure both sides
Area and the second drain region, doped with n-type doping impurity in second source region and second drain region.
Illustratively, semiconductor devices of the invention is FinFET, the semiconductor in each PMOS device area
It is formed with the first fin structure 1011 on substrate, then is formed with the second fin in the semiconductor substrate in the NMOS device area
Structure 1012, the first grid structure is across first fin structure 1011, and second grid structure is across second fin
Chip architecture 1012.
In one example, by taking FinFET as an example, in order to obtain structure as shown in Figure 1A, following step can be executed
Rapid A1 to A4：
First, step A1 is executed, multiple fin structures are formed on a semiconductor substrate, for example, in the semiconductor substrate
On the PMOS device area and the NMOS device area in be respectively formed with the first fin structure and the second fin structure, fin
The width of structure is all identical or fin is divided into multiple fin structure groups with different in width, the length of fin structure
It can differ.
Specifically, the forming method of the fin structure is not limited to a certain kind, and a kind of illustrative shape is given below
At method：Hard mask layer (not shown) is formed on a semiconductor substrate, forms the hard mask layer and this field may be used
The various suitable techniques that technical staff is familiar with, such as chemical vapor deposition method, the hard mask layer can be from lower and
The oxide skin(coating) and silicon nitride layer of upper stacking；The hard mask layer is patterned, is formed for etching semiconductor substrate on it
The multiple masks being isolated from each other for forming fin, in one embodiment, using self-aligned double patterning case (SADP) process implementing institute
State patterning process；Semiconductor substrate is etched to be formed on fin structure.
Then, step A2, depositing isolation material layer, to cover all fin structures above-mentioned be can also carry out.
Specifically, depositing isolation material layer, to be filled up completely the gap between fin structure.In one embodiment, it adopts
Implement the deposition with the chemical vapor deposition method with flowability.The material of spacer material layer can with selective oxidation object,
Such as high-aspect-ratio technique (HARP) oxide, it is specifically as follows silica.
Then spacer material layer described in etch-back, until the object height of the fin structure, to form isolation structure 102,
The top surface of the isolation structure 102 is less than the top surface of the first fin structure and second fin structure.Specifically, etch-back institute
Spacer material layer is stated, with fin structure described in exposed portion, and then forms the fin structure with certain height.
Then, step A3 is executed, is developed across the first dummy gate structure 104p of first fin structure and across the
Second dummy gate structure 104n of two fin structures, wherein dummy gate structure include that the dummy grid stacked gradually from bottom to top is situated between
Electric layer 1041 and dummy grid material layer 1042.
It should be pointed out that the term " across " used in the present invention, such as across fin structure (such as the first fin
Structure, second fin structure etc.) dummy gate structure (or gate structure), refer to the part of fin structure upper surface and
Side is each formed with dummy gate structure, and the dummy gate structure is also formed on the part surface of semiconductor substrate.
In one example, it first can be sequentially depositing to form dummy grid dielectric layer 1041 and dummy grid material on a semiconductor substrate
The bed of material 1042.
Wherein, the dummy grid dielectric layer can select common oxide, such as SiO2, the dummy grid material layer can
To select semi-conducting material commonly used in the art, such as polysilicon can be selected etc., it is not limited to it is a certain, it is not another herein
One enumerate,
The deposition method of the dummy grid material layer 1042 can select the side such as chemical vapor deposition or atomic layer deposition
Method.
Then the dummy grid dielectric layer and dummy grid material layer are patterned, to form first dummy gate structure and
Two dummy gate structures.Specifically, the hard mask layer 105 in the dummy grid material layer, light is formed on the hard mask layer 105
Photoresist layer, then exposure imaging, has the first dummy gate structure and the patterned patterning of the second dummy gate structure to form definition
Photoresist layer, then etch the hard mask layer 105,1042 and of dummy grid material layer successively using the photoresist layer as mask
Dummy grid dielectric layer 1041 finally removes photoresist layer to form first dummy gate structure and the second dummy gate structure.
Wherein, hard mask layer 105 remains in the dummy grid material layer 1042.
Later, also optionally, it is formed on the side wall of first dummy gate structure and the second dummy gate structure inclined
Move side wall (not shown).
Specifically, the offset side wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
At.As embodiment in the one of the present embodiment, the offset side wall is that silica, silicon nitride collectively constitute, and concrete technology is：
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on a semiconductor substrate, then use engraving method
Form offset side wall.It can also be respectively formed on spacer material layer in the top surface of dummy gate structure and side wall, in the steps afterwards
By the method for planarization, such as chemical mechanical grinding, the spacer material layer on top surface is removed, formation is located only on side wall
Offset side wall.
Optionally, LDD ion implanting steps are executed respectively to the first dummy gate structure and the second dummy gate structure both sides
And anneal activation.
LDD ion implantings can reduce electric field to form lightly doped drain (LDD) structure in source/drain region, and can significantly change
Into thermoelectronic effect.
LDD ion implantings are carried out to the first fin structure of the first dummy gate structure both sides in the areas PMOS, to form p-type
Lightly doped drain (LDD), injection ion can be arbitrary p-type Doped ions, including but not limited to boron (B) ion, indium (In)
Ion.
To the second fin structure of the second dummy gate structure both sides in NMOS area carry out LDD ion implantings carry out LDD from
Son injection, to form N-type lightly doped drain (LDD), injection ion can be any suitable n-type doping ion, including but not
It is limited to phosphorus (P) ion, arsenic (As) ion.
Then, step A4 is executed, the first stressor layers, the p-type are formed in first source region and first drain region
Impurity is entrained in first stressor layers.
In one example, the method for forming first stressor layers includes the following steps：
As shown in Figure 1A, first, formed the first spacer material layer 106p, with cover the semiconductor substrate 100 and
The first grid structure.
Specifically, the first spacer material floor 106p covers the semiconductor in the PMOS device area and NMOS device area
The surface of substrate 100 and the first dummy gate structure 104p and the second dummy gate structure 104n.
First spacer material layer 106p can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
At.As embodiment in the one of the present embodiment, the first spacer material layer 106 is that silica, silicon nitride collectively constitute.
Then, etching removal part the first spacer material layer 106p, to expose first source region and described the
The surface in one drain region, and form the first clearance wall 1061 on the side wall of the first dummy gate structure 104p.
Specifically, the first spacer material layer 106p etchings on the top surface of the first dummy gate structure 104p can be gone
It removes, and can retain the first clearance wall on the first fin structure and the second fin structure on the outside of the first dummy gate structure 104p
Material layer 106p, protective layer when using as the first stressor layers of subsequently epitaxial growing.
Illustratively, it can be achieved that by photoetching process, patterned photoresist layer is formed, described in photoresist layer covering
NMOS device area, and expose the first spacer material floor in the first source region and the first drain region surface in the PMOS device area
And first the first spacer material layer on dummy gate structure surface, it can also expose first be formed on isolation structure 102
Spacer material layer 106p, later again using the patterned photoresist layer as mask, the first gap wall material of etching removal exposing
The bed of material, to expose the surface of first source region and first drain region, and in the side wall of the first dummy gate structure 104p
The first clearance wall of upper formation.
The method of etching can use any suitable dry etching or wet etching well known to those skilled in the art
The methods of.
After the completion of etching, the photoresist layer can be removed for example, by the method for ashing.
Then, the etching removal part semiconductor substrate, to be formed in first source region and first drain region
First groove, then the first stressor layers 1031 are formed in first groove.
In one example, part first fin structure for etching the both sides the first dummy gate structure 104p, with
The first groove is formed in the predetermined region for forming the first source region and the first drain region；Selective epitaxial is given birth in first groove again
Long first stressor layers 1031.It is further preferred that the first groove can also be " ∑ " connected in star.
Illustratively, the p-type impurity is epitaxially-formed in first groove using epitaxial growth technology
First stressor layers adulterated in situ, the hard mask due to the first spacer material layer 106p and in dummy grid material layer
The protective effect of layer 105, therefore, the first stressor layers 1031 are only selectively grown in the lining of the semiconductor in the first groove of exposing
The surface at bottom, also, since the first spacer material floor 104n completely covers NMOS device area, so will not be in NMOS device
First stressor layers 1031 are grown on the semi-conducting material in area.
It is heavy that low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor may be used in selective epitaxial growth
Product (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy
(MBE) one kind in.
The material of first stressor layers 1031 may include SiGe or other can provide the suitable material of compression.Specifically
Ground can be used chemical vapor deposition method or gas source molecular beam epitaxy method and grow the SiGe adulterated in situ, with silane or
A certain amount of germane is added as silicon source in person's disilane.For example, selecting GeH4And SiH2Cl2As reaction gas, and select
Select H2As carrier gas, the wherein flow-rate ratio of reaction gas and carrier gas is 0.01-0.1, and the temperature of deposition is 300 DEG C -1000 DEG C, excellent
650 DEG C -750 DEG C, gas pressure 1Torr-50Torr, preferably 20Torr-40Torr are selected as, it also optionally simultaneously can
By providing such as boron, boron difluoride (BF during depositing operation2) and/or diborane (B2H6) etc. admixtures agent so that SiGe extensions
Layer includes the p-type impurity such as boron etc.
Wherein, the first stressor layers of doped p-type impurity in situ can be used for forming source/drain region in PMOS device area,
Such as the source/drain region of heavy doping.
Form the stressor layers with compression in PMOS, the performance of cmos device can by by action of compressive stress in
PMOS is improved.
Further, first stressor layers 1031 are formed in first fin structure, and first stress
The top surface of layer 1031 is higher than the top surface of first fin structure.
In one example, be not provided with the first stressor layers in first source region and the first drain region, and by source/drain from
The method of son injection carries out the first source region and the first drain region the doping of p-type impurity, wherein source drain ion injection
Method can use the common method of those skilled in the art, further, can form the first source region and the first leakage of heavy doping
Area.
So far, the structure as described in Figure 1A is obtained by above-mentioned steps.
Then, step 2 is executed, the first extension coating is respectively formed on the surface in first source region and the first drain region,
Wherein, doped with the first impurity in the first extension coating.
Specifically, as shown in Figure 1B, it is respectively formed on the covering of the first extension on the surface in first source region and the first drain region
Layer 107, wherein doped with the first impurity in the first extension coating 107.
In one example, the first stressor layers 1031 are formed in first source region and the first drain region, then described
One extension coating 107 is formed in the surface of first stressor layers 1031.
Wherein, the material of the first extension coating 107 can be any suitable siliceous semi-conducting material, including
But be not limited to SiGe, Si etc..In the present embodiment, the material of the first extension coating 107 is preferably SiGe.
Optionally, the first impurity includes Sb and/or N, in the present embodiment, preferably, the first impurity includes Sb
And N.
In one example, using epitaxial growth technology institute is epitaxially-formed on the surface of first stressor layers 1031
The first extension coating 107 that the first impurity adulterates in situ is stated, due to the protection of the first spacer material layer 106p
Effect, therefore, the first extension coating 107 is only selectively grown in 1031 surface of the first stressor layers of exposing.
It is heavy that low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor may be used in selective epitaxial growth
Product (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy
(MBE) one kind in.
In one example, the material of the first extension coating 107 may include SiGe, specifically, chemical gas can be used
The phase deposition method SiGe that either growth of gas source molecular beam epitaxy method is adulterated in situ uses silane or disilane as silicon
Source, while a certain amount of germane is added.For example, selecting GeH4And SiH2Cl2As reaction gas, and select H2As carrier gas,
Middle reaction gas and the flow-rate ratio of carrier gas are 0.01-0.1, and the temperature of deposition is 300 DEG C -1000 DEG C, preferably 650 DEG C -750
DEG C, gas pressure 1Torr-50Torr, preferably 20Torr-40Torr also optionally simultaneously can be in the depositing operation phases
Between by provide such as Sb and N admixtures agent so that SiGe epitaxial layers include the first impurity such as Sb and/or N etc.
Optionally, the thickness of the first extension coating 107 can be reasonably selected according to actual process, for example,
The thickness range of first extension coating 107 can be 5 angstroms~20 angstroms or other suitable thickness.
Then, step 3 is executed, the second stressor layers, the N-type are formed in second source region and second drain region
Impurity is entrained in second stressor layers.
In one example, the method for forming second stressor layers 1032 includes the following steps：
First, as shown in Figure 1 C, the second spacer material layer 106n is formed, to cover the PMOS device area and described
The semiconductor substrate 100 in NMOS device area, the first grid structure and the second grid structure.
Illustratively, in the isolation structure 102, the first spacer material layer, first clearance wall 1061, institute
State the first fin structure, second fin structure, the first extension coating 107, the first dummy gate structure 104p
The second clearance material layer 106n is formed on the surface exposed with the second dummy gate structure 104n.
Second spacer material layer 106n can be silica, silicon nitride, one kind in silicon oxynitride or their combinations
It constitutes.As embodiment in the one of the present embodiment, the second spacer material layer 106n is that silica, silicon nitride collectively constitute.
It can be formed using any suitable deposition method, including but not limited to chemical vapor deposition, physical vapour deposition (PVD) or atom
The methods of layer deposition.
Then, continue as shown in Figure 1 C, etching removal part the second spacer material layer, to expose second source
The surface in area and second drain region, and the second clearance wall 1062 is formed on the side wall of the second grid structure.
Illustratively, it can be achieved that by photoetching process, patterned photoresist layer is formed, described in photoresist layer covering
PMOS device area, and expose the second spacer material floor in the second source region and the second drain region surface in the NMOS device area
And second the second spacer material layer on the surfaces dummy gate structure 104n, it can also expose NMOS device area inside points and be formed in
The second spacer material layer 106n on isolation structure 102, later again using the patterned photoresist layer as mask, etching removal
The the second spacer material layer and the first spacer material layer below exposed, to expose first source region and described the
The surface in one drain region, and form the second clearance wall 1062 on the side wall of the second dummy gate structure 104n.
Wherein, the second spacer material floor 106n is located at the part in PMOS device area and is retained, for use as protective layer.
The method of etching can use any suitable dry etching or wet etching well known to those skilled in the art
The methods of.
After the completion of etching, the photoresist layer can be removed for example, by the method for ashing.
Then, the etching removal part semiconductor substrate, to be formed in second source region and second drain region
Second groove, then the second stressor layers 1032 are formed in second groove.
In one example, part second fin structure for etching the both sides the second dummy gate structure 104n, with
The second groove is formed in the predetermined region for forming the second source region and the second drain region；Selective epitaxial is given birth in second groove again
Long second stressor layers 1032.
Illustratively, the n-type doping impurity is epitaxially-formed in second groove using epitaxial growth technology
Second stressor layers adulterated in situ, the hard mask due to the second spacer material layer 106n and in dummy grid material layer
The protective effect of layer 105, therefore, the second stressor layers 1032 are only selectively grown in the lining of the semiconductor in the second groove of exposing
The surface at bottom, also, since the second spacer material layer 106n covers the first extension coating 107 and entire PMOS
Device region, therefore do not have the second stressor layers and be grown in PMOS device area.
It is heavy that low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor may be used in selective epitaxial growth
Product (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy
(MBE) one kind in.
In NMOS device area, the second stressor layers 1032 usually have tensile stress.The material of second stressor layers 1032 can be with
For SiP, SiC or other the suitable material of tensile stress can be provided.In the present embodiment, preferably select SiP as the second stress
Layer 1032.
Further, chemical vapor deposition method or gas source molecular beam epitaxy method growth SiP can be used, use silane
Or disilane, as silicon source, phosphine forms the Si epitaxial layers that phosphorus adulterates in situ as phosphorus source.
Further, second stressor layers 1032 are formed in second fin structure, and second stress
The top surface of layer 1032 is higher than the top surface of second fin structure.
Wherein, the first stressor layers of in-situ doped N-type impurity can be used for forming source/drain region in NMOS device area,
Such as the source/drain region of heavy doping.
In one example, be not provided with the second stressor layers in second source region and the second drain region, and by source/drain from
The method of son injection carries out the second source region and the second drain region the doping of n-type doping impurity, wherein source drain ion injection
Method can use the common method of those skilled in the art, further, can form the second source region and the second leakage of heavy doping
Area.
Then, step 4 is executed, forms the covering of the second extension on the surface in second source region and second drain region
Layer, wherein doped with the second impurity in the second extension coating.
Illustratively, as shown in figure iD, the second extension is formed on the surface in second source region and second drain region
Coating 108, wherein doped with the second impurity in the second extension coating 108.
In one example, the second stressor layers 1032 are formed in second source region and the second drain region, then described
Two extension coatings 108 are formed on the surface of second stressor layers 1032.
Wherein, the material of the second extension coating 108 can be any suitable siliceous semi-conducting material, including
But be not limited to SiGe, Si etc..In the present embodiment, the material of the second extension coating 108 is preferably SiGe.
Optionally, the second impurity includes Ga and/or C, in the present embodiment, preferably, the second impurity includes Ga
And C.
In one example, using epitaxial growth technology institute is epitaxially-formed on the surface of second stressor layers 1032
The second extension coating 108 that the second impurity adulterates in situ is stated, due to the second spacer material layer 106n and firmly
The protective effect of mask layer 105, therefore, the second extension coating 108 are only selectively grown in the second stressor layers of exposing
1032 surfaces.
It is heavy that low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor may be used in selective epitaxial growth
Product (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy
(MBE) one kind in.
In one example, the material of the second extension coating 108 may include SiGe, specifically, chemical gas can be used
The phase deposition method SiGe that either growth of gas source molecular beam epitaxy method is adulterated in situ uses silane or disilane as silicon
Source, while a certain amount of germane is added.For example, selecting GeH4And SiH2Cl2As reaction gas, and select H2As carrier gas,
Middle reaction gas and the flow-rate ratio of carrier gas are 0.01-0.1, and the temperature of deposition is 300 DEG C -1000 DEG C, preferably 650 DEG C -750
DEG C, gas pressure 1Torr-50Torr, preferably 20Torr-40Torr, also optionally while during depositing operation
By providing such as Ga and C admixtures agent so that SiGe epitaxial layers include the second impurity such as Ga and/or C etc.
Optionally, the thickness of the second extension coating 108 can be reasonably selected according to actual process, for example,
The thickness range of second extension coating 108 can be 5 angstroms~20 angstroms or other suitable thickness.
It is noted that be initially formed in the present embodiment first stressor layers in PMOS device area, the first extension coating with
And first impurity doping, then carry out second stressor layers in NMOS device area, the second extension coating and
The doping of two impurities and etc., and the present invention is applied equally to for the reasonable exchange of other sequence of steps, for example, first
Second stressor layers in NMOS device area, the doping of the second extension coating and the second impurity are carried out, is re-formed
The doping of first stressor layers in PMOS device area, the first extension coating and the first impurity.
Then, step 5 is executed, forms the first interlayer dielectric layer, first interlayer dielectric on the semiconductor substrate
The top surface of layer is flushed with the top surface of the first grid structure and the second grid structure.
Illustratively, as referring to figure 1E, the first grid structure is the first dummy gate structure 104p, the second grid
Structure is the second dummy gate structure 104n, deposits the first interlayer dielectric layer 1091, to cover the surface of entire semiconductor substrate, then
The step of executing planarization, stops on the top surface of the first dummy gate structure 104p and the second dummy gate structure 104n, by flat
Smoothization can remove the hard mask layer on the top surface of the first dummy gate structure 104p and the second dummy gate structure 104n.
Wherein, first interlayer dielectric layer 1091 can select dielectric material commonly used in the art, such as various oxygen
Compound etc., in this embodiment interlayer dielectric layer can select SiO2, thickness is not limited to a certain numerical value.
The non-limiting examples of the planarization process include mechanical planarization method and chemically mechanical polishing planarization side
Method.
Then, step 6 is executed, first dummy gate structure and second dummy gate structure are removed, to form first
Gate trench and second grid groove.
The first dummy gate structure and the second dummy gate structure are removed, including removes dummy grid dielectric layer and dummy grid material successively
The bed of material, to form first grid groove, the semiconductor substrate in NMOS device area in the semiconductor substrate 100 in PMOS device area
Second grid groove is formed on 100, the gate trench in the PMOS device area is on the extending direction of first fin structure
The gate trench of first fin structure described in exposed portion, NMOS device area reveals on the extending direction of second fin structure
Go out part second fin structure.
The method for removing first dummy gate structure and second dummy gate structure can be any suitable dry method
The method of etching or wet etching.
Then, step 7 is executed, forms the first metal gate structure in the first grid groove, and described second
The second metal gate structure is formed in gate trench.
Illustratively, as referring to figure 1E, the first metal gate structure 1101 is formed in the first grid groove, and
The second metal gate structure 1102 is formed in the second grid groove.
Illustratively, the first metal gate structure 1101 includes the gate trench bottom being formed in the PMOS device area
Boundary layer, be sequentially formed in the bottom and side wall of gate trench and the high k dielectric layer above the boundary layer, first
Diffusion impervious layer, P-type workfunction layer, N-type workfunction layer and the second diffusion impervious layer, and the grid of the filling gate trench are electric
Pole layer.
Illustratively, the second metal gate structure 1102 includes the gate trench bottom being formed in the NMOS device area
Boundary layer, be sequentially formed in the bottom and side wall of gate trench and the high k dielectric layer above the boundary layer, first
Diffusion impervious layer, N-type workfunction layer and the second diffusion impervious layer, and fill the gate electrode layer of the gate trench.
Wherein it is possible to form the first metal gates knot using any suitable method well known to those skilled in the art
Structure and the second metal gate structure, do not do repeat one by one herein.
It is noted that the first grid structure and second grid structure of the present invention can also be other kinds of
Gate structure, such as gate structure includes the gate dielectric and grid layer stacked gradually from bottom to top, gate dielectric can be with
For dielectric materials such as silica, grid layer can be the materials such as polysilicon.
Then, step 8 is executed, in first interlayer dielectric layer and the first grid structure and the second gate
The second interlayer dielectric layer is formed on the surface of pole structure.
Specifically, as shown in fig. 1F, second interlayer dielectric layer 1092 cover first interlayer dielectric layer 1091 with
And the surface of first metal gate structure 1101 and second metal gate structure 1102, and planarize.
Second interlayer dielectric layer 1092 can be silicon oxide layer, including the use of thermal chemical vapor deposition (thermal
CVD) the material for having doped or undoped silica that manufacturing process or high-density plasma (HDP) manufacturing process are formed
Layer, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer
Can also be the spin cloth of coating-type glass (spin-on-glass, SOG) for adulterating boron or adulterating phosphorus, the tetraethoxy-silicane for adulterating phosphorus
Alkane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).
The thickness of second interlayer dielectric layer 1092 can be any suitable numerical value, be not specifically limited herein, the
The top surface of two interlayer dielectric layers 1092 is higher than the top of the first metal gate structure 1101 and second metal gate structure 1102
Face.
Then, step 9 is executed, first is formed in second interlayer dielectric layer and first interlayer dielectric layer and connects
Contact hole is open, and the first contact hole opening exposes the surface of the first extension coating, in second interlayer dielectric layer
It is open with the second contact hole is formed in first interlayer dielectric layer, the second contact hole opening is exposed second extension and covered
The surface of cap rock.
In one example, the method for forming the first contact hole opening and second contact hole opening includes following
Step：
First, as shown in fig. 1F, etching the interlayer dielectric layer, (including the second interlayer dielectric layer 1092 and the first interlayer are situated between
Electric layer 1091) it stops at respectively on the surface of the first extension coating 107 and the second extension coating 108, to form
One contact hole opening 1111 and the second contact hole opening 1112.
Further, the bottom of the first contact hole opening 1111 is located in the first extension coating 107, described
The bottom of second contact hole opening 1112 is located in the second extension coating 108.
Specifically, can patterned photoresist layer be formed on the surface of the second interlayer dielectric layer 1092 first, the photoetching
Glue-line defines the positions and dimensions etc. of the first contact hole opening and the second contact hole opening of predetermined formation, then patterned with this
Photoresist is that mask etches the second interlayer dielectric layer and the first interlayer dielectric layer successively, stops at the first extension covering respectively
On the surface of layer 107 and the second extension coating 108, it is open with forming the first contact hole opening 1111 and the second contact hole
1112。
Then, patterned photoresist layer is removed, such as the photoresist layer is removed using the method for ashing.
Then, step 10 is executed, forms third contact hole opening and the 4th contact hole in second interlayer dielectric layer
Opening, wherein the third contact hole opening exposes the top surface of the first grid structure, and the 4th contact hole opening is exposed
The top surface of the second grid structure.
Specifically, as shown in fig. 1F, third contact hole 1113 Hes of opening are formed in second interlayer dielectric layer 1092
4th contact hole opening 1114, wherein the third contact hole opening 1113 exposes first metal gate structure 1101
Top surface, the 4th contact hole opening 1114 expose the top surface of second metal gate structure 1102.
Illustratively, patterned photoresist layer is formed on the second interlayer dielectric layer 1092, the patterned photoresist
Layer defines the parameters such as position, size and the pattern of third contact hole opening and the 4th contact hole opening, then with patterned photoetching
Glue-line is mask, etches second interlayer dielectric layer 1092 and stops at the first metal gate structure 1101 and the second metal gates
On the surface of structure 1102, to form the third contact hole opening 1113 and the 4th contact hole opening 1114.
Then, the method that can use such as ashing removes the photoresist layer.
Then, step 11 is executed, prerinse step is carried out, to remove removing natural oxidizing layer.
Specifically, as shown in Figure 1 G, prerinse step is carried out, to remove the first contact hole opening, the second contact hole
The oxide layer of opening, third contact hole opening and the 4th contact hole open bottom, such as natural oxidizing layer.
The prerinse can use any suitable method well known to those skilled in the art, such as using including hydrofluoric acid
Cleaning solution etc..
Then, step 12 is executed, in the bottom and side of first contact hole opening and second contact hole opening
Metal layer is formed on wall.
Specifically, as shown in Figure 1 G, in first contact hole opening, second contact hole opening, third contact hole
Metal layer 112 is formed in the bottom and side wall of opening and the 4th contact hole opening.
Wherein, the material of metal layer can use titanium (Ti), nickeliferous (nickel), cobalt (cobalt) and platinum (platinum)
Or combinations thereof material, in the present embodiment, the material preferably with metal layer is Ti.
It can deposit to form the metal layer 112 using any suitable method well known to those skilled in the art, including
But be not limited to chemical vapor deposition method or physical gas-phase deposite method etc..
Then, step 13 is executed, forms coating (not shown) on the metal layer 112.
Wherein physical vapour deposition (PVD) (PVD) can be selected in the preparation method of coating, and coating can be between -40 DEG C~400
DEG C temperature with about formed under the pressure of 0.1 millitorr (mTorr)~100 millitorr (mTorr).Covering layer material be metal or
The material of metal compound layer for example tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or
Its constituent.In addition, coating also may include multiple film layers, in the present embodiment, the coating includes TiN layer.
Then, step 14 is executed, annealing steps are carried out.
The annealing steps can use any suitable method for annealing, such as furnace anneal, laser short annealing, pulse electricity
Beamlet short annealing, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (such as halogen lamp, electric arc
Lamp, graphite heating) short annealing.In the present embodiment, preferably, annealing uses laser annealing (laser anneal).
Wherein, the temperature range of annealing can be 800~1100 DEG C, preferably, the temperature of annealing is 900 DEG C.When annealing
Between can be any suitable time, for example, annealing time may range from the 400 μ s of μ s~800, the annealing time namely use
Residence time (Dwell time) when laser annealing.
In the annealing process of this step, make the first contact hole open bottom the metal layer and be in contact with it first
The reaction of extension coating 107 generates the first metal silicide (for example, TiSi), makes the metal of the second contact hole open bottom
The second extension coating 108 reaction that layer is in contact with it generates the second metal silicide (for example, TiSi).
In one example, the first metal silicide surrounds the bottom of the first contact hole opening, and the first metal
The bottom of silicide is located at the surface in the first extension coating 107 and higher than the semiconductor substrate.
In one example, the first metal silicide surrounds the bottom of the second contact hole opening, and the first metal
The bottom of silicide is located at the surface in the second extension coating 108 and higher than the semiconductor substrate.
The annealing steps also make first impurity (Sb and N) fractional condensation to first metal silicide and its simultaneously
Interface between the semi-conducting material contacted, and the p-type impurity is captured (for example, the p-type is adulterated in interface
Impurity is the p-type impurity adulterated in situ in the first stressor layers), and then form dopant separation Schottky (Dopant
Segregated Schottky, abbreviation DSS), p-type impurity is eventually located at interface metal silicide side, to reduce
Schottky barrier height (SBH), reduces the contact resistance (Rc) of regions and source/drain so that the ectoparasitism of transistor
Resistance also accordingly reduces, and the first impurity of doping can also prevent the p-type impurity in the first extension coating outside
It spreads (for example, being spread into the first stressor layers).
In one example, the first extension coating of whole thickness is reacted with the metal layer is formed as described
One metal silicide, first impurity fractional condensation to first metal silicide and first source region and described the
Interface between one metal silicide and first drain region, for example, first impurity is segregated to first gold medal
Belong to the interface of silicide and first stressor layers.
In one example, the surface portion of the first extension coating is reacted with the metal layer is formed as described
One metal silicide, the first impurity fractional condensation is between first metal silicide and the first extension coating
Interface.
Further, while the annealing steps also make second impurity (Ga and/or C) fractional condensation arrive second gold medal
Belong to the interface between silicide and its semi-conducting material contacted, and the n-type doping impurity (example is captured in interface
Such as, which is the n-type doping impurity adulterated in situ in the second stressor layers), and then form dopant and detach Schottky
(Dopant segregated Schottky, abbreviation DSS), n-type doping impurity is eventually located at interface metal silicide side,
To reduce schottky barrier height (SBH), the contact resistance (Rc) of regions and source/drain is reduced so that transistor
Ectoparasitism resistance also accordingly reduces, and the second impurity of doping can also prevent the n-type doping in the second extension coating
Impurity into the second stressor layers to external diffusion (for example, spreading).
In one example, the second extension coating of whole thickness is reacted with the metal layer is formed as described
Two metal silicides, second impurity fractional condensation to second metal silicide and second source region and described the
Interface between two metal silicides and second drain region, for example, second impurity is segregated to second gold medal
Belong to the interface of silicide and second stressor layers.
In one example, the surface portion of the second extension coating is reacted with the metal layer is formed as described
Two metal silicides, the second impurity fractional condensation is between second metal silicide and the second extension coating
Interface.
It is worth noting that, also progress after metal layer can be formed by the annealing in this step before forming coating.
Later, step 15 is executed, conductive layer is formed and fills first contact hole opening, the second contact hole opening, the
Three contact holes are open and the 4th contact hole opening, to be respectively formed the first contact hole, the second contact hole, third contact hole and the 4th
Contact hole.
Specifically, continue as shown in Figure 1 G, to form conductive layer 113 and fill the first contact hole opening, the second contact hole
Opening, third contact hole opening and the 4th contact hole are open and are planarized, to be respectively formed the first contact hole, the second contact
Hole, third contact hole and the 4th contact hole.
Conductive material can pass through low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition
(PECVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques are formed.
Wherein, conductive layer can be any suitable conductive material well known to those skilled in the art, including but unlimited gold
Belong to material.Preferably, conductive layer is tungsten material.In another embodiment, conductive layer can be cobalt (Co), molybdenum (Mo), titanium nitride
(TiN) and the conductive material or combinations thereof containing tungsten.
The non-limiting examples of the planarization process include mechanical planarization method and chemically mechanical polishing planarization side
Method.The planarization stops on the surface of second interlayer dielectric layer 1092.
First contact hole structure is electrically connected with the source/drain region in the PMOS device area, the second contact hole knot
Structure is electrically connected with the source/drain region in the NMOS device area, and the third contact hole structure is electrically connected the first grid structure,
4th contact hole structure is electrically connected the second grid structure.
So far the introduction for completing the committed step of the manufacturing method of the semiconductor devices to the present invention, for complete device
The step of preparation of part also needs other does not do repeat one by one herein.
In conclusion the manufacturing method of the present invention, in the first source region of the semiconductor substrate in the PMOS device area and
The surface in one drain region is respectively formed on the first extension coating, wherein doped with the first doping in the first extension coating
Impurity (for example, Sb and/or N), in the forming metal layer on surface of the first extension coating, at least partly described first extension
Coating reacts to form the first metal silicide with the metal layer, wherein the first impurity fractional condensation to described first
Interface between metal silicide and its semi-conducting material contacted, and the p-type impurity is captured in interface,
And then dopant separation Schottky (Dopant segregated Schottky, abbreviation DSS) is formed, to reduce Schottky
Barrier height (SBH) reduces the contact resistance (Rc) of regions and source/drain so that the ectoparasitism resistance of transistor also phase
It should reduce, the first impurity of doping can also prevent the p-type impurity in the first extension coating to external diffusion；
In addition, being respectively formed on outside second in the second source region of the semiconductor substrate in NMOS device area and the surface in the second drain region
Prolong coating, wherein doped with the second impurity (for example, Ga and/or C) in the second extension coating, described
The forming metal layer on surface of second extension coating, at least partly described second extension coating react to be formed with the metal layer
Second metal silicide, wherein the second impurity fractional condensation to first metal silicide is partly led with what it was contacted
Interface between body material, and the n-type doping impurity is captured in interface, and then form dopant and detach Schottky
(Dopant segregated Schottky, abbreviation DSS), to reduce schottky barrier height (SBH), reduces source
The contact resistance (Rc) of pole/drain region so that the ectoparasitism resistance of transistor also accordingly reduces, and the second doping of doping is miscellaneous
Matter can also prevent the n-type doping impurity in the second extension coating to external diffusion.Therefore, method of the invention can improve device
The performance of part.
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices is by the manufacturing method in embodiment one above-mentioned
It prepares.
The structure of the semiconductor devices of the present invention is described in detail below with reference to Fig. 1 G.Wherein, main in the present embodiment
By taking FinFET as an example.
Specifically, as shown in Figure 1 G, semiconductor devices of the invention includes：Semiconductor substrate 100, the semiconductor substrate
Including MOS device area.
In one example, the MOS device area includes at least one of PMOS device area, NMOS device area.
The case where with the semiconductor substrate including mainly PMOS device area and NMOS device area in the present embodiment, is to this hair
It is bright to illustrate.
Wherein, semiconductor substrate 100 is body silicon substrate, can be following at least one of the material being previously mentioned：Si、
Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, further include these half
The multilayered structure etc. that conductor is constituted, or to be laminated on stacking silicon (SSOI) on silicon-on-insulator (SOI), insulator, insulator
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
In one example, it is provided with first grid structure in the semiconductor substrate 100 in the PMOS device area,
It is provided with second grid structure in semiconductor substrate 100 in the NMOS device area.
Illustratively, semiconductor devices of the invention is FinFET, partly leading in each PMOS device area
It is formed with the first fin structure 1011 in body substrate, then is formed with the second fin in the semiconductor substrate in the NMOS device area
Chip architecture 1012, the first grid structure is across first fin structure, and second grid structure is across second fin
Structure.
Illustratively, first grid structure is the first metal gate structure 1101 comprising is formed in the PMOS device
The boundary layer of gate trench bottom in area is sequentially formed in the bottom and side wall of gate trench and on the boundary layer
High k dielectric layer, the first diffusion impervious layer, P-type workfunction layer, N-type work function and the second diffusion impervious layer of side, and filling institute
State the gate electrode layer of gate trench.
Illustratively, second grid structure is the second metal gate structure 1102 comprising is formed in the NMOS device
The boundary layer of gate trench bottom in area is sequentially formed in the bottom and side wall of gate trench and on the boundary layer
High k dielectric layer, the first diffusion impervious layer, N-type work function and the second diffusion impervious layer of side, and the filling gate trench
Gate electrode layer.
Wherein it is possible to form the first metal gates knot using any suitable method well known to those skilled in the art
Structure and the second metal gate structure, do not do repeat one by one herein.
It is noted that the first grid structure and second grid structure of the present invention can also be other kinds of
Gate structure, such as gate structure includes the gate dielectric and grid layer stacked gradually from bottom to top, gate dielectric can be with
For dielectric materials such as silica, grid layer can be the materials such as polysilicon.
Illustratively, the channel material below the first grid structure in the PMOS device area includes elemental semiconductor,
Wherein, elemental semiconductors can be any elemental semiconductor used well known to those skilled in the art, including but unlimited
Channel material below the second grid structure in Ge either Si or SiGe, the NMOS device area may include III-V
Compound semiconductor, for example, iii-v binary or ternary semiconductor, in the present embodiment, the iii-v
Conjunction object semiconductor is InGaAs, and in the present embodiment, the elemental semiconductor is Ge, using Group III-V compound semiconductor as
The raceway groove of NMOS device, and raceway groove of the elemental semiconductor as PMOS device is used, carrier mobility can be improved.
In one example, the first clearance wall 1061 is formed on the side wall of the first grid structure, described
The second clearance wall 1062 is formed on the side wall of two gate structures.
In one example, it is provided in the semiconductor substrate in PMOS device area described in first grid structure both sides
First source region and the first drain region, wherein doped with p-type impurity, optionally, P in first source region and the first drain region
Type impurity includes boron.
Illustratively, the first stressor layers 1031, the p-type doping are formed in first source region and first drain region
Impurity is entrained in first stressor layers 1031.
The material of first stressor layers 1031 may include SiGe or other can provide the suitable material of compression.Specifically
Ground, can be used chemical vapor deposition method or gas source molecular beam epitaxy method growing P-type impurity adulterates in situ
SiGe。
Form the stressor layers with compression in PMOS, the performance of cmos device can by by action of compressive stress in
PMOS is improved.
Further, first stressor layers 1031 are formed in first fin structure, and first stress
The top surface of layer 1031 is higher than the top surface of first fin structure.
Further, it has been respectively formed on the first extension coating 107 on the surface in first source region and the first drain region,
In, doped with the first impurity in the first extension coating 107.
In one example, the first stressor layers 1031 are formed in first source region and the first drain region, then described
One extension coating 107 is formed in the surface of first stressor layers 1031.
Wherein, the material of the first extension coating 107 can be any suitable siliceous semi-conducting material, including
But be not limited to SiGe, Si etc..In the present embodiment, the material of the first extension coating 107 is preferably SiGe.
Optionally, the first impurity includes Sb and/or N, in the present embodiment, preferably, the first impurity includes Sb
And N.
In one example, using epitaxial growth technology institute is epitaxially-formed on the surface of first stressor layers 1031
State the first extension coating 107 that the first impurity adulterates in situ.
Optionally, the thickness of the first extension coating 107 can be reasonably selected according to actual process, for example,
The thickness range of first extension coating 107 can be 5 angstroms~20 angstroms or other suitable thickness.
Further, the second source is set in the semiconductor substrate in NMOS device area described in second grid structure both sides
Area and the second drain region, doped with n-type doping impurity in second source region and second drain region, optionally, the N-type is mixed
Impurity includes at least one of phosphorus or arsenic.
In one example, the second stressor layers 1032, the N are formed in second source region and second drain region
Type impurity is entrained in second stressor layers.
In NMOS device area, the second stressor layers 1032 usually have tensile stress.The material of second stressor layers 1032 can be with
For SiP, SiC or other the suitable material of tensile stress can be provided.In the present embodiment, preferably select SiP as the second stress
Layer 1032.
Further, chemical vapor deposition method or gas source molecular beam epitaxy method growth SiP can be used, use silane
Or disilane, as silicon source, phosphine forms the Si epitaxial layers that phosphorus adulterates in situ as phosphorus source.
Further, second stressor layers 1032 are formed in second fin structure, and second stress
The top surface of layer 1032 is higher than the top surface of second fin structure.
Illustratively, the second extension coating 108 is formed on the surface in second source region and second drain region,
Wherein, doped with the second impurity in the second extension coating 108.
In one example, the second stressor layers 1032 are formed in second source region and the second drain region, then described
Two extension coatings 108 are formed on the surface of second stressor layers 1032.
Wherein, the material of the second extension coating 108 can be any suitable siliceous semi-conducting material, including
But be not limited to SiGe, Si etc..In the present embodiment, the material of the second extension coating 108 is preferably SiGe.
Optionally, the second impurity includes Ga and/or C, in the present embodiment, preferably, the second impurity includes Ga
And C.
In one example, using epitaxial growth technology institute is epitaxially-formed on the surface of second stressor layers 1032
State the second extension coating 108 that the second impurity adulterates in situ.
Optionally, the thickness of the second extension coating 108 can be reasonably selected according to actual process, for example,
The thickness range of second extension coating 108 can be 5 angstroms~20 angstroms or other suitable thickness.
Further, in the PMOS device area, on the side of first clearance wall 1061 and part described
It is formed on the surface of one extension coating 107 and on the surface of the first fin structure exposing and on the surface of portions of isolation structure
There is the second spacer material layer 106n.
In one example, in the NMOS device area, on the part surface of second fin structure 1012 and
The first spacer material layer and the second spacer material layer are formed on the surface of portions of isolation structure from bottom to top.
In one example, the first interlayer dielectric layer 1091 is formed on the semiconductor substrate, and first interlayer is situated between
The top surface of electric layer is flushed with the top surface of the first grid structure and the second grid structure.
In one example, in first interlayer dielectric layer and the first grid structure and the second grid knot
The second interlayer dielectric layer is formed on the surface of structure.
Specifically, second interlayer dielectric layer 1092 covers first interlayer dielectric layer 1091 and first gold medal
Belong to the surface of gate structure 1101 and second metal gate structure 1102.
Second interlayer dielectric layer 1092 can be silicon oxide layer, including the use of thermal chemical vapor deposition (thermal
CVD) the material for having doped or undoped silica that manufacturing process or high-density plasma (HDP) manufacturing process are formed
Layer, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer
Can also be the spin cloth of coating-type glass (spin-on-glass, SOG) for adulterating boron or adulterating phosphorus, the tetraethoxy-silicane for adulterating phosphorus
Alkane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).
The thickness of second interlayer dielectric layer 1092 can be any suitable numerical value, be not specifically limited herein, the
The top surface of two interlayer dielectric layers 1092 is higher than the top of the first metal gate structure 1101 and second metal gate structure 1102
Face.
In one example, is formed in second interlayer dielectric layer 1092 and first interlayer dielectric layer 1091
One contact hole is open, and the first contact hole opening exposes the surface of the first extension coating 107, in second interlayer
The second contact hole opening is formed in dielectric layer 1092 and first interlayer dielectric layer 1091, the second contact hole opening is exposed
The surface of the second extension coating 108.
Further, the bottom of the first contact hole opening is located in the extension coating 107, second contact
The bottom of hole opening is located in the second extension coating 108.
Further, third contact hole opening is formed in second interlayer dielectric layer 1092 and the 4th contact hole is opened
Mouthful, wherein the third contact hole opening exposes the top surface of first metal gate structure 1101, and the 4th contact hole is opened
Mouth exposes the top surface of second metal gate structure 1102.
Further, it is connect in first contact hole opening, second contact hole opening, third contact hole opening and the 4th
It is formed with metal layer 112 in the bottom and side wall of contact hole opening.
Wherein, the material of metal layer can use titanium (Ti), nickeliferous (nickel), cobalt (cobalt) and platinum (platinum)
Or combinations thereof material, in the present embodiment, the material preferably with metal layer is Ti.
Further, coating (not shown) is formed on the metal layer 112.
Covering layer material is material such as tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, the nitrogen of metal or metal compound layer
Change titanium zirconium, tungsten, tungsten nitride, its alloy or its constituent.In addition, coating also may include multiple film layers, and in the present embodiment, institute
It includes TiN layer to state coating.
Further, metal layer 112 is occurred by annealing with the first extension coating contacted and the second extension coating
Reaction, and then form the first metal silicide and the second metal silicide (for example, TiSi).
Further, it is formed with the first metal silicide on the surface of the first extension coating 107, wherein described
First impurity is segregated to the interface between first metal silicide and its semi-conducting material contacted.
In one example, the first metal silicide surrounds the bottom of the first contact hole opening, and the first metal
The bottom of silicide is located at the surface in the first extension coating 107 and higher than the semiconductor substrate.
In one example, the first metal silicide surrounds the bottom of the second contact hole opening, and the first metal
The bottom of silicide is located at the surface in the second extension coating 108 and higher than the semiconductor substrate.
The annealing simultaneously makes first impurity (Sb and N) fractional condensation be contacted to first metal silicide with it
Semi-conducting material between interface, and capture the p-type impurity (for example, the p-type impurity is in interface
The p-type impurity adulterated in situ in first stressor layers), and then form dopant separation Schottky (Dopant segregated
Schottky, abbreviation DSS), p-type impurity is eventually located at interface metal silicide side, to reduce Schottky gesture
Height (SBH) is built, reduces the contact resistance (Rc) of regions and source/drain so that the ectoparasitism resistance of transistor is also corresponding
Reduce, the first impurity of doping can also prevent the p-type impurity in the first extension coating to external diffusion (for example,
It is spread into the first stressor layers).
In one example, the first extension coating of whole thickness is reacted with the metal layer is formed as described
One metal silicide, first impurity fractional condensation to first metal silicide and first source region and described the
Interface between one metal silicide and first drain region, for example, first impurity is segregated to first gold medal
Belong to the interface of silicide and first stressor layers.
In one example, the surface portion of the first extension coating is reacted with the metal layer is formed as described
One metal silicide, the first impurity fractional condensation is between first metal silicide and the first extension coating
Interface.
In one example, it is formed with the second metal silicide on the surface of the second extension coating, wherein described
Second impurity is segregated to the interface between second metal silicide and the semi-conducting material of its contact, and
Capture the n-type doping impurity.
Further, while the annealing steps also make second impurity (Ga and/or C) fractional condensation arrive second gold medal
Belong to the interface between silicide and its semi-conducting material contacted, and the n-type doping impurity (example is captured in interface
Such as, which is the n-type doping impurity adulterated in situ in the second stressor layers), and then form dopant and detach Schottky
(Dopant segregated Schottky, abbreviation DSS), n-type doping impurity is eventually located at interface metal silicide side,
To reduce schottky barrier height (SBH), the contact resistance (Rc) of regions and source/drain is reduced so that transistor
Ectoparasitism resistance also accordingly reduces, and the second impurity of doping can also prevent the n-type doping in the second extension coating
Impurity into the second stressor layers to external diffusion (for example, spreading).
In one example, whole second extension coatings are reacted with the metal layer is formed as second metal
Silicide, the second impurity fractional condensation to second metal silicide and second source region and second metal
Interface between silicide and second drain region, for example, second impurity is segregated to second metal silication
The interface of object and second stressor layers.
In one example, the surface portion of the second extension coating is reacted with the metal layer is formed as described
Two metal silicides, the second impurity fractional condensation is between second metal silicide and the second extension coating
Interface.
In one example, the first contact hole opening, the second contact hole opening, third contact hole opening and the 4th connect
Contact hole opening is filled with conductive layer 113, to respectively constitute the first contact hole, the second contact hole, third contact hole and the 4th contact
Hole.
First contact hole is electrically connected with the source/drain region in the PMOS device area, second contact hole with it is described
Source/drain region electrical connection in NMOS device area, the third contact hole are electrically connected the first grid structure, the 4th contact
Hole is electrically connected the second grid structure.
So far the introduction for completing the key structure of the semiconductor devices to the present invention, is also possible to wrap for complete device
Other components are included, do not do repeating one by one herein.
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.
The semiconductor devices of the present invention has low schottky barrier height, low contact resistance, therefore its ectoparasitism
Capacitance is also lower, has higher device performance.
Embodiment three
The present invention also provides a kind of electronic device, including the semiconductor devices described in embodiment two, the semiconductor devices
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products for including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
The wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：
Semiconductor substrate, the semiconductor substrate include MOS device area, in the semiconductor substrate in the MOS device area
Active area and drain region are set；
It is respectively formed on extension coating on the surface in the source region and the drain region, wherein in the extension coating
In doped with impurity；
It is formed with metal silicide on the surface of the extension coating, wherein the impurity fractional condensation to the gold
Belong to the interface between the semi-conducting material that silicide and the metal silicide are contacted.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate is provided, the semiconductor substrate includes MOS device area, and the semiconductor in the MOS device area serves as a contrast
Active area and drain region are set in bottom；
It is respectively formed on extension coating on the surface in the source region and the drain region, wherein adulterated in the extension coating
There is impurity；
In the forming metal layer on surface of the extension coating；
It reacts at least partly described extension coating to form metal silicide with the metal layer, wherein the impurity
Segregate the interface between the semi-conducting material that the metal silicide and the metal silicide are contacted.
2. manufacturing method as described in claim 1, which is characterized in that the MOS device area includes PMOS device area, NMOS devices
At least one of part area；
The intratectal impurity of extension in the PMOS device area includes Sb and/or N；
The intratectal impurity of extension in the NMOS device area includes Ga and/or C.
3. manufacturing method as described in claim 1, which is characterized in that by the extension coating of whole thickness and the gold
Belong to layer reaction and is formed as the metal silicide, the impurity fractional condensation to the metal silicide and the source region and institute
State the interface between metal silicide and the drain region；Alternatively,
The surface portion of the extension coating is reacted with the metal layer is formed as the metal silicide, the impurity
Segregate the interface between the metal silicide and the extension coating.
4. manufacturing method as described in any one of claims 1 to 3, which is characterized in that before forming the extension coating,
It is further comprising the steps of：Stressor layers are formed in the source region and the drain region, the extension coating is formed in the stress
On the surface of layer.
5. manufacturing method as claimed in claim 4, which is characterized in that the method for forming the stressor layers includes：
Semiconductor substrate described in etching part, to form groove in the source region and the drain region；
The stressor layers adulterated in situ are epitaxially-formed in the groove.
6. manufacturing method as claimed in claim 2, which is characterized in that the MOS device area includes PMOS device area and NMOS
Device region, before the extension coating for forming the PMOS device area, alternatively, being covered in the extension for forming the PMOS device area
It after cap rock, is formed before the metal layer in the PMOS device area, in the table of the source region and the drain region in the NMOS device area
The extension coating is formed on face.
7. manufacturing method as described in claim 1, which is characterized in that by annealing make the extension coating with it is described
Metal layer reacts to form the metal silicide.
8. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include MOS device area, are arranged in the semiconductor substrate in the MOS device area
Active area and drain region；
It is respectively formed on extension coating on the surface in the source region and the drain region, wherein mixed in the extension coating
It is miscellaneous to have impurity；
It is formed with metal silicide on the surface of the extension coating, wherein the impurity fractional condensation to the metallic silicon
Interface between the semi-conducting material that compound and the metal silicide are contacted.
9. semiconductor devices as claimed in claim 8, which is characterized in that the MOS device area includes PMOS device area, NMOS
At least one of device region；
The intratectal impurity of extension in the PMOS device area includes Sb and/or N；
The intratectal impurity of extension in the NMOS device area includes Ga and/or C.
10. semiconductor devices as claimed in claim 8, which is characterized in that the impurity fractional condensation to the metal silication
Interface between object and the source region and the metal silicide and the drain region；Alternatively,
The impurity is segregated to the interface between the metal silicide and the extension coating.
11. semiconductor devices as claimed in claim 8, which is characterized in that be formed with and answer in the source region and the drain region
Power layer, the extension coating are formed on the surface of the stressor layers.
12. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor described in one of claim 8 to 11
Device.
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