CN107968071A - A kind of semiconductor devices and its manufacture method and electronic device - Google Patents
A kind of semiconductor devices and its manufacture method and electronic device Download PDFInfo
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- CN107968071A CN107968071A CN201610915730.3A CN201610915730A CN107968071A CN 107968071 A CN107968071 A CN 107968071A CN 201610915730 A CN201610915730 A CN 201610915730A CN 107968071 A CN107968071 A CN 107968071A
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 12
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- 230000026267 regulation of growth Effects 0.000 claims description 11
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- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 18
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method and electronic device, is related to technical field of semiconductors.This method includes：Stress epitaxial layer is formed in source/drain region in nmos area, the stress epitaxial layer includes the second stress epitaxial layer of the first width positioned at bottom, tertiary stress epitaxial layer on the second stress epitaxial layer, wherein, tertiary stress epitaxial layer includes the tertiary stress epitaxial layer of the second width and the tertiary stress epitaxial layer of the 3rd width more than the second clearance wall top surface from bottom to top, wherein the first width is less than the second width, second width is less than the 3rd width, therefore the top of stress epitaxial layer is expanded, make contact area bigger, so as to which stress epitaxial layer has relatively low external resistance, furthermore, due to not increasing the volume of bottom stress epitaxial layer, short-channel effect is set also to have obtained good control, and then improve the performance and yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method and electronics
Device.
Background technology
In technical field of semiconductors, with developing rapidly for nanofabrication technique, the characteristic size of transistor has been enter into
Nanoscale.The performance of the silicon CMOS device of current main-stream this mode is improved by the method for scaled down, is subject to more next
The limitation of more physics and technique.In order to improve the performance of NMOS and PMOS transistor in cmos device, stress technique
(stress engineering) is increasingly paid close attention to be subject to industry.
The mobility of carrier in stress influence semiconductor.In general, the mobility of electronics is with along electricity in silicon
The increase of the tension of sub- migratory direction and increase, and reduced with the increase of compression.On the contrary, in silicon positively charged sky
The mobility in cave increases with the increase of the compression of hole moving direction, and reduces with the increase of tension.Cause
This, can be by introducing appropriate compression and the hole mobility and NMOS of PMOS can be respectively increased in tension in channels
Electron mobility, such as：By the performance of germanium silicon (SiGe) process improving PMOS, NMOS is improved by phosphorus silicon (SiP) technique
Performance.
Source/drain (S/D) extension profile is very crucial for the performance and yield for lifting FinFET.For nmos device
SiP stress epitaxial layers preparation process, it is not the preferable knot that we want that SiP, which merges epitaxial layer (merged epitaxy),
Structure, it is unfavorable for the raising of device performance, but if design needs relatively low external resistance (external resistance),
Then just need stress epitaxial layer that there is larger volume, it is therefore desirable to the volume and profile of rational balance extension, so as to improve
The performance of device.In addition, larger SiP extensions are unfavorable for the control of short-channel effect, because the lateral diffusion-capability of phosphorus is too poor.
Therefore, it is necessary to a kind of semiconductor devices and its manufacture method are proposed, reasonably to balance the body of source drain epitaxial
Product and profile, so as to further improve the performance of device.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, a kind of manufacture method of semiconductor devices is provided in the embodiment of the present invention one, including：
Semiconductor substrate is provided, the Semiconductor substrate includes PMOS areas and nmos area, in the PMOS areas and nmos area
The first fin structure and the second fin structure are respectively formed with interior Semiconductor substrate；
It is developed across part first fin structure and part second fin respectively in the PMOS areas and nmos area
The first dummy gate structure and the second dummy gate structure of chip architecture；
The one stress extension of growth regulation in the source/drain region of first fin structure of the first dummy gate structure both sides
Layer；
The first clearance wall is formed on the side wall of second fin structure of the second dummy gate structure both sides；
First etch-back is carried out to the source/drain region of exposed second fin structure, to remove part second fin
Chip architecture forms the first groove；
The thickness of first clearance wall is thinned, to expand the width of first groove to the first width；
Two stress epitaxial layer of growth regulation on second fin structure exposed in first groove, with described in filling
First groove, wherein the width of the second stress epitaxial layer is first width；
The second clearance wall is formed on the side wall of second fin structure and the second stress epitaxial layer；
Second etch-back removes part the second stress epitaxial layer, to form the second groove；
The thickness of second clearance wall is thinned, to expand the width of second groove to the second width；
Tertiary stress epitaxial layer is grown on the surface of the second stress epitaxial layer, to fill full second groove simultaneously
Spill on the top surface of remaining second clearance wall, wherein, the tertiary stress epitaxial layer in second groove
Width is second width, and the tertiary stress epitaxial layer more than the second clearance wall top surface is wide with the 3rd
Degree, wherein, first width is less than second width, and second width is less than the 3rd width.
Further, after first dummy gate structure and second dummy gate structure is formed, described first is formed
It is further comprising the steps of before stress epitaxial layer：
The first spacer material layer is deposited, to cover the PMOS areas and the nmos area；
Patterned first photoresist layer is formed, to cover the nmos area, exposes the PMOS areas；
Using patterned first photoresist layer as mask, etching remove on the first fin structure top surface with
And part the first spacer material layer on the semiconductor substrate surface；
Etch-back remove part first fin structure in the source/drain region of the first dummy gate structure both sides and
Part the first spacer material layer on first fin structure.
Further, after the first stress epitaxial layer is formed, formed before first clearance wall, further include step
Suddenly：Oxidation processes are carried out, to form the first oxide skin(coating) on the surface that the first stress epitaxial layer exposes.
Further, the method for forming first clearance wall comprises the following steps：
The second spacer material layer is deposited, to cover the PMOS areas and the nmos area；
Patterned second photoresist layer is formed, exposes the nmos area to cover the PMOS areas；
Etching removes described the on the semiconductor substrate surface on the second fin structure top surface and in nmos area
One spacer material layer and the second spacer material layer, to form described first on the side wall of second fin structure
Clearance wall, and the top surface of the second fin structure described in exposed portion.
Further, after the first etch-back step, it is thinned before the thickness of first clearance wall, further includes step
Suddenly：The surface of second fin structure to exposing aoxidizes, and to form the second oxide skin(coating), and is being thinned described second
After the step of thickness of clearance wall, second oxide skin(coating) is subjected to prerinse removal.
Further, the process for forming second clearance wall comprises the following steps：
The third space wall material bed of material is deposited, to cover the PMOS areas and the nmos area；
Patterned 3rd photoresist layer is formed, exposes the nmos area to cover the PMOS areas；
Etching is removed in the Semiconductor substrate on the second stress epitaxial layer top surface and in the nmos area
The part third space wall material bed of material, to be formed on the side wall of second fin structure and the second stress epitaxial layer
Second clearance wall.
Further, the thickness range of first clearance wall is 60~120 angstroms.
Further, the depth bounds of first etch-back is 20~40nm.
Further, it is thinned after first clearance wall, the thickness range of remaining first clearance wall is 2~6nm.
Further, it is thinned after second clearance wall, the thickness range of remaining second clearance wall is 2~6nm.
Further, the depth bounds of second etch-back is 10~20nm.
Further, the material of the second stress epitaxial layer and the tertiary stress epitaxial layer includes SiP.
Further, being thinned and to second clearance wall to first clearance wall is realized using the method for wet etching
Be thinned.
Further, the wet etching uses the etchant for including phosphoric acid.
Further, the method further includes：
Between the Semiconductor substrate, the first stress epitaxial layer, the tertiary stress epitaxial layer and described second
Contact etch stop layer is formed on the surface of gap wall；
The interlevel dielectric deposition on the contact etch stop layer, and planarize the interlayer dielectric layer.
Further, the material of the first stress epitaxial layer includes SiGe.
The embodiment of the present invention two provides a kind of semiconductor devices, including：
Semiconductor substrate, the Semiconductor substrate includes PMOS areas and nmos area, in the PMOS areas and nmos area
The first fin structure and the second fin structure are respectively formed with the Semiconductor substrate；
It is respectively formed with the PMOS areas and nmos area across part first fin structure and part described second
The first grid structure and second grid structure of fin structure；
Formed with the first stress extension in the source/drain region of first fin structure of the first grid structure both sides
Layer；
From bottom to top formed with first in the source-drain area of second fin structure of the second grid structure both sides
The second stress epitaxial layer, the tertiary stress epitaxial layer of the second width and the tertiary stress epitaxial layer of the 3rd width of width,
Wherein, first width is less than second width, and second width is less than the 3rd width；
Second fin structure, the second stress epitaxial layer, second width tertiary stress epitaxial layer
Formed with clearance wall on side wall.
Further, it is also formed with the first oxide skin(coating) on the surface of the first stress epitaxial layer.
Further, on the surface of first oxide skin(coating), it is on the side wall of first fin structure and described
Formed with spacer material floor on semiconductor substrate surface in PMOS areas.
Further, the material of the second stress epitaxial layer and the tertiary stress epitaxial layer includes SiP.
Further, further include：
In the Semiconductor substrate, the first stress epitaxial layer, the tertiary stress epitaxial layer and the clearance wall
Surface on formed with contact etch stop layer；
Deposition has interlayer dielectric layer on the contact etch stop layer.
Further, the material of the first stress epitaxial layer includes SiGe.
The embodiment of the present invention three provides a kind of electronic device, it includes foregoing semiconductor devices.
Manufacturing method according to the invention, clearance wall conduct is used in the source/drain region growth stress epitaxial layer of nmos area
Guiding, therefore will not be formed and merge epitaxial layer (merged epitaxy), further, since the top of stress epitaxial layer is expanded,
Make contact area bigger, therefore stress epitaxial layer has relatively low external resistance (external resistance), furthermore, due to
Do not increase the volume of bottom stress epitaxial layer substantially, short-channel effect has also been obtained good control, therefore, according to this hair
Bright manufacture method, reasonably balances the volume and profile of source/drain stress epitaxial layer, improves the performance of device and good
Rate.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 to Figure 18 shows a kind of correlation step shape of the manufacture method of semiconductor devices in one embodiment of the invention
Into structure sectional view；
Figure 19 shows a kind of indicative flowchart of the manufacture method of semiconductor devices of one embodiment of the invention；
Figure 20 shows the schematic diagram of the electronic device in one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
Embodiment one
In view of problems of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, such as Figure 20 institutes
Show, it is mainly included the following steps that：
Step S201, there is provided Semiconductor substrate, the Semiconductor substrate includes PMOS areas and nmos area, in the PMOS areas
With the first fin structure and the second fin structure are respectively formed with the Semiconductor substrate in nmos area；
Step S202, part first fin structure and part are developed across in the PMOS areas and nmos area respectively
The first dummy gate structure and the second dummy gate structure of two fin structures；
Step S203, the growth regulation in the source/drain region of first fin structure of the first dummy gate structure both sides
One stress epitaxial layer；
Step S204, forms between first on the second fin structure two side of the second dummy gate structure both sides
Gap wall；
Step S205, carries out the first etch-back, to remove part institute to the source/drain region of exposed second fin structure
State the second fin structure and form the first groove；
Step S206, is thinned the thickness of first clearance wall, to expand the width of first groove to the first width；
Step S207, two stress epitaxial layer of growth regulation on second fin structure exposed in first groove,
To fill first groove, wherein the width of the second stress epitaxial layer is first width；
Step S208, the second gap is formed on the side wall of second fin structure and the second stress epitaxial layer
Wall；
Step S209, the second etch-back removes part the second stress epitaxial layer, to form the second groove；
Step S210, is thinned the thickness of second clearance wall, to expand the width of second groove to the second width；
Step S211, grows tertiary stress epitaxial layer on the surface of the second stress epitaxial layer, full described to fill
Second groove is simultaneously spilt on the top surface of remaining second clearance wall, wherein, the in second groove the described 3rd should
The width of power epitaxial layer is second width, the tertiary stress epitaxial layer tool more than the second clearance wall top surface
There is the 3rd width, wherein, first width is less than second width, and second width is less than the 3rd width.
Manufacturing method according to the invention, in nmos area source/drain region using clearance wall as drawing during growth stress epitaxial layer
Lead, therefore will not be formed and merge epitaxial layer (merged epitaxy), further, since expanding the top of stress epitaxial layer, make
Contact area bigger, therefore stress epitaxial layer has relatively low external resistance, furthermore, due to not increasing bottom stress extension substantially
The volume of layer, makes short-channel effect also obtain good control, therefore, manufacturing method according to the invention, rational balance
The volume and profile of source/drain stress epitaxial layer, improves the performance and yield of device.
In the following, the manufacture method of the semiconductor devices of the present invention is described in detail referring to figs. 1 to Figure 18, wherein,
Fig. 1 to Figure 18 shows the structure that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
Sectional view.
Specifically, first, as shown in Figure 1, there is provided Semiconductor substrate 100, the Semiconductor substrate 100 include PMOS areas and
Nmos area, is respectively formed with the first fin structure 1011 and in the Semiconductor substrate 100 in the PMOS areas and nmos area
Two fin structures 1012.
Specifically, Semiconductor substrate 100 its can be at least one of following material being previously mentioned：Si、Ge、SiGe、
SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, further include the multilayer knot of these semiconductors composition
Structure etc., or be laminated for silicon-on-insulator (SOI), on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..In the present embodiment, Semiconductor substrate 100 is preferably
Silicon substrate.
Formed with the first fin structure 1011 in Semiconductor substrate 100 in the PMOS areas, in each NMOS
Formed with the second fin structure 1012 in Semiconductor substrate 100 in area.
In one example, forming first fin structure 1011 and the method for second fin structure 1012 includes
Following steps：
Patterned mask layer is formed on the surface of the Semiconductor substrate 100, the patterned mask layer definition has
The pattern of first fin structure 1011 and second fin structure 1012, including the width of fin, length and position
Deng；Using the patterned mask layer as mask, the Semiconductor substrate 100 is etched, to form first fin structure
1011 and second fin structure 1012.Mask layer can usually include any type of several mask materials, include but not limited to：
Hard mask material and photoresist mask material.It can use the methods of dry etching or wet etching and carry out above-mentioned etching, wherein,
Dry etching process can be any of reactive ion etching, ion beam milling, plasma etching, laser ablation or these methods
Combination.Single engraving method can also be used, or more than one engraving method can also be used.
It should be noted that form the method for first fin structure 1011 and second fin structure 1012 only
It is exemplary, it is not limited to the above method.
The width of fin structure is all identical, or fin is divided into multiple fin structure groups with different in width, fin
The length of structure can also differ.
Isolation structure 102 is also formed with a semiconductor substrate 100, and isolation structure 102 can be that shallow trench isolates (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure, in the present embodiment, isolation structure 102 are preferably shallow trench isolation
Structure.The top surface of the isolation structure 102 is less than the first fin structure 1011 and the top surface of second fin structure 1012.Partly lead
Various traps (well) structure is also formed with body substrate 100, for example, being formed in PMOS areas formed with N-type trap in nmos area
There is p-type trap, to put it more simply, being omitted in diagram.
Then, as shown in figure 3, being developed across part first fin structure respectively in the PMOS areas and nmos area
1011 and the first dummy gate structure and the second dummy gate structure of the second fin structure of part 1012.
Exemplarily, the first dummy gate structure and the second dummy gate structure include dummy grid dielectric layer 1031 and dummy grid
Material layer 1032.
It is pointed out that the term " across " used in the present invention, such as across fin structure (such as the first fin
Structure, second fin structure etc.) gate structure (for example, dummy gate structure), refer in the upper surface of the part of fin structure
Gate structure is each formed with side, and the gate structure is also formed on the part surface of Semiconductor substrate.
In one example, as shown in Fig. 2, first can be sequentially depositing to form dummy grid dielectric layer on a semiconductor substrate 100
1031。
Wherein, the dummy grid dielectric layer 1031 can be silica (SiO2) or silicon oxynitride (SiON).It can use
Oxidation technology such as furnace oxidation, rapid thermal annealing oxidation (RTO), steam oxidation in situ known by those skilled in the art
(ISSG) etc. the dummy grid dielectric layer 1031 of silica material is formed.Silicon oxynitride can be formed by performing nitriding process to silica,
Wherein, the nitriding process can be high temperature furnace pipe nitridation, rapid thermal annealing nitrogenizes or pecvd nitride, it is, of course, also possible to
Using other nitriding processes, which is not described herein again.Can also be other chemical vapor deposition method and physical vapour deposition (PVD)
Method etc. forms dummy grid dielectric layer 1031.
In one example, the shape on all surfaces of the first fin structure 1011 and the second fin structure 1012 that expose
Into there is dummy grid dielectric layer 1031.
Then, as shown in figure 3, forming dummy grid material layer 1032 on the dummy grid dielectric layer 1031, and changed
Mechanical lapping is learned to obtain flat surface.
Dummy grid material layer 1032 can select semi-conducting material commonly used in the art, such as can select polysilicon etc.,
A certain kind is not limited to, will not enumerate herein,
The deposition process of the dummy grid material layer includes chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition
(PECVD), it is possible to use the general similarity method such as sputter and physical vapour deposition (PVD) (PVD).
Then dummy grid dielectric layer 1031 and the dummy grid material layer 1032 are patterned, to form the first dummy gate structure
With the second dummy gate structure.Specifically, hard mask layer 11 is formed in the dummy grid material layer, then on hard mask layer 11
Photoresist layer is formed, then exposure imaging, to form opening, then using the photoresist layer as hard mask layer described in mask etch
11 and dummy grid material layer 1032.
Afterwards, also optionally, offset side is formed on the side wall of the first dummy gate structure and the second dummy gate structure
Wall (not shown).
Specifically, the offset side wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.As embodiment in the one of the present embodiment, the offset side wall is silica, silicon nitride collectively constitutes, and concrete technology is：
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on a semiconductor substrate, then using engraving method
Form offset side wall.Spacer material layer can also be respectively formed in the top surface and side wall of dummy gate structure, in the steps afterwards
By the method for planarization, such as chemical mechanical grinding, the spacer material layer on top surface is removed, formation is located only within side wall
Offset side wall.
Then, LDD ion implantings are carried out respectively to the PMOS areas and the nmos area.
Wherein, LDD ion implantings can reduce electric field to form lightly doped drain (LDD) structure in source/drain region, and can be with
Significantly improve thermoelectronic effect.
Exemplarily, LDD ions are carried out to the first fin structure 1011 of the first dummy gate structure both sides in PMOS areas
Injection, to form p-type lightly doped drain (LDD), it can be arbitrary p-type Doped ions that it, which injects ion, include but not limited to boron
(B) ion, indium (In) ion.
LDD ion implantings are carried out to the second fin structure 1012 of the second dummy gate structure both sides in nmos area again, with
N-type lightly doped drain (LDD) is formed, it can be any suitable n-type doping ion that it, which injects ion, include but not limited to phosphorus (P)
Ion, arsenic (As) ion.
Then, as shown in figure 4, the first spacer material layer 104 is deposited, to cover the PMOS areas and the nmos area.
Specifically, the first spacer material layer 104 is formed on the surface of the isolation structure 102 exposed, is described first pseudo-
On gate structure and the top surface and side wall of the second dummy gate structure and the first dummy gate structure and the second dummy gate structure two
On first fin structure 1011 of side and the side wall and top surface of the second fin structure 1012.
First spacer material layer 104 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.As an embodiment of the present embodiment, the first spacer material layer 104 is silicon nitride.
It can use and include but not limited to：The method of chemical vapor deposition method and physical gas-phase deposite method forms first
Spacer material layer 104.
Then, as shown in figure 5, forming patterned first photoresist layer 1051, to cover the nmos area, expose described
PMOS areas.
Specifically, using photoetching process (including coating photoresist, and the process such as exposure imaging), to form this patterned
First photoresist layer 1051, patterned first photoresist layer 1051 expose the first spacer material floor in the PMOS areas
104。
Then, it is mask with patterned first photoresist layer 1051, etching, which removes, is located at the first fin knot
On 1011 top surface of structure and on 100 surface of Semiconductor substrate described in the part on (namely on 102 surface of isolation structure)
First spacer material layer 104, retains the institute of on the side wall of the first dummy gate structure and the first dummy gate structure both sides
State the first spacer material layer 104 on 1021 side wall of the first fin structure.
The method of etching can use any suitable dry etching or wet etching well known to those skilled in the art
The methods of.
Then, continue as shown in figure 5, etch-back removes the part in the source/drain region of the first dummy gate structure both sides
Part the first spacer material layer 104 on first fin structure 1011 and first fin structure 1011.
Etch-back can use the side such as any suitable dry etching well known to those skilled in the art or wet etching
Method.It is preferred that using anisotropic dry etching method, dry method etch technology includes but not limited to：Reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting.Dry method is carried out preferably by one or more RIE step
Etching.
Afterwards, patterned first photoresist layer 1051 is removed.The method of ashing can be used to remove described first
Photoresist layer 1051.
Then, as shown in fig. 6, the source/drain of first fin structure 1011 in the first dummy gate structure both sides
One stress epitaxial layer 106 of growth regulation in area.
Can use selective epitaxial growth method on the surface of the first fin structure 1011 exposed growth regulation one
Stress epitaxial layer 106, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecule
One kind in beam epitaxy (MBE).
The material of first stress epitaxial layer 106, which can include SiGe or other, can provide the suitable material of compression.Tool
Body, chemical vapor deposition method either gas source molecular beam epitaxy method growth SiGe silane or disilane can be used
As silicon source, while add a certain amount of germane.For example, select GeH4And SiH2Cl2As reacting gas, and select H2As
The flow-rate ratio of carrier gas, wherein reacting gas and carrier gas is 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, is preferably 650-
750 DEG C, gas pressure 1-50Torr, be preferably 20-40Torr.
Form the stressor layers with compression in PMOS, the performance of cmos device can by by action of compressive stress in
PMOS is improved.
Wherein, it is preferred that the cross sectional shape of the first stress epitaxial layer 106 is preferably " ∑ " shape.
Then, as shown in fig. 7, oxidation processes are carried out, to be formed on the surface that the first stress epitaxial layer 106 exposes
First oxide skin(coating) 107.
Oxidation technology such as furnace oxidation, rapid thermal annealing known by those skilled in the art can be used to aoxidize
(RTO), steam oxidation (ISSG) in situ etc. forms the first oxide skin(coating) of formation 107 of silica material.
Then, continue as shown in fig. 7, the second spacer material layer 1081 of deposition, to cover PMOS areas and described
Nmos area.
Second spacer material layer 1081 can use the material identical with the first foregoing spacer material layer 104, the
Two spacer material layers 1081 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.It is used as this reality
A kind of embodiment of example is applied, the second spacer material layer 1081 is silicon nitride.
It can use and include but not limited to：The method of chemical vapor deposition method and physical gas-phase deposite method forms second
Spacer material layer 1081.
Wherein, in PMOS areas, the second spacer material layer 1081 covers the surface of the first stress epitaxial layer 106,
On first oxide skin(coating) 107, and on the side wall of the first fin structure 1011 in PMOS areas and isolation structure
102 surface is respectively formed on the second spacer material layer 1081.
Then, as shown in figure 8, forming patterned second photoresist layer 1052, to cover described in the PMOS areas exposure
Nmos area, is mask with patterned second photoresist layer 1052, etching remove on 1012 top surface of the second fin structure with
And the first spacer material layer on 100 surface of Semiconductor substrate in nmos area and the second spacer material layer,
To form first clearance wall 108, and the second fin described in exposed portion on the side wall of second fin structure 1012
The top surface of structure 1012.
Specifically, using photoetching process (including coating photoresist, and the process such as exposure imaging), to form this patterned
Second photoresist layer 1052, patterned second photoresist layer 1052 expose the second spacer material layer in the nmos area.
Wherein, the first spacer material layer on 100 surface of Semiconductor substrate in nmos area and described the are removed
Two spacer material layers, namely remove the first spacer material layer on 102 surface of isolation structure in nmos area and institute
State the second spacer material layer.
The method of etching can use any suitable dry etching or wet etching well known to those skilled in the art
The methods of, it is preferred that the method using dry etching.
Exemplarily, the thickness range of first clearance wall 108 can be 60~120 angstroms, and above-mentioned thickness range is only made
For example, other suitable scopes are equally applicable to the present invention.
Then, as shown in figure 9, being mask with patterned second photoresist layer 1052, to exposed second fin
The source/drain region of structure 1012 carries out the first etch-back, and the first groove is formed to remove part second fin structure 1012
109。
In one example, which also removes the dummy grid dielectric on 1012 side wall of the second fin structure at the same time
Layer 1031.
First etch-back can use any suitable dry etching or wet etching well known to those skilled in the art
Or the methods of combinations thereof.It is preferred that using anisotropic dry etching method, dry method etch technology includes but unlimited
In：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Preferably by one or more
RIE step carries out dry etching.
Afterwards, patterned second photoresist layer 1052 is removed.The method of ashing can be used to remove
Patterned second photoresist layer 1052.
Exemplarily, the depth bounds of first etch-back is 20~40nm, namely from the second fin structure 1012
The depth bounds that top surface starts downward etch-back is 20~40nm, which is only used as example.
Then, as shown in Figure 10, the surface of second fin structure 1012 to exposing aoxidizes, to form second
Oxide skin(coating) 110.
Specifically, the surface of second fin structure 1012 to exposing from the first groove 109 aoxidizes, with shape
Into the second oxide skin(coating) 110.Etching stopping layer of second oxide skin(coating) 110 as after during the first clearance wall of etching.
Oxidation technology such as furnace oxidation, rapid thermal annealing known by those skilled in the art can be used to aoxidize
(RTO), steam oxidation (ISSG) in situ etc. forms the second oxide skin(coating) of formation 110 of silica material.
Then, as shown in figure 11, the thickness of first clearance wall 108 is thinned, to expand the width of first groove 109
Spend to the first width L1.
Exemplarily, being thinned to first clearance wall 108 is realized using the method for wet etching.
In one example, when the material of first clearance wall 108 is silicon nitride, the wet etching can use
Etchant including phosphoric acid, to realize being thinned to first clearance wall 108, which can also be the phosphoric acid solution of heat,
It has high etch-rate to silicon nitride, and has low etch-rate to oxide etc..
Wherein, in the present embodiment, it is thinned after first clearance wall 108, the thickness of remaining first clearance wall 108
Degree scope is 2~6nm, but is not limited thereto.
It is noted that can be to PMOS during first clearance wall 108 is thinned in the wet etching, while also
The second spacer material floor in area has carried out etching and has been thinned.
Then, the second oxide skin(coating) 110 is removed by prerinse, to expose the second fin in the first groove 109
The top surface of chip architecture 1012.Exemplarily, prerinse can use hydrofluoric acid solution, such as buffer oxide etch agent
(buffer oxide etchant (BOE)) or hydrofluoric acid buffer solution (buffer solution of hydrofluoric
acid(BHF))。
Then, as shown in figure 12, growth regulation on second fin structure 1012 exposed in first groove 109
Two stress epitaxial layers 111, to fill first groove, wherein the width of the second stress epitaxial layer 111 is described first
Width L1.
Can use selective epitaxial growth method on the surface of the second fin structure 1012 exposed growth regulation two
Stress epitaxial layer 111, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecule
One kind in beam epitaxy (MBE).
In NMOS, the second stress epitaxial layer 111 usually has tension.The material of second stress epitaxial layer 111 can be with
For SiP, SiC or other the suitable material of tension can be provided.In the present embodiment, SiP is preferably selected as the second stress
Epitaxial layer.Specifically, chemical vapor deposition method or gas source molecular beam epitaxy method growth SiP can be used, with silane or
Person's disilane is as silicon source, and phosphine is as phosphorus source.
Wherein, the top surface of the second stress epitaxial layer 111 can also be above the top surface of the first clearance wall 108 on its side wall, this
Growth of one clearance wall 108 for the second stress epitaxial layer 111 has guiding function, controls its between the first clearance wall
Grown up in one groove.
The surface also optionally exposed to the second stress epitaxial layer carries out oxidation processes, should to form oxide skin(coating)
Etching stopping layer when oxide skin(coating) can be as the etched gap wall material bed of material afterwards.
Then, as shown in figure 13, the third space wall material bed of material 1121 is deposited, to cover the PMOS areas and the NMOS
Area.
The third space wall material bed of material 1121 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.As an embodiment of the present embodiment, the third space wall material bed of material 1121 is silicon nitride.
It can use and include but not limited to：The method of chemical vapor deposition method and physical gas-phase deposite method forms the 3rd
Spacer material layer 1121.
Then, as shown in figure 14, patterned 3rd photoresist layer 1053 is formed, to cover described in the PMOS areas exposure
Nmos area, with patterned 3rd photoresist layer 1053 for mask, etching, which removes, is located at 111 top surface of the second stress epitaxial layer
The part third space wall material bed of material 1121 in Semiconductor substrate 100 in upper and described nmos area, with described the
Second clearance wall 112 is formed on the side wall of two fin structures 1012 and the second stress epitaxial layer 111.
Specifically, using photoetching process (including coating photoresist, and the process such as exposure imaging), to form this patterned
3rd photoresist layer 1053, patterned 3rd photoresist layer 1053 expose the third space wall material bed of material in the nmos area
1121。
Wherein, the third space wall material bed of material 1121 on 100 surface of Semiconductor substrate in nmos area is removed, namely is removed
The third space wall material bed of material 1121 on 102 surface of isolation structure in nmos area.
The method of etching can use any suitable dry etching or wet etching well known to those skilled in the art
The methods of, it is preferred that the method using dry etching.
In one example, when on the second stress epitaxial layer 111 formed with oxide, can also by the oxide removal,
To expose the top surface of the second stress epitaxial layer 111.
Then, as shown in figure 15, with patterned 3rd photoresist layer 1053 for mask, the second etch-back removal portion
Divide the second stress epitaxial layer 111, to form the second groove 113.
Second etch-back can use any suitable dry etching or wet etching well known to those skilled in the art
Or the methods of combinations thereof.It is preferred that using anisotropic dry etching method, dry method etch technology includes but unlimited
In：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Preferably by one or more
RIE step carries out dry etching.
Exemplarily, wet etching can be used has high etch-rate to the second stress epitaxial layer 111, to clearance wall
There is the engraving method of low etch-rate with isolation structure.
Exemplarily, the depth bounds of second etch-back is 10~20nm, namely from the top of the second stress epitaxial layer
The depth bounds that face starts downward etch-back is 10~20nm, which is only used as example.
Afterwards, patterned 3rd photoresist layer 1053 is removed.The method of ashing can be used to remove
Patterned 3rd photoresist layer 1053.
Then, as shown in figure 16, the thickness of second clearance wall 112 is thinned, to expand the width of second groove 113
Spend to the second width L2.
Exemplarily, being thinned to second clearance wall 112 is realized using the method for wet etching.
In one example, when the material of second clearance wall 112 is silicon nitride, the wet etching can use
Etchant including phosphoric acid, to realize being thinned to second clearance wall 112, which can also be the phosphoric acid solution of heat,
It has high etch-rate to silicon nitride, and has low etch-rate to oxide etc..
Wherein, in the present embodiment, it is thinned after second clearance wall 112, the thickness of remaining second clearance wall 112
Degree scope is 2~6nm, but is not limited thereto.
It is noted that can be right during second clearance wall 1128 is thinned in the wet etching, while also
The third space wall material bed of material 1121 in PMOS areas has carried out etching and has been thinned.
Then, as shown in figure 17, tertiary stress epitaxial layer 114 is grown on the surface of the second stress epitaxial layer 111,
To fill full second groove and spill on the top surface of remaining second clearance wall 112, wherein, second groove
The width of the interior tertiary stress epitaxial layer 112 is the second width L2, more than 112 top surface of the second clearance wall
The tertiary stress epitaxial layer 114 there is the 3rd width L3, wherein, the first width L1 is less than the second width L2,
The second width L2 is less than the 3rd width L3.
It is noted that first width, the second width and the 3rd width refer to vertical with semiconductor substrate surface
And the face vertical with the extending direction of the fin structure goes section the second stress epitaxial layer and tertiary stress epitaxial layer to be obtained
The width of the respective cross-section obtained.
Can use selective epitaxial growth method on the surface of the second stress epitaxial layer 111 exposed growth regulation three
Stress epitaxial layer 114, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecule
One kind in beam epitaxy (MBE).
In NMOS, tertiary stress epitaxial layer 114 usually has tension.The material of tertiary stress epitaxial layer 114 can be with
For SiP, SiC or other the suitable material of tension can be provided.In the present embodiment, SiP is preferably selected as tertiary stress
Epitaxial layer 114.Specifically, chemical vapor deposition method or gas source molecular beam epitaxy method growth SiP can be used, uses silane
Or disilane, as silicon source, phosphine is as phosphorus source.
Wherein, in epitaxial growth tertiary stress epitaxial layer 114, second clearance wall 112 is for tertiary stress epitaxial layer
114 growth has guiding function, controls and is grown up in its second groove between the second clearance wall 112.
By the above method, SiP stress epitaxial layers are formd in the source/drain region in nmos area, the stress epitaxial layer bag
Include positioned at bottom the first width the second stress epitaxial layer, the tertiary stress epitaxial layer on the second stress epitaxial layer, its
In, tertiary stress epitaxial layer includes the tertiary stress epitaxial layer of the second width and more than the second clearance wall top surface from bottom to top
The 3rd width tertiary stress epitaxial layer, wherein the first width is less than the second width, the second width is less than the 3rd width, therefore
The top of stress epitaxial layer is expanded, makes contact area bigger, so that stress epitaxial layer has relatively low external resistance, furthermore, by
In the volume for not increasing bottom stress epitaxial layer, short-channel effect is set also to have obtained good control.
Then, as shown in figure 18, answered in the Semiconductor substrate 100, the first stress epitaxial layer the 106, the described 3rd
Contact etch stop layer 115 is formed on the surface of power epitaxial layer 114 and second clearance wall 112；In the contact hole
Interlevel dielectric deposition 116 on etching stopping layer 115, and planarize the interlayer dielectric layer 116.
Contact etch stop layer (CESL) 115 is formed over the substrate, and the contact etch stop layer may include
One dielectric material, such as material, nitrogenous material, carbonaceous material or homologue.
Contact etch stop layer 115 may include any two kinds in several etch stop materials.Non-limiting example bag
Include conductor etch and stop material, conductor etching stopping material and dielectric etch stop material.Due in following additional description
The reason for becoming more apparent from, etching stopping layer include the etch stop material easily influenced by local change, it is etching
Stop-layer provides the specific etching selectivity in region.The contact etch stop layer 115 is the bag comprising two layers in the present invention
Containing one layer of oxide skin(coating) inside and the nitride layer outside the oxide skin(coating), wherein the oxide can be selected
SiO2, the nitride can select one kind in SiCN, SiN, SiC, SiOF, SiON, but the contact etch stops
Layer is not limited to above-mentioned example.
Then interlevel dielectric deposition 116 and planarize.It is flat that the non-limiting examples of the planarization process include machinery
Smoothization method and chemical mechanical grinding (CMP) flattening method.
Interlayer dielectric layer 116 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process
Or the material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, such as without mixing
Miscellaneous silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron
Or the spin cloth of coating-type glass (spin-on-glass, SOG) of doping phosphorus, the tetraethoxysilane (PTEOS) of doping phosphorus or doping
The tetraethoxysilane (BTEOS) of boron.
So far the introduction of the key step of the manufacture method of the semiconductor devices to the present invention is completed, for complete device
The making of part also needs other preceding steps, intermediate steps or subsequent step, and this is no longer going to repeat them.
Manufacturing method according to the invention, in nmos area source/drain region using clearance wall as drawing during growth stress epitaxial layer
Lead, therefore will not be formed and merge epitaxial layer (merged epitaxy), further, since expanding the top of stress epitaxial layer, make
Contact area bigger, therefore stress epitaxial layer has relatively low external resistance, furthermore, due to not increasing bottom stress extension substantially
The volume of layer, makes short-channel effect also obtain good control, therefore, manufacturing method according to the invention, rational balance
The volume and profile of source/drain stress epitaxial layer, improves the performance and yield of device.
Embodiment two
The present invention also provides a kind of semiconductor devices prepared using method in previous embodiment one.
Specifically, as shown in Figure 17 and Figure 18, semiconductor devices of the invention includes Semiconductor substrate 100, described partly to lead
Body substrate 100 includes PMOS areas and nmos area, being respectively formed with the Semiconductor substrate 100 in the PMOS areas and nmos area
First fin structure 1011 and the second fin structure 1012.
Specifically, Semiconductor substrate 100 its can be at least one of following material being previously mentioned：Si、Ge、SiGe、
SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, further include the multilayer knot of these semiconductors composition
Structure etc., or be laminated for silicon-on-insulator (SOI), on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..In the present embodiment, Semiconductor substrate 100 is preferably
Silicon substrate.
Formed with the first fin structure 1011 in Semiconductor substrate 100 in the PMOS areas, in each NMOS
Formed with the second fin structure 1012 in Semiconductor substrate 100 in area.
In one example, forming first fin structure 1011 and the method for second fin structure 1012 includes
Following steps：
Patterned mask layer is formed on the surface of the Semiconductor substrate 100, the patterned mask layer definition has
The pattern of first fin structure 1011 and second fin structure 1012, including the width of fin, length and position
Deng；Using the patterned mask layer as mask, the Semiconductor substrate 100 is etched, to form first fin structure
1011 and second fin structure 1012.Mask layer can usually include any type of several mask materials, include but not limited to：
Hard mask material and photoresist mask material.It can use the methods of dry etching or wet etching and carry out above-mentioned etching, wherein,
Dry etching process can be any of reactive ion etching, ion beam milling, plasma etching, laser ablation or these methods
Combination.Single engraving method can also be used, or more than one engraving method can also be used.
It should be noted that form the method for first fin structure 1011 and second fin structure 1012 only
It is exemplary, it is not limited to the above method.
The width of fin structure is all identical, or fin is divided into multiple fin structure groups with different in width, fin
The length of structure can also differ.
Isolation structure 102 is also formed with a semiconductor substrate 100, and isolation structure 102 can be that shallow trench isolates (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure, in the present embodiment, isolation structure 102 are preferably shallow trench isolation
Structure.The top surface of the isolation structure 102 is less than the first fin structure 1011 and the top surface of second fin structure 1012.Partly lead
Various traps (well) structure is also formed with body substrate 100, for example, being formed in PMOS areas formed with N-type trap in nmos area
There is p-type trap, to put it more simply, being omitted in diagram.
Further, it is respectively formed with the PMOS areas and nmos area across part first fin structure 1011 and portion
Divide the first grid structure and second grid structure of the second fin structure 1012.
First grid structure and second grid structure include gate dielectric 1031 and grid layer 1032 from bottom to top.
1031 gate dielectric of gate dielectric can be formed by thermal oxide, nitridation or oxynitridation process.Forming grid
During the dielectric layer of pole, above-mentioned technique can also be applied in combination.Gate dielectric can include following any conventional dielectric：
SiO2、Si3N4、SiON、SiON2, such as TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3High-k dielectric and including calcium titanium
Other similar oxides of ore deposit type oxide, but not limited to this.In general, high-k dielectric is amenable to (900 DEG C) annealing of high temperature.Grid
Pole dielectric layer can also include any combinations of above-mentioned dielectric substance.
Grid layer 1032 is formed on gate dielectric 1031.In one embodiment, grid layer is made of polycrystalline silicon material,
The material of metal, metal nitride, metal silicide or similar compound as grid layer generally can also be used.
In one example, formed with the source/drain region of the first fin structure 1011 of first grid structure both sides
One stress epitaxial layer 106, is also formed with the first oxide skin(coating) 107, described on the surface of the first stress epitaxial layer 106
Semiconductor on the surface of first oxide skin(coating) 107, on the side wall of first fin structure 1011 and in the PMOS areas
Formed with spacer material layer 1121 on 100 surface of substrate.
The material of first stress epitaxial layer 106, which can include SiGe or other, can provide the suitable material of compression.
Form the stressor layers with compression in PMOS, the performance of cmos device can by by action of compressive stress in
PMOS is improved.
Wherein, it is preferred that the cross sectional shape of the first stress epitaxial layer 106 is preferably " ∑ " shape.
Exemplarily, the first oxide skin(coating) 107 is the silica formed using the method for oxidation processes.
Spacer material layer 1121 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.Make
For an embodiment of the present embodiment, spacer material layer 1121 is silicon nitride.
Further, semiconductor devices of the invention is additionally included in second fin of the second grid structure both sides
The second stress epitaxial layer 111 formed with the first width L1, the of the second width L2 from bottom to top in the source/drain region of structure 1012
The tertiary stress epitaxial layer 114 of three stress epitaxial layers 114 and the 3rd width L3, wherein, the first width L1 is less than institute
The second width L2 is stated, the second width L2 is less than the 3rd width L3, in the second fin structure 1012, second stress
Epitaxial layer 111, second width tertiary stress epitaxial layer 114 side wall on formed with clearance wall 112.
Clearance wall 112 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.It is used as this reality
A kind of embodiment of example is applied, clearance wall 112 is silicon nitride.
In NMOS, the second stress epitaxial layer 111 and tertiary stress epitaxial layer 114 usually have tension.Second stress
The material of epitaxial layer 111 and tertiary stress epitaxial layer 114 can be SiP, SiC or other can provide the suitable material of tension
Material.In the present embodiment, SiP is preferably selected as the second stress epitaxial layer 111 and tertiary stress epitaxial layer 114.Specifically, may be used
Using chemical vapor deposition method, either gas source molecular beam epitaxy method grows SiP by the use of silane or disilane as silicon source,
Phosphine is as phosphorus source.
Exemplarily, the second stress epitaxial layer 111 and tertiary stress epitaxial layer 114 can also have tension for different
Material.
The semiconductor devices of the present invention, it forms SiP stress epitaxial layers, the stress in source/drain region in nmos area
Epitaxial layer includes the second stress epitaxial layer of the first width positioned at bottom, outside the tertiary stress on the second stress epitaxial layer
Prolong layer, wherein, tertiary stress epitaxial layer includes the tertiary stress epitaxial layer of the second width and positioned at the second clearance wall from bottom to top
The tertiary stress epitaxial layer of the 3rd more than top surface width, wherein the first width is less than the second width, the second width is less than the 3rd
Width, therefore the top of stress epitaxial layer is expanded, make contact area bigger, therefore stress epitaxial layer has relatively low dispatch from foreign news agency
Resistance, furthermore, due to not increasing the volume of bottom stress epitaxial layer, short-channel effect has also been obtained good control.
Further, in the Semiconductor substrate 100, the first stress epitaxial layer 106, the tertiary stress epitaxial layer
114 and the clearance wall 112 surface on formed with contact etch stop layer 115；In the contact etch stop layer
Deposition has interlayer dielectric layer 116 on 115.
Contact etch stop layer (CESL) 115 is formed over the substrate, and the contact etch stop layer may include
One dielectric material, such as material, nitrogenous material, carbonaceous material or homologue.
Contact etch stop layer 115 may include any two kinds in several etch stop materials.Non-limiting example bag
Include conductor etch and stop material, conductor etching stopping material and dielectric etch stop material.Due in following additional description
The reason for becoming more apparent from, etching stopping layer include the etch stop material easily influenced by local change, it is etching
Stop-layer provides the specific etching selectivity in region.The contact etch stop layer 115 is the bag comprising two layers in the present invention
Containing one layer of oxide skin(coating) inside and the nitride layer outside the oxide skin(coating), wherein the oxide can be selected
SiO2, the nitride can select one kind in SiCN, SiN, SiC, SiOF, SiON, but the contact etch stops
Layer is not limited to above-mentioned example.
Interlayer dielectric layer 116 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process
Or the material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, such as without mixing
Miscellaneous silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron
Or the spin cloth of coating-type glass (spin-on-glass, SOG) of doping phosphorus, the tetraethoxysilane (PTEOS) of doping phosphorus or doping
The tetraethoxysilane (BTEOS) of boron.
For complete device, it further includes other structure elements, does not do repeating one by one herein.
Since the semiconductor devices of the present invention is prepared using foregoing method, have the advantages that identical.
The semiconductor devices of the present invention, uses clearance wall to be used as guiding in nmos area source/drain region during growth stress epitaxial layer,
Therefore it will not be formed and merge epitaxial layer (merged epitaxy), further, since the semiconductor devices of the present invention includes expanding
Stress epitaxial layer top, make contact area bigger, therefore stress epitaxial layer has relatively low external resistance, furthermore, due to base
Do not increase the volume of bottom stress epitaxial layer in sheet, short-channel effect has also been obtained good control, reasonably balance source/
The volume and profile of drain stress epitaxial layer, therefore, the performance higher of semiconductor devices according to the present invention.
Embodiment three
Present invention also offers a kind of electronic device, including the semiconductor devices described in embodiment two, the semiconductor
Device method according to embodiment one is prepared.
The electronic device of the present embodiment, can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, or any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Figure 20 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, is included in shell 301
In display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices mainly wraps
Include：
Semiconductor substrate, the Semiconductor substrate includes PMOS areas and nmos area, in the PMOS areas and nmos area
The first fin structure and the second fin structure are respectively formed with Semiconductor substrate；
It is respectively formed with the PMOS areas and nmos area across part first fin structure and the second fin of part
The first grid structure and second grid structure of structure；
Formed with the first stress epitaxial layer in the source/drain region of the first fin structure of first grid structure both sides；
From bottom to top formed with first in the source-drain area of second fin structure of the second grid structure both sides
The second stress epitaxial layer, the tertiary stress epitaxial layer of the second width and the tertiary stress epitaxial layer of the 3rd width of width,
Wherein, first width is less than second width, and second width is less than the 3rd width；
The second fin structure, the second stress epitaxial layer, second width tertiary stress epitaxial layer side wall
On formed with clearance wall.
The electronic device of the present invention includes foregoing semiconductor devices, therefore also has the advantages that identical.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (23)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that the described method includes：Semiconductor substrate is provided, the Semiconductor substrate includes PMOS areas and nmos area, in the PMOS areas and nmos area The first fin structure and the second fin structure are respectively formed with Semiconductor substrate；It is developed across part first fin structure and part the second fin knot respectively in the PMOS areas and nmos area The first dummy gate structure and the second dummy gate structure of structure；The one stress epitaxial layer of growth regulation in the source/drain region of first fin structure of the first dummy gate structure both sides；The first clearance wall is formed on the side wall of second fin structure of the second dummy gate structure both sides；First etch-back is carried out to the source/drain region of exposed second fin structure, to remove part the second fin knot It is configured to the first groove；The thickness of first clearance wall is thinned, to expand the width of first groove to the first width；Two stress epitaxial layer of growth regulation on second fin structure exposed in first groove, to fill described first Groove, wherein the width of the second stress epitaxial layer is first width；The second clearance wall is formed on the side wall of second fin structure and the second stress epitaxial layer；Second etch-back removes part the second stress epitaxial layer, to form the second groove；The thickness of second clearance wall is thinned, to expand the width of second groove to the second width；Tertiary stress epitaxial layer is grown on the surface of the second stress epitaxial layer, to fill full second groove and overflow Onto the top surface of remaining second clearance wall, wherein, the width of the tertiary stress epitaxial layer in second groove For second width, the tertiary stress epitaxial layer more than the second clearance wall top surface has the 3rd width, its In, first width is less than second width, and second width is less than the 3rd width.
- 2. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that forming the first dummy grid knot After structure and second dummy gate structure, formed before the first stress epitaxial layer, it is further comprising the steps of：The first spacer material layer is deposited, to cover the PMOS areas and the nmos area；Patterned first photoresist layer is formed, to cover the nmos area, exposes the PMOS areas；Using patterned first photoresist layer as mask, etching removes on the first fin structure top surface and position In part the first spacer material layer on the semiconductor substrate surface；Etch-back removes part first fin structure in the source/drain region of the first dummy gate structure both sides and described Part the first spacer material layer on first fin structure.
- 3. manufacture method as claimed in claim 1 or 2, it is characterised in that after the first stress epitaxial layer is formed, shape Into before first clearance wall, step is further included：Oxidation processes are carried out, with the surface that the first stress epitaxial layer exposes The first oxide skin(coating) of upper formation.
- 4. manufacture method as claimed in claim 2, it is characterised in that forming the method for first clearance wall includes following step Suddenly：The second spacer material layer is deposited, to cover the PMOS areas and the nmos area；Patterned second photoresist layer is formed, exposes the nmos area to cover the PMOS areas；Etching is removed between described first on the semiconductor substrate surface on the second fin structure top surface and in nmos area The gap wall material bed of material and the second spacer material layer, to form first gap on the side wall of second fin structure Wall, and the top surface of the second fin structure described in exposed portion.
- 5. manufacture method as claimed in claim 1, it is characterised in that after the first etch-back step, be thinned described Before the thickness of first clearance wall, step is further included：The surface of second fin structure to exposing aoxidizes, to be formed Second oxide skin(coating), and after the step of thickness of second clearance wall is thinned, second oxide skin(coating) is carried out pre- Cleaning removes.
- 6. manufacture method as claimed in claim 1, it is characterised in that forming the process of second clearance wall includes following step Suddenly：The third space wall material bed of material is deposited, to cover the PMOS areas and the nmos area；Patterned 3rd photoresist layer is formed, exposes the nmos area to cover the PMOS areas；Etching removes the part in the Semiconductor substrate on the second stress epitaxial layer top surface and in the nmos area The third space wall material bed of material, described in being formed on the side wall of second fin structure and the second stress epitaxial layer Second clearance wall.
- 7. manufacture method as claimed in claim 1, it is characterised in that the thickness range of first clearance wall is 60~120 Angstrom.
- 8. manufacture method as claimed in claim 1, it is characterised in that the depth bounds of first etch-back for 20~ 40nm。
- 9. manufacture method as claimed in claim 1, it is characterised in that it is thinned after first clearance wall, it is remaining described The thickness range of first clearance wall is 2~6nm.
- 10. manufacture method as claimed in claim 1, it is characterised in that it is thinned after second clearance wall, it is remaining described The thickness range of second clearance wall is 2~6nm.
- 11. manufacture method as claimed in claim 1, it is characterised in that the depth bounds of second etch-back for 10~ 20nm。
- 12. manufacture method as claimed in claim 1, it is characterised in that the second stress epitaxial layer and the tertiary stress The material of epitaxial layer includes SiP.
- 13. manufacture method as claimed in claim 1, it is characterised in that realized using the method for wet etching to described first Clearance wall being thinned and second clearance wall be thinned.
- 14. manufacture method as claimed in claim 13, it is characterised in that the wet etching uses the etching for including phosphoric acid Agent.
- 15. manufacture method as claimed in claim 1, it is characterised in that the method further includes：In the Semiconductor substrate, the first stress epitaxial layer, the tertiary stress epitaxial layer and second clearance wall Surface on form contact etch stop layer；The interlevel dielectric deposition on the contact etch stop layer, and planarize the interlayer dielectric layer.
- 16. manufacture method as claimed in claim 1, it is characterised in that the material of the first stress epitaxial layer includes SiGe.
- A kind of 17. semiconductor devices, it is characterised in that including：Semiconductor substrate, the Semiconductor substrate includes PMOS areas and nmos area, described in the PMOS areas and nmos area The first fin structure and the second fin structure are respectively formed with Semiconductor substrate；It is respectively formed with the PMOS areas and nmos area across part first fin structure and part second fin The first grid structure and second grid structure of structure；Formed with the first stress epitaxial layer in the source/drain region of first fin structure of the first grid structure both sides；From bottom to top formed with the first width in the source-drain area of second fin structure of the second grid structure both sides The second stress epitaxial layer, the tertiary stress epitaxial layer of the second width and the tertiary stress epitaxial layer of the 3rd width, wherein, First width is less than second width, and second width is less than the 3rd width；Second fin structure, the second stress epitaxial layer, second width tertiary stress epitaxial layer side wall On formed with clearance wall.
- 18. semiconductor devices as claimed in claim 17, it is characterised in that on the surface of the first stress epitaxial layer also Formed with the first oxide skin(coating).
- 19. semiconductor devices as claimed in claim 18, it is characterised in that on the surface of first oxide skin(coating), institute State on the semiconductor substrate surface on the side wall of the first fin structure and in the PMOS areas formed with spacer material floor.
- 20. semiconductor devices as claimed in claim 17, it is characterised in that the second stress epitaxial layer and the described 3rd should The material of power epitaxial layer includes SiP.
- 21. semiconductor devices as claimed in claim 17, it is characterised in that further include：In the table of the Semiconductor substrate, the first stress epitaxial layer, the tertiary stress epitaxial layer and the clearance wall Formed with contact etch stop layer on face；Deposition has interlayer dielectric layer on the contact etch stop layer.
- 22. semiconductor devices as claimed in claim 17, the material of the first stress epitaxial layer includes SiGe.
- 23. a kind of electronic device, it is characterised in that including such as claim 17 to 22 any one of them semiconductor devices.
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| US20090095980A1 (en) * | 2007-10-16 | 2009-04-16 | Chen-Hua Yu | Reducing Resistance in Source and Drain Regions of FinFETs |
| US20150091059A1 (en) * | 2013-09-30 | 2015-04-02 | United Microelectronics Corp. | PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE AND PRODUCT THEREOF |
| US9450047B1 (en) * | 2015-03-31 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure having enlarged regrowth regions and manufacturing method of the same |
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