CN107968071B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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CN107968071B
CN107968071B CN201610915730.3A CN201610915730A CN107968071B CN 107968071 B CN107968071 B CN 107968071B CN 201610915730 A CN201610915730 A CN 201610915730A CN 107968071 B CN107968071 B CN 107968071B
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epitaxial layer
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CN107968071A (en
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: and forming a stress epitaxial layer in a source/drain region in the NMOS region, wherein the stress epitaxial layer comprises a second stress epitaxial layer with a first width positioned at the bottom and a third stress epitaxial layer positioned on the second stress epitaxial layer, the third stress epitaxial layer comprises a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width positioned above the top surface of the second gap wall from bottom to top, the first width is smaller than the second width, and the second width is smaller than the third width, so that the top of the stress epitaxial layer is enlarged, the contact area is larger, the stress epitaxial layer has lower external resistance, and furthermore, because the volume of the bottom stress epitaxial layer is not increased, the short channel effect is well controlled, and the performance and the yield of the device are improved.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In the field of semiconductor technology, with the rapid development of nano-fabrication technology, the feature size of transistors has entered the nanometer scale. The way to improve the performance of currently mainstream silicon CMOS devices by scaling down is subject to increasing physical and process limitations. Stress engineering (stress engineering) is receiving increasing attention in the industry to improve the performance of NMOS and PMOS transistors in CMOS devices.
Stress affects the mobility of carriers in the semiconductor. In general, the mobility of electrons in silicon increases with increasing tensile stress along the direction of electron migration, and decreases with increasing compressive stress. In contrast, the mobility of positively charged holes in silicon increases with increasing compressive stress in the direction of hole movement and decreases with increasing tensile stress. Therefore, the hole mobility of PMOS and the electron mobility of NMOS can be respectively improved by introducing appropriate compressive stress and tensile stress in the channel, for example: the PMOS performance is improved by a silicon germanium (SiGe) process and the NMOS performance is improved by a silicon phosphorous (SiP) process.
Source/drain (S/D) epitaxial profiles are critical to improving performance and yield of FinFET devices. For the preparation process of the SiP stress epitaxial layer of the NMOS device, the SiP merged epitaxial layer (merged epitaxixy) is not an ideal structure that we want, which is not good for the improvement of the device performance, but if the design needs a lower external resistance (external resistance), the stress epitaxial layer is required to have a larger volume, so that the volume and the profile of the epitaxial layer need to be reasonably balanced, thereby improving the device performance. In addition, larger SiP epitaxy is detrimental to short channel effect control because the lateral diffusion capability of phosphorus is too poor.
Therefore, there is a need for a semiconductor device and a method for fabricating the same that can reasonably balance the volume and profile of the source/drain epitaxy, thereby further improving the device performance.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;
forming a first dummy gate structure and a second dummy gate structure respectively crossing a portion of the first fin structure and a portion of the second fin structure in the PMOS region and the NMOS region;
growing a first stress epitaxial layer in the source/drain regions of the first fin structures on two sides of the first dummy gate structure;
forming first gap walls on the side walls of the second fin structures at two sides of the second dummy gate structure;
performing first back etching on the exposed source/drain regions of the second fin structures to remove part of the second fin structures to form first grooves;
thinning the thickness of the first gap wall to enlarge the width of the first groove to a first width;
growing a second stress epitaxial layer on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stress epitaxial layer is the first width;
forming second spacer walls on the second fin structures and the side walls of the second stress epitaxial layer;
a second etching back step is carried out to remove part of the second stress epitaxial layer so as to form a second groove;
thinning the thickness of the second gap wall to enlarge the width of the second groove to a second width;
and growing a third stress epitaxial layer on the surface of the second stress epitaxial layer to fill the second groove and overflow to the top surface of the rest second gap wall, wherein the width of the third stress epitaxial layer in the second groove is the second width, and the third stress epitaxial layer above the top surface of the second gap wall has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width.
Further, after the first dummy gate structure and the second dummy gate structure are formed and before the first stress epitaxial layer is formed, the method further comprises the following steps:
depositing a first spacer material layer to cover the PMOS region and the NMOS region;
forming a patterned first photoresist layer to cover the NMOS region and expose the PMOS region;
etching and removing a part of the first spacer material layer on the top surface of the first fin structure and on the surface of the semiconductor substrate by taking the patterned first photoresist layer as a mask;
and etching back to remove a part of the first fin structure in the source/drain regions at two sides of the first dummy gate structure and a part of the first spacer material layer on the first fin structure.
Further, after the first stress epitaxial layer is formed and before the first spacer is formed, the method further comprises the following steps: and carrying out oxidation treatment to form a first oxide layer on the exposed surface of the first stress epitaxial layer.
Further, the method of forming the first spacer includes the steps of:
depositing a second spacer material layer to cover the PMOS region and the NMOS region;
forming a patterned second photoresist layer to cover the PMOS region and expose the NMOS region;
and etching and removing the first gap wall material layer and the second gap wall material layer on the top surface of the second fin structure and the surface of the semiconductor substrate in the NMOS area so as to form the first gap wall on the side wall of the second fin structure and expose part of the top surface of the second fin structure.
Further, after the first etching back step and before the step of reducing the thickness of the first spacer, the method further comprises the steps of: and oxidizing the exposed surface of the second fin structure to form a second oxide layer, and after the step of thinning the thickness of the second spacer, pre-cleaning and removing the second oxide layer.
Further, the process of forming the second spacer includes the steps of:
depositing a third spacer material layer to cover the PMOS region and the NMOS region;
forming a patterned third photoresist layer to cover the PMOS region and expose the NMOS region;
and etching and removing part of the third spacer material layer on the top surface of the second stress epitaxial layer and the semiconductor substrate in the NMOS region so as to form the second spacers on the second fin structures and the side walls of the second stress epitaxial layer.
Furthermore, the thickness range of the first gap wall is 60-120 angstroms.
Furthermore, the depth range of the first back etching is 20-40 nm.
Further, after the first gap wall is thinned, the thickness range of the rest first gap wall is 2-6 nm.
Further, after the second gap wall is thinned, the thickness range of the rest second gap wall is 2-6 nm.
Further, the depth range of the second back etching is 10-20 nm.
Further, the materials of the second stress epitaxial layer and the third stress epitaxial layer both comprise SiP.
Further, the thinning of the first gap wall and the thinning of the second gap wall are realized by using a wet etching method.
Further, the wet etching uses an etchant including phosphoric acid.
Further, the method further comprises:
forming a contact hole etching stop layer on the surfaces of the semiconductor substrate, the first stress epitaxial layer, the third stress epitaxial layer and the second gap wall;
and depositing an interlayer dielectric layer on the contact hole etching stop layer, and flattening the interlayer dielectric layer.
Further, the material of the first stressed epitaxial layer comprises SiGe.
An embodiment of the present invention provides a semiconductor device, including:
the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;
forming a first gate structure and a second gate structure respectively crossing a part of the first fin structure and a part of the second fin structure in the PMOS region and the NMOS region;
forming a first stress epitaxial layer in the source/drain regions of the first fin structures on two sides of the first gate structure;
a second stress epitaxial layer with a first width, a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width are formed in the source-drain regions of the second fin structures on two sides of the second gate structure from bottom to top, wherein the first width is smaller than the second width, and the second width is smaller than the third width;
and forming gap walls on the side walls of the second fin structure, the second stress epitaxial layer and the third stress epitaxial layer with the second width.
Further, a first oxide layer is formed on the surface of the first stress epitaxial layer.
Further, a layer of spacer material is formed on the surface of the first oxide layer, on sidewalls of the first fin structures, and on the surface of the semiconductor substrate within the PMOS region.
Further, the materials of the second stress epitaxial layer and the third stress epitaxial layer both comprise SiP.
Further, still include:
forming a contact hole etching stop layer on the surfaces of the semiconductor substrate, the first stress epitaxial layer, the third stress epitaxial layer and the gap wall;
an interlayer dielectric layer is deposited on the contact hole etching stop layer.
Further, the material of the first stressed epitaxial layer comprises SiGe.
The third embodiment of the invention provides an electronic device, which comprises the semiconductor device.
According to the manufacturing method of the invention, the spacer is used as a guide when the stress epitaxial layer grows in the source/drain region of the NMOS region, so that a merged epitaxial layer (merged epitoxy) cannot be formed, in addition, the top of the stress epitaxial layer is enlarged, so that the contact area is larger, so that the stress epitaxial layer has lower external resistance (external resistance), and in addition, the volume of the bottom stress epitaxial layer is not basically increased, so that the short channel effect is well controlled, therefore, according to the manufacturing method of the invention, the volume and the profile of the source/drain stress epitaxial layer are reasonably balanced, and the performance and the yield of the device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 to 18 are cross-sectional views showing structures formed at relevant steps of a method of manufacturing a semiconductor device in an embodiment of the present invention;
fig. 19 is a schematic flow chart showing a method of manufacturing a semiconductor device of an embodiment of the present invention;
fig. 20 shows a schematic diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
In view of the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 20, which mainly comprises the following steps:
step S201, providing a semiconductor substrate, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;
step S202, forming a first dummy gate structure and a second dummy gate structure which cross over part of the first fin structure and part of the second fin structure in the PMOS area and the NMOS area respectively;
step S203, growing a first stress epitaxial layer in the source/drain regions of the first fin structures on the two sides of the first dummy gate structure;
step S204, forming first clearance walls on two side walls of the second fin structures at two sides of the second dummy gate structure;
step S205, performing a first etching back on the exposed source/drain region of the second fin structure to remove a portion of the second fin structure to form a first trench;
step S206, thinning the thickness of the first gap wall to enlarge the width of the first groove to a first width;
step S207, growing a second stress epitaxial layer on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stress epitaxial layer is the first width;
step S208, forming a second spacer on the second fin structure and the sidewall of the second stress epitaxial layer;
step S209, a second etch-back process is performed to remove a portion of the second stress epitaxial layer to form a second groove;
step S210, thinning the thickness of the second gap wall to enlarge the width of the second groove to a second width;
step S211, growing a third stress epitaxial layer on the surface of the second stress epitaxial layer to fill the second groove and overflow onto the top surface of the remaining second spacer, where the width of the third stress epitaxial layer in the second groove is the second width, and the third stress epitaxial layer located above the top surface of the second spacer has a third width, where the first width is smaller than the second width, and the second width is smaller than the third width.
According to the manufacturing method, the spacer is used as a guide when the stress epitaxial layer grows in the source/drain region of the NMOS region, so that a merged epitaxial layer (merged epitoxy) cannot be formed, in addition, the top of the stress epitaxial layer is enlarged, so that the contact area is larger, the stress epitaxial layer has lower external resistance, and in addition, the volume of the bottom stress epitaxial layer is not basically enlarged, so that the short channel effect is well controlled, therefore, according to the manufacturing method, the volume and the profile of the source/drain stress epitaxial layer are reasonably balanced, and the performance and the yield of the device are improved.
Next, a detailed description is given of a manufacturing method of a semiconductor device of the present invention with reference to fig. 1 to 18, in which fig. 1 to 18 show cross-sectional views of structures formed at relevant steps of a manufacturing method of a semiconductor device in an embodiment of the present invention.
Specifically, first, as shown in fig. 1, a semiconductor substrate 100 is provided, where the semiconductor substrate 100 includes a PMOS region and an NMOS region, and a first fin structure 1011 and a second fin structure 1012 are formed on the semiconductor substrate 100 in the PMOS region and the NMOS region, respectively.
Specifically, the semiconductor substrate 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. In the present embodiment, the semiconductor substrate 100 is preferably a silicon substrate.
First fin structures 1011 are formed on the semiconductor substrate 100 in the PMOS region and second fin structures 1012 are formed on the semiconductor substrate 100 in each of the NMOS regions.
In one example, a method of forming the first fin structures 1011 and the second fin structures 1012 includes the steps of:
forming a patterned mask layer on the surface of the semiconductor substrate 100, where the patterned mask layer defines patterns of the first fin structure 1011 and the second fin structure 1012, including width, length, and position of a fin; the semiconductor substrate 100 is etched using the patterned mask layer as a mask to form the first fin structures 1011 and the second fin structures 1012. The mask layer may generally comprise any of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. The etching may be performed by dry etching, wet etching, or the like, wherein the dry etching process may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
It is noted that the method of forming the first fin structures 1011 and the second fin structures 1012 is merely exemplary and not limited to the above method.
The fin structures may have the same width, or the fins may be divided into a plurality of fin structure groups having different widths, and the fin structures may have different lengths.
Isolation structures 102 are also formed on the semiconductor substrate 100, the isolation structures 102 may be Shallow Trench Isolation (STI) structures or local oxide silicon (L OCOS) isolation structures, and in the present embodiment, the isolation structures 102 are preferably shallow trench isolation structures, the top surfaces of the isolation structures 102 are lower than the top surfaces of the first fin structures 1011 and the second fin structures 1012, various well (well) structures are also formed in the semiconductor substrate 100, for example, N-type wells are formed in the PMOS region, and P-type wells are formed in the NMOS region, which are omitted for simplicity.
Next, as shown in fig. 3, a first dummy gate structure and a second dummy gate structure are formed in the PMOS region and the NMOS region respectively across a portion of the first fin structures 1011 and a portion of the second fin structures 1012.
Illustratively, the first and second dummy gate structures each include a dummy gate dielectric layer 1031 and a dummy gate material layer 1032.
It is noted that the term "cross-over" as used in the present disclosure, such as a gate structure (e.g., dummy gate structure) that crosses over a fin structure (e.g., first fin structure, second fin structure, etc.), means that the gate structure is formed on both the top surface and the side surface of a portion of the fin structure, and the gate structure is also formed on a portion of the surface of the semiconductor substrate.
In one example, as shown in fig. 2, a dummy gate dielectric layer 1031 may be deposited sequentially on the semiconductor substrate 100.
Wherein the dummy gate dielectric layer 1031 may be silicon oxide (SiO)2) Or silicon oxynitride (SiON). The dummy gate dielectric 1031 of silicon oxide material may be formed by an oxidation process known to those skilled in the art, such as furnace oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), etc. Performing a nitridation process on the silicon oxide may form silicon oxynitride, where the nitridation process may be high-temperature furnace nitridation, rapid thermal annealing nitridation, or plasma nitridation, and of course, other nitridation processes may also be used, which are not described herein again. The dummy gate dielectric layer 1031 may also be formed by other chemical vapor deposition methods, physical vapor deposition methods, and the like.
In one example, a dummy gate dielectric layer 1031 is formed on all surfaces of the exposed first fin structures 1011 and second fin structures 1012.
Next, as shown in fig. 3, a dummy gate material layer 1032 is formed on the dummy gate dielectric layer 1031, and chemical mechanical polishing is performed to obtain a flat surface.
The dummy gate material layer 1032 may be made of a semiconductor material commonly used in the art, such as polysilicon, but is not limited to one,
The dummy gate material layer may be deposited by Chemical Vapor Deposition (CVD) such as low temperature chemical vapor deposition (L TCVD), low pressure chemical vapor deposition (L PCVD), rapid thermal chemical vapor deposition (L TCVD), plasma chemical vapor deposition (PECVD), and the like, and generally similar methods such as sputtering and Physical Vapor Deposition (PVD) may be used.
The dummy gate dielectric layer 1031 and the dummy gate material layer 1032 are then patterned to form a first dummy gate structure and a second dummy gate structure. Specifically, a hard mask layer 11 is formed on the dummy gate material layer, a photoresist layer is formed on the hard mask layer 11, and then exposure and development are performed to form an opening, and then the hard mask layer 11 and the dummy gate material layer 1032 are etched using the photoresist layer as a mask.
After that, offset spacers (not shown) may be optionally formed on sidewalls of the first dummy gate structure and the second dummy gate structure.
Specifically, the offset spacer may be formed of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. As an embodiment of this embodiment, the offset spacer is composed of silicon oxide and silicon nitride, and the specific process includes: and forming a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer on the semiconductor substrate, and then forming the offset side wall by adopting an etching method. Or forming a side wall material layer on both the top surface and the side wall of the dummy gate structure, and removing the side wall material layer on the top surface through a planarization method, such as chemical mechanical polishing, in the subsequent step to form the offset side wall only on the side wall.
Subsequently, L DD ion implants are performed for the PMOS region and the NMOS region, respectively.
Among them, L DD ion implantation to form a lightly doped drain (L DD) structure in the source/drain region can reduce an electric field and can significantly improve a hot electron effect.
Illustratively, L DD ions are implanted into the first fin structures 1011 on both sides of the first dummy gate structure In the PMOS region to form a P-type lightly doped drain (L DD), and the implanted ions may be any P-type doped ions, including but not limited to boron (B) ions and indium (In) ions.
L DD ion implantation is performed on the second fin structures 1012 on both sides of the second dummy gate structure in the NMOS region to form a lightly doped N-type drain (L DD), and the implanted ions may be any suitable N-type dopant ions, including but not limited to phosphorus (P) ions and arsenic (As) ions.
Next, as shown in fig. 4, a first spacer material layer 104 is deposited to cover the PMOS region and the NMOS region.
Specifically, the first spacer material layer 104 is formed on the surface of the exposed isolation structure 102, on the top surfaces and sidewalls of the first and second dummy gate structures, and on the sidewalls and top surfaces of the first and second fin structures 1011 and 1012 at both sides of the first and second dummy gate structures.
The first spacer material layer 104 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of the present embodiment, the first spacer material layer 104 is silicon nitride.
Methods including, but not limited to: the first spacer material layer 104 is formed by a chemical vapor deposition method and a physical vapor deposition method.
Next, as shown in fig. 5, a patterned first photoresist layer 1051 is formed to cover the NMOS region and expose the PMOS region.
Specifically, the patterned first photoresist layer 1051 is formed by a photolithography process (including processes of coating photoresist, exposing and developing), and the patterned first photoresist layer 1051 exposes the first spacer material layer 104 in the PMOS region.
Subsequently, using the patterned first photoresist layer 1051 as a mask, the first spacer material layer 104 on the top surfaces of the first fin structures 1011 and on the surface of the semiconductor substrate 100 (i.e., on the surface of the isolation structure 102) is removed by etching, and the first spacer material layer 104 on the sidewalls of the first dummy gate structures and on the sidewalls of the first fin structures 1021 on both sides of the first dummy gate structures is remained.
The etching method may use any suitable dry etching or wet etching method known to those skilled in the art.
Subsequently, as shown in fig. 5, etching back removes portions of the first fin structures 1011 in the source/drain regions on both sides of the first dummy gate structure and portions of the first spacer material layer 104 on the first fin structures 1011.
The etch back may use any suitable dry or wet etching method known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Preferably, the dry etching is performed by one or more RIE steps.
Thereafter, the patterned first photoresist layer 1051 is removed. The first photoresist layer 1051 may be removed using an ashing method.
Next, as shown in fig. 6, a first stress epitaxial layer 106 is grown in the source/drain regions of the first fin structures 1011 on both sides of the first dummy gate structure.
The first stressed epitaxial layer 106 may be grown on the surface of the exposed first fin structures 1011 using a selective epitaxial growth method, which may be one of low pressure chemical vapor deposition (L PCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
The material of the first stress epitaxial layer 106 may comprise SiGe or other suitable material that can provide compressive stress. Specifically, SiGe can be grown by a chemical vapor deposition method or a gas source molecular beam epitaxy method, silane or disilane is used as a silicon source, and a certain amount of germane is added. For example, GeH is selected4And SiH2Cl2As a reaction gas and selecting H2As the carrier gas, the flow ratio of the reaction gas and the carrier gas is 0.01 to 0.1, the deposition temperature is 300-1000 ℃, preferably 650-750 ℃, and the gas pressure is 1-50Torr, preferably 20-40 Torr.
And forming a stress layer with compressive stress in the PMOS, wherein the performance of the CMOS device can be improved by applying the compressive stress to the PMOS.
Wherein, the cross-sectional shape of the first stress epitaxial layer 106 is preferably "βˆ‘".
Next, as shown in fig. 7, an oxidation process is performed to form a first oxide layer 107 on the exposed surface of the first stress epitaxial layer 106.
The first oxide layer 107 may be formed of a silicon oxide material by an oxidation process known to those skilled in the art, such as furnace oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like.
Next, continuing with fig. 7, a second spacer material layer 1081 is deposited to cover the PMOS region and the NMOS region.
The second spacer material layer 1081 may be made of the same material as the first spacer material layer 104, and the second spacer material layer 1081 may be made of one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the second spacer material layer 1081 is silicon nitride.
Methods including, but not limited to: the second spacer material layer 1081 is formed by a chemical vapor deposition method or a physical vapor deposition method.
In the PMOS region, the second spacer material layer 1081 covers the surface of the first stress epitaxial layer 106, is located above the first oxide layer 107, and forms the second spacer material layer 1081 on the sidewall of the first fin structure 1011 and the surface of the isolation structure 102 in the PMOS region.
Next, as shown in fig. 8, a patterned second photoresist layer 1052 is formed to cover the PMOS region and expose the NMOS region, and the first spacer material layer and the second spacer material layer on the top surface of the second fin structures 1012 and on the surface of the semiconductor substrate 100 in the NMOS region are etched away using the patterned second photoresist layer 1052 as a mask to form the first spacers 108 on the sidewalls of the second fin structures 1012 and expose a portion of the top surface of the second fin structures 1012.
Specifically, the patterned second photoresist layer 1052 is formed by a photolithography process (including processes of coating photoresist, exposing and developing, etc.), and the patterned second photoresist layer 1052 exposes the second spacer material layer in the NMOS region.
The first spacer material layer and the second spacer material layer on the surface of the semiconductor substrate 100 in the NMOS region are removed, that is, the first spacer material layer and the second spacer material layer on the surface of the isolation structure 102 in the NMOS region are removed.
The etching method may use any suitable dry etching or wet etching method known to those skilled in the art, and preferably, dry etching method is used.
Illustratively, the thickness of the first spacer 108 may be in a range of 60 to 120 angstroms, and the above thickness range is only an example, and other suitable ranges may be applicable to the present invention.
Next, as shown in fig. 9, a first etch back is performed to the exposed source/drain regions of the second fin structures 1012 by using the patterned second photoresist layer 1052 as a mask, so as to remove portions of the second fin structures 1012 to form first recesses 109.
In one example, the first etch-back also simultaneously removes the dummy gate dielectric layer 1031 on the sidewalls of the second fin structures 1012.
The first etch back may use any suitable dry or wet etch or combination thereof known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Preferably, the dry etching is performed by one or more RIE steps.
Thereafter, the patterned second photoresist layer 1052 is removed. The patterned second photoresist layer 1052 may be removed using an ashing method.
Illustratively, the depth of the first etch-back is in the range of 20-40 nm, i.e., the depth of the etch-back from the top surface of the second fin structure 1012 is in the range of 20-40 nm, which is only an example.
Next, as shown in fig. 10, the exposed surface of the second fin structure 1012 is oxidized to form a second oxide layer 110.
Specifically, the surface of the second fin structures 1012 exposed from the first recess 109 is oxidized to form the second oxide layer 110. The second oxide layer 110 serves as an etch stop layer for the subsequent etching of the first spacers.
The second oxide layer 110 may be formed of a silicon oxide material by an oxidation process known to those skilled in the art, such as furnace oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like.
Next, as shown in fig. 11, the thickness of the first spacer 108 is reduced to enlarge the width of the first groove 109 to the first width L1.
Illustratively, the thinning of the first spacer 108 is achieved using a wet etching method.
In one example, when the material of the first spacer 108 is silicon nitride, the wet etching may use an etchant including phosphoric acid to achieve the thinning of the first spacer 108, and the phosphoric acid may also be a hot phosphoric acid solution, which has a high etching rate for silicon nitride and a low etching rate for oxide, etc.
In the present embodiment, after the first spacer 108 is thinned, the thickness of the remaining first spacer 108 is in a range of 2 to 6nm, but not limited thereto.
It is worth mentioning that during the wet etching process to thin the first spacer 108, the second spacer material layer in the PMOS region is also etched and thinned.
The second oxide layer 110 is then removed by a preclean to expose the top surfaces of the second fin structures 1012 in the first recess 109. Illustratively, the precleaning can employ a hydrofluoric acid solution, such as a Buffered Oxide Etchant (BOE) or a buffered hydrofluoric acid solution (BHF).
Next, as shown in fig. 12, a second stressed epitaxial layer 111 is grown on the second fin structures 1012 exposed in the first recess 109 to fill the first recess, wherein the width of the second stressed epitaxial layer 111 is the first width L1.
The second stressed epitaxial layer 111 can be grown on the exposed surfaces of the second fin structures 1012 using a selective epitaxial growth method, which can be one of low pressure chemical vapor deposition (L PCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
In NMOS, the second stressed epitaxial layer 111 typically has tensile stress. The material of the second stressed epitaxial layer 111 may be SiP, SiC or other suitable material that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stressed epitaxial layer. Specifically, SiP can be grown by a chemical vapor deposition method or a gas source molecular beam epitaxy method, silane or disilane is used as a silicon source, and phosphane is used as a phosphorus source.
The top surface of the second stressed epitaxial layer 111 may also be higher than the top surface of the first spacer 108 on the sidewall thereof, and the first spacer 108 has a guiding effect on the growth of the second stressed epitaxial layer 111, controlling the growth thereof upward in the first groove between the first spacers.
The exposed surface of the second stressed epitaxial layer may also be selectively oxidized to form an oxide layer that may serve as an etch stop layer for subsequent etching of the spacer material layer.
Next, as shown in fig. 13, a third spacer material layer 1121 is deposited to cover the PMOS region and the NMOS region.
The third spacer material layer 1121 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of the present embodiment, the third spacer material layer 1121 is silicon nitride.
Methods including, but not limited to: the third spacer material layer 1121 is formed by a chemical vapor deposition method or a physical vapor deposition method.
Next, as shown in fig. 14, a patterned third photoresist layer 1053 is formed to cover the PMOS region and expose the NMOS region, and a portion of the third spacer material layer 1121 on the top surface of the second stress epitaxial layer 111 and on the semiconductor substrate 100 in the NMOS region is etched away by using the patterned third photoresist layer 1053 as a mask, so as to form the second spacers 112 on the sidewalls of the second fin structures 1012 and the second stress epitaxial layer 111.
Specifically, the patterned third photoresist layer 1053 is formed by a photolithography process (including processes of coating photoresist, exposing and developing), and the patterned third photoresist layer 1053 exposes the third spacer material layer 1121 in the NMOS region.
The third spacer material layer 1121 on the surface of the semiconductor substrate 100 in the NMOS region is removed, that is, the third spacer material layer 1121 on the surface of the isolation structure 102 in the NMOS region is removed.
The etching method may use any suitable dry etching or wet etching method known to those skilled in the art, and preferably, dry etching method is used.
In one example, when oxide is formed on the second stressed epitaxial layer 111, the oxide may also be removed to expose the top surface of the second stressed epitaxial layer 111.
Next, as shown in fig. 15, a second etch back is performed to remove a portion of the second stressed epitaxial layer 111 by using the patterned third photoresist layer 1053 as a mask, so as to form a second groove 113.
The second etch back may use any suitable dry or wet etch or combination of these methods known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Preferably, the dry etching is performed by one or more RIE steps.
Illustratively, the wet etching may use an etching method having a high etching rate for the second stressed epitaxial layer 111 and a low etching rate for the spacer and the isolation structure.
Illustratively, the depth of the second etch-back is in the range of 10 to 20nm, that is, the depth of the etch-back from the top surface of the second stressed epitaxial layer is in the range of 10 to 20nm, and this depth range is only used as an example.
Thereafter, the patterned third photoresist layer 1053 is removed. The patterned third photoresist layer 1053 may be removed using an ashing method.
Next, as shown in fig. 16, the thickness of the second spacer 112 is reduced to enlarge the width of the second groove 113 to a second width L2.
Illustratively, the thinning of the second spacer 112 is achieved using a wet etching method.
In one example, when the material of the second spacer 112 is silicon nitride, the wet etching may use an etchant including phosphoric acid to achieve the thinning of the second spacer 112, and the phosphoric acid may also be a hot phosphoric acid solution, which has a high etching rate for silicon nitride and a low etching rate for oxide, etc.
In the present embodiment, after the second spacer 112 is thinned, the thickness of the remaining second spacer 112 is in a range of 2 to 6nm, but not limited thereto.
It is worth mentioning that during the wet etching process to thin the second spacer 1128, the third spacer material layer 1121 in the PMOS region is also etched and thinned.
Next, as shown in fig. 17, a third stressed epitaxial layer 114 is grown on the surface of the second stressed epitaxial layer 111 to fill the second groove and overflow onto the top surface of the remaining second spacer 112, wherein the width of the third stressed epitaxial layer 112 in the second groove is the second width L2, and the third stressed epitaxial layer 114 above the top surface of the second spacer 112 has a third width L3, wherein the first width L1 is smaller than the second width L2, and the second width L2 is smaller than the third width L3.
It should be noted that the first width, the second width and the third width refer to widths of respective cross sections obtained by cutting the second stressed epitaxial layer and the third stressed epitaxial layer with a plane perpendicular to the surface of the semiconductor substrate and perpendicular to the extending direction of the fin structure.
The third stressed epitaxial layer 114 may be grown on the surface of the exposed second stressed epitaxial layer 111 using a selective epitaxial growth method, which may employ one of low pressure chemical vapor deposition (L PCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
In NMOS, the third stressed epitaxial layer 114 typically has tensile stress. The material of the third stressed epitaxial layer 114 may be SiP, SiC, or other suitable material that can provide tensile stress. In this embodiment, SiP is preferably selected as the third stressed epitaxial layer 114. Specifically, SiP can be grown by a chemical vapor deposition method or a gas source molecular beam epitaxy method, silane or disilane is used as a silicon source, and phosphane is used as a phosphorus source.
Wherein, when the third stressed epitaxial layer 114 is epitaxially grown, the second spacer 112 has a guiding effect on the growth of the third stressed epitaxial layer 114, and controls the growth thereof upwards in the second groove between the second spacers 112.
Through the method, the SiP stress epitaxial layer is formed in the source/drain region in the NMOS region, the stress epitaxial layer comprises a second stress epitaxial layer with a first width positioned at the bottom and a third stress epitaxial layer positioned on the second stress epitaxial layer, wherein the third stress epitaxial layer comprises a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width positioned above the top surface of the second gap wall from bottom to top, the first width is smaller than the second width, and the second width is smaller than the third width, so that the top of the stress epitaxial layer is enlarged, the contact area is larger, the stress epitaxial layer has lower external resistance, and furthermore, the short channel effect is well controlled because the volume of the bottom stress epitaxial layer is not enlarged.
Next, as shown in fig. 18, a contact hole etch stop layer 115 is formed on the surfaces of the semiconductor substrate 100, the first stressed epitaxial layer 106, the third stressed epitaxial layer 114, and the second spacer 112; an interlayer dielectric layer 116 is deposited on the contact hole etch stop layer 115, and the interlayer dielectric layer 116 is planarized.
A contact etch stop layer (CES L) 115, which may comprise a dielectric material, such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like, is formed over the substrate.
Contact hole etch stop layer 115 may comprise any two of several etch stop materials. Non-limiting examples include conductor etch stop materials, semiconductorsAn etch stop material and a dielectric etch stop material. For reasons that will become more apparent in the additional description below, the etch stop layer includes an etch stop material susceptible to localized changes that provide the etch stop layer with a region-specific etch selectivity. In the present invention, the contact hole etch stop layer 115 comprises two layers, an oxide layer contained therein and a nitride layer outside the oxide layer, wherein the oxide may be selected from SiO2The nitride may be selected from one of SiCN, SiN, SiC, SiOF, SiON, but the contact hole etching stopper layer is not limited to the above examples.
An interlevel dielectric layer 116 is then deposited and planarized. Non-limiting examples of the planarization process include a mechanical planarization method and a Chemical Mechanical Polishing (CMP) planarization method.
The interlayer dielectric layer 116 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.
Thus, the introduction of the main steps of the method for manufacturing a semiconductor device of the present invention is completed, and other previous steps, intermediate steps or subsequent steps are required for the fabrication of the complete device, which is not described in detail herein.
According to the manufacturing method, the spacer is used as a guide when the stress epitaxial layer grows in the source/drain region of the NMOS region, so that a merged epitaxial layer (merged epitoxy) cannot be formed, in addition, the top of the stress epitaxial layer is enlarged, so that the contact area is larger, the stress epitaxial layer has lower external resistance, and in addition, the volume of the bottom stress epitaxial layer is not basically enlarged, so that the short channel effect is well controlled, therefore, according to the manufacturing method, the volume and the profile of the source/drain stress epitaxial layer are reasonably balanced, and the performance and the yield of the device are improved.
Example two
The invention also provides a semiconductor device prepared by using the method in the first embodiment.
Specifically, as shown in fig. 17 and 18, the semiconductor device of the present invention includes a semiconductor substrate 100, wherein the semiconductor substrate 100 includes a PMOS region and an NMOS region, and a first fin structure 1011 and a second fin structure 1012 are formed on the semiconductor substrate 100 in the PMOS region and the NMOS region, respectively.
Specifically, the semiconductor substrate 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. In the present embodiment, the semiconductor substrate 100 is preferably a silicon substrate.
First fin structures 1011 are formed on the semiconductor substrate 100 in the PMOS region and second fin structures 1012 are formed on the semiconductor substrate 100 in each of the NMOS regions.
In one example, a method of forming the first fin structures 1011 and the second fin structures 1012 includes the steps of:
forming a patterned mask layer on the surface of the semiconductor substrate 100, where the patterned mask layer defines patterns of the first fin structure 1011 and the second fin structure 1012, including width, length, and position of a fin; the semiconductor substrate 100 is etched using the patterned mask layer as a mask to form the first fin structures 1011 and the second fin structures 1012. The mask layer may generally comprise any of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. The etching may be performed by dry etching, wet etching, or the like, wherein the dry etching process may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
It is noted that the method of forming the first fin structures 1011 and the second fin structures 1012 is merely exemplary and not limited to the above method.
The fin structures may have the same width, or the fins may be divided into a plurality of fin structure groups having different widths, and the fin structures may have different lengths.
Isolation structures 102 are also formed on the semiconductor substrate 100, the isolation structures 102 may be Shallow Trench Isolation (STI) structures or local oxide silicon (L OCOS) isolation structures, and in the present embodiment, the isolation structures 102 are preferably shallow trench isolation structures, the top surfaces of the isolation structures 102 are lower than the top surfaces of the first fin structures 1011 and the second fin structures 1012, various well (well) structures are also formed in the semiconductor substrate 100, for example, N-type wells are formed in the PMOS region, and P-type wells are formed in the NMOS region, which are omitted for simplicity.
Further, a first gate structure and a second gate structure are formed in the PMOS region and the NMOS region, respectively, and cross over a portion of the first fin structure 1011 and a portion of the second fin structure 1012.
The first gate structure and the second gate structure each include a gate dielectric layer 1031 and a gate layer 1032 from bottom to top.
Gate dielectric 1031 the gate dielectric may be formed by a thermal oxidation, nitridation or oxynitridation process. The above processes may also be used in combination when forming the gate dielectric layer. The gate dielectric layer may comprise any conventional dielectric as follows: SiO 22、Si3N4、SiON、SiON2Such as TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3And other similar oxides including perovskite-type oxides, but are not limited thereto. Typically, high k dielectrics can withstand a high temperature (900 ℃) anneal. The gate dielectric layer may also comprise any combination of the above-described dielectric materials.
Gate layer 1032 is formed on gate dielectric 1031. In one embodiment, the gate layer is made of polysilicon material, and metal, metal nitride, metal silicide or similar compounds can be used as the material of the gate layer.
In one example, a first stress epitaxial layer 106 is formed in the source/drain region of the first fin structure 1011 on both sides of the first gate structure, a first oxide layer 107 is further formed on the surface of the first stress epitaxial layer 106, and a gap wall material layer 1121 is formed on the surface of the first oxide layer 107, on the sidewall of the first fin structure 1011, and on the surface of the semiconductor substrate 100 in the PMOS region.
The material of the first stress epitaxial layer 106 may comprise SiGe or other suitable material that can provide compressive stress.
And forming a stress layer with compressive stress in the PMOS, wherein the performance of the CMOS device can be improved by applying the compressive stress to the PMOS.
Wherein, the cross-sectional shape of the first stress epitaxial layer 106 is preferably "βˆ‘".
Illustratively, the first oxide layer 107 is silicon oxide formed using a method of oxidation treatment.
The spacer material layer 1121 may be made of one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the gap wall material layer 1121 is silicon nitride.
Further, the semiconductor device of the present invention further includes a second stressed epitaxial layer 111 with a first width L1, a third stressed epitaxial layer 114 with a second width L2, and the third stressed epitaxial layer 114 with a third width L3 formed from bottom to top in the source/drain regions of the second fin structures 1012 on both sides of the second gate structure, wherein the first width L1 is smaller than the second width L2, the second width L2 is smaller than the third width L3, and a gap wall 112 is formed on the sidewalls of the second fin structures 1012, the second stressed epitaxial layer 111, and the third stressed epitaxial layer 114 with the second width.
The spacers 112 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment of the present invention, the spacer 112 is silicon nitride.
In NMOS, the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 typically have tensile stress. The material of the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 may be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114. Specifically, SiP can be grown by a chemical vapor deposition method or a gas source molecular beam epitaxy method, silane or disilane is used as a silicon source, and phosphane is used as a phosphorus source.
Illustratively, the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 may also be different materials having tensile stress.
The semiconductor device of the invention forms a SiP stress epitaxial layer in a source/drain region in an NMOS region, the stress epitaxial layer comprises a second stress epitaxial layer with a first width positioned at the bottom and a third stress epitaxial layer positioned on the second stress epitaxial layer, wherein the third stress epitaxial layer comprises a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width positioned above the top surface of a second gap wall from bottom to top, the first width is smaller than the second width, and the second width is smaller than the third width, so that the top of the stress epitaxial layer is enlarged, the contact area is larger, the stress epitaxial layer has lower external resistance, and furthermore, the short channel effect is well controlled because the volume of the bottom stress epitaxial layer is not enlarged.
Further, a contact hole etch stop layer 115 is formed on the surfaces of the semiconductor substrate 100, the first stressed epitaxial layer 106, the third stressed epitaxial layer 114 and the spacer 112; an interlayer dielectric layer 116 is deposited on the contact hole etch stop layer 115.
A contact etch stop layer (CES L) 115, which may comprise a dielectric material, such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like, is formed over the substrate.
The contact hole etch stop layer 115 may includeAny two of several etch stop materials. Non-limiting examples include conductive etch stop materials, semiconductor etch stop materials, and dielectric etch stop materials. For reasons that will become more apparent in the additional description below, the etch stop layer includes an etch stop material susceptible to localized changes that provide the etch stop layer with a region-specific etch selectivity. In the present invention, the contact hole etch stop layer 115 comprises two layers, an oxide layer contained therein and a nitride layer outside the oxide layer, wherein the oxide may be selected from SiO2The nitride may be selected from one of SiCN, SiN, SiC, SiOF, SiON, but the contact hole etching stopper layer is not limited to the above examples.
The interlayer dielectric layer 116 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.
For the complete device, other structural components are also included, and are not described in detail herein.
The semiconductor device of the invention is prepared by the method, so that the semiconductor device has the same advantages.
The semiconductor device of the invention uses the gap wall as a guide when a stress epitaxial layer grows in a source/drain region of an NMOS region, so that a merged epitaxial layer (merged epitoxy) cannot be formed, in addition, because the semiconductor device of the invention comprises the top of the expanded stress epitaxial layer, the contact area is larger, so that the stress epitaxial layer has lower external resistance, in addition, because the volume of the bottom stress epitaxial layer is not basically increased, the short channel effect is well controlled, the volume and the outline of the source/drain stress epitaxial layer are reasonably balanced, and therefore, the performance of the semiconductor device is higher.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device described in the second embodiment, wherein the semiconductor device is prepared according to the method described in the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.
Among them, fig. 20 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the semiconductor device of embodiment two, the semiconductor device mainly comprising:
the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;
forming a first gate structure and a second gate structure respectively crossing part of the first fin structure and part of the second fin structure in the PMOS region and the NMOS region;
forming a first stress epitaxial layer in the source/drain regions of the first fin structures at two sides of the first gate structure;
a second stress epitaxial layer with a first width, a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width are formed in the source-drain regions of the second fin structures on two sides of the second gate structure from bottom to top, wherein the first width is smaller than the second width, and the second width is smaller than the third width;
and forming gap walls on the side walls of the second fin structure, the second stress epitaxial layer and the third stress epitaxial layer with the second width.
The electronic device of the present invention includes the aforementioned semiconductor device, and therefore has the same advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (23)

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;
forming a first dummy gate structure and a second dummy gate structure respectively crossing a portion of the first fin structure and a portion of the second fin structure in the PMOS region and the NMOS region;
growing a first stress epitaxial layer in the source/drain regions of the first fin structures on two sides of the first dummy gate structure;
forming first gap walls on the side walls of the second fin structures at two sides of the second dummy gate structure;
performing first back etching on the exposed source/drain regions of the second fin structures to remove part of the second fin structures to form first grooves;
thinning the thickness of the first gap wall to enlarge the width of the first groove to a first width;
growing a second stress epitaxial layer on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stress epitaxial layer is the first width;
forming second spacer walls on the second fin structures and the side walls of the second stress epitaxial layer;
a second etching back step is carried out to remove part of the second stress epitaxial layer so as to form a second groove;
thinning the thickness of the second gap wall to enlarge the width of the second groove to a second width;
and growing a third stress epitaxial layer on the surface of the second stress epitaxial layer to fill the second groove and overflow to the top surface of the rest second gap wall, wherein the width of the third stress epitaxial layer in the second groove is the second width, and the third stress epitaxial layer above the top surface of the second gap wall has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising, after forming the first dummy gate structure and the second dummy gate structure and before forming the first stress epitaxial layer, the steps of:
depositing a first spacer material layer to cover the PMOS region and the NMOS region;
forming a patterned first photoresist layer to cover the NMOS region and expose the PMOS region;
etching and removing a part of the first spacer material layer on the top surface of the first fin structure and on the surface of the semiconductor substrate by taking the patterned first photoresist layer as a mask;
and etching back to remove a part of the first fin structure in the source/drain regions at two sides of the first dummy gate structure and a part of the first spacer material layer on the first fin structure.
3. The method of manufacturing of claim 1 or 2, wherein after forming the first stressed epitaxial layer and before forming the first spacer, further comprising the steps of: and carrying out oxidation treatment to form a first oxide layer on the exposed surface of the first stress epitaxial layer.
4. The method of manufacturing according to claim 2, wherein the method of forming the first spacer comprises the steps of:
depositing a second spacer material layer to cover the PMOS region and the NMOS region;
forming a patterned second photoresist layer to cover the PMOS region and expose the NMOS region;
and etching and removing the first gap wall material layer and the second gap wall material layer on the top surface of the second fin structure and the surface of the semiconductor substrate in the NMOS area so as to form the first gap wall on the side wall of the second fin structure and expose part of the top surface of the second fin structure.
5. The method of manufacturing of claim 1, wherein after the first etch-back step, before thinning the thickness of the first spacer, further comprising the steps of: and oxidizing the exposed surface of the second fin structure to form a second oxide layer, and after the step of thinning the thickness of the second spacer, pre-cleaning and removing the second oxide layer.
6. The manufacturing method according to claim 1, wherein the process of forming the second spacer includes the steps of:
depositing a third spacer material layer to cover the PMOS region and the NMOS region;
forming a patterned third photoresist layer to cover the PMOS region and expose the NMOS region;
and etching and removing part of the third spacer material layer on the top surface of the second stress epitaxial layer and the semiconductor substrate in the NMOS region so as to form the second spacers on the second fin structures and the side walls of the second stress epitaxial layer.
7. The method of claim 1, wherein the first spacer has a thickness in a range of 60 to 120 angstroms.
8. The method according to claim 1, wherein the depth of the first etch-back is in a range of 20nm to 40 nm.
9. The method according to claim 1, wherein a thickness of the first spacer remaining after the thinning of the first spacer is in a range of 2 to 6 nm.
10. The method according to claim 1, wherein a thickness of the second spacer remaining after the thinning of the second spacer is in a range of 2 to 6 nm.
11. The manufacturing method according to claim 1, wherein a depth of the second etch-back is in a range of 10 to 20 nm.
12. The method of manufacturing of claim 1 wherein the material of the second stressed epitaxial layer and the third stressed epitaxial layer each comprise SiP.
13. The manufacturing method according to claim 1, wherein the thinning of the first spacer and the thinning of the second spacer are achieved using a wet etching method.
14. The manufacturing method according to claim 13, wherein the wet etching uses an etchant including phosphoric acid.
15. The method of manufacturing of claim 1, further comprising:
forming a contact hole etching stop layer on the surfaces of the semiconductor substrate, the first stress epitaxial layer, the third stress epitaxial layer and the second gap wall;
and depositing an interlayer dielectric layer on the contact hole etching stop layer, and flattening the interlayer dielectric layer.
16. The method of manufacturing of claim 1, wherein the material of the first stressed epitaxial layer comprises SiGe.
17. A semiconductor device, comprising:
the semiconductor substrate comprises a PMOS area and an NMOS area, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS area and the NMOS area;
forming a first gate structure and a second gate structure respectively crossing a part of the first fin structure and a part of the second fin structure in the PMOS region and the NMOS region;
forming a first stress epitaxial layer in the source/drain regions of the first fin structures on two sides of the first gate structure;
a second stress epitaxial layer with a first width, a third stress epitaxial layer with a second width and a third stress epitaxial layer with a third width are formed in the source-drain regions of the second fin structures on two sides of the second gate structure from bottom to top, wherein the first width is smaller than the second width, the second width is smaller than the third width, and the first width is larger than the width of the second fin structures;
and forming gap walls on the side walls of the second fin structure, the second stress epitaxial layer and the third stress epitaxial layer with the second width.
18. The semiconductor device of claim 17, wherein a first oxide layer is also formed on a surface of the first stress epitaxial layer.
19. The semiconductor device of claim 18, wherein a layer of spacer material is formed on a surface of the first oxide layer, on sidewalls of the first fin structures, and on a surface of the semiconductor substrate within the PMOS region.
20. The semiconductor device of claim 17, wherein the material of the second stressed epitaxial layer and the third stressed epitaxial layer each comprises SiP.
21. The semiconductor device according to claim 17, further comprising:
forming a contact hole etching stop layer on the surfaces of the semiconductor substrate, the first stress epitaxial layer, the third stress epitaxial layer and the gap wall;
an interlayer dielectric layer is deposited on the contact hole etching stop layer.
22. The semiconductor device of claim 17, the material of the first stressed epitaxial layer comprising SiGe.
23. An electronic device comprising the semiconductor device according to any one of claims 17 to 22.
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CN107919326A (en) * 2016-10-10 2018-04-17 δΈ­θŠ―ε›½ι™…ι›†ζˆη”΅θ·―εˆΆι€ (上桷)ζœ‰ι™ε…¬εΈ Fin field effect pipe and forming method thereof

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