CN107644815B

CN107644815B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN107644815B
Application number: CN201610578207.6A
Authority: CN
Inventors: 周飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Zhongxin Nanfang integrated circuit manufacturing Co.,Ltd.; Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-07-21
Filing date: 2016-07-21
Publication date: 2021-04-23
Anticipated expiration: 2036-07-21
Also published as: CN107644815A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: taking the patterned mask layer exposing the part of the first dummy gate structure positioned above the second well region as a mask, and performing ion implantation of first conductive type impurities on the exposed first dummy gate material layer; removing the second dummy gate material layer and part of the first dummy gate material layer; removing the second pseudo gate dielectric layer and part of the first pseudo gate dielectric layer to form a first gate groove and a second gate groove which are respectively positioned in the I/O device area and the core device area, wherein the rest first pseudo gate dielectric layer is in a step shape; a metal gate structure is formed in the first gate trench and the second gate trench. According to the method, the step-type pseudo gate dielectric layer is formed in the I/O device area of the FinFET device, so that the breakdown voltage of the device is enhanced, and the overall performance of the device is improved.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

With the continuous development of semiconductor technology, lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) devices are widely used in power integrated circuits due to their good short channel characteristics. LDMOS devices are well suited for applications in RF (radio frequency) base station and power MOSFET (metal oxide semiconductor field effect transistor) switching. In the application of RF technology, LDMOS devices are mainly applied in base station circuits due to their high power performance, high gain, excellent linearity and low manufacturing cost. In power MOSFET applications, such as DC-CD converters, LDMOS devices have excellent switching performance and can reduce switching losses compared to other power conversion devices. Therefore, the LDMOS technology brings higher power peak-to-average ratio, higher gain and linearity for the new generation of base station amplifier, and simultaneously brings higher data transmission rate for multimedia services.

Since LDMOS devices are commonly used in power circuits, such as RF technology and power MOSFETs, which require high voltage power amplification and large output power, LDMOS devices must be able to withstand high voltages. With the wide application of the LDMOS to the power integrated circuit, the requirements for the performance of the LDMOS device are higher and higher, and the requirement for the breakdown voltage of the LDMOS device is higher, and the threshold shift and the good performance may also be required to be increased. The existing LDMOS device is difficult to meet the requirement of higher breakdown voltage.

As device dimensions continue to shrink, challenges from manufacturing and design aspects have prompted the development of three-dimensional designs such as fin structure field effect transistors (finfets). Compared with the existing planar transistor, the FinFET is an advanced semiconductor device for process nodes of 20nm and below, can effectively control the short channel effect which is difficult to overcome due to the fact that the device is scaled down, can also effectively improve the density of a transistor array formed on a substrate, and meanwhile, a grid electrode in the FinFET is arranged around a fin structure (a fin-shaped channel), so that static electricity can be controlled from three surfaces, and the performance in the aspect of static electricity control is more outstanding.

In the manufacturing process of the FinFET, the LDMOS device is generally converted from a planar device to a device with a fin structure, and after the LDMOS planar process is converted to the FinFET process, the breakdown voltage of the LDMOS device is reduced. For LDMOS devices, and LDNMOS devices in particular, gate oxide breakdown is one of the important factors that limit the overall Breakdown Voltage (BVDs) of the device.

Therefore, how to increase the breakdown voltage of the LDMOS device in the FinFET process to further improve the device performance is an urgent problem to be solved.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the deficiencies of the prior art, a first embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises an I/O device area and a core device area, and a first well region with a first conduction type and a second well region with a second conduction type are formed in the semiconductor substrate in the I/O device area;

forming a first fin structure and a second fin structure on the semiconductor substrate, wherein the first fin structure and the second fin structure are respectively located in the I/O device area and the core device area, and the first fin structure is partially located on the first well region and partially located on the second well region;

forming an isolation structure on the semiconductor substrate outside the first fin structure and the second fin structure, wherein the top surface of the isolation structure is lower than the top surfaces of the first fin structure and the second fin structure;

forming a first dummy gate structure crossing a part of the first fin structures and a second dummy gate structure crossing the second fin structures, wherein the first dummy gate structure comprises a first dummy gate dielectric layer and a first dummy gate material layer which are stacked from bottom to top, the first dummy gate structure covers a first edge of the first fin structures on the second well region and extends outwards to a part of the isolation structure outside the first edge, and the second dummy gate structure comprises a second dummy gate dielectric layer and a second dummy gate material layer which are stacked from bottom to top;

forming an interlayer dielectric layer on the semiconductor substrate to expose top surfaces of the first dummy gate structure and the second dummy gate structure;

forming a patterned mask layer on the interlayer dielectric layer, a part of the first dummy gate structure and the second dummy gate structure, wherein the patterned mask layer exposes a part of the first dummy gate structure above the second well region;

performing ion implantation of first conductive type impurities on the exposed first dummy gate material layer by taking the mask layer as a mask;

removing the second dummy gate material layer and a part of the first dummy gate material layer, wherein the part of the first dummy gate material layer located on the first well region is completely removed, and a part of the first dummy gate material layer doped with the first conductive type impurities located on the second well region is remained;

removing the second dummy gate dielectric layer and part of the first dummy gate dielectric layer by taking the remaining first dummy gate material layer as a mask to form a first gate trench and a second gate trench which are respectively positioned in the I/O device area and the core device area, wherein the remaining first dummy gate dielectric layer is of a step type;

forming a metal gate structure in the first and second gate trenches.

Further, before forming the first fin structures and the second fin structures, a step of forming a third well region having the first conductivity type in the semiconductor substrate in the core device region is also included.

Further, the second fin structure is formed on the third well region.

Further, the thickness of the first dummy gate dielectric layer is greater than the thickness of the second dummy gate dielectric layer.

Further, when the first fin structure and the second fin structure are formed, the method further includes: and forming a third fin structure on the semiconductor substrate and on the second well region, wherein the third fin structure and the first fin structure are arranged at intervals.

Further, after forming the first dummy gate structure and before forming the interlayer dielectric layer, forming a source in a portion of the first fin structure above the first well region and forming a drain in the third fin structure, wherein the source and the drain have a second conductivity type.

Further, before forming the source and the drain, a step of forming a side wall on the side wall of the first dummy gate structure is included.

Further, the step of forming the metal gate structure includes:

sequentially forming a high-K dielectric layer and a work function layer on the bottom and the side wall of the first gate groove and the second gate groove;

and filling gate electrode layers in the first gate trench and the second gate trench.

Further, before forming the high-k dielectric layer, a step of forming an interface layer at the bottom of the first gate trench and the second gate trench is further included.

Further, in the first gate trench, the remaining first dummy gate material layer is amorphous silicon.

Further, the second dummy gate material layer and a part of the first dummy gate material layer are removed by wet etching.

Further, a tetramethyl ammonium hydroxide solution is adopted as the etching solution for the wet etching.

Further, the first conductive type is a P type, and the second conductive type is an N type, or the first conductive type is an N type, and the second conductive type is a P type.

Further, the first conductive type impurity includes boron.

Another aspect of the present invention provides a semiconductor device, including:

the semiconductor device comprises a semiconductor substrate, a first control circuit and a second control circuit, wherein the semiconductor substrate comprises an I/O device area, and a first well region with a first conduction type and a second well region with a second conduction type are arranged in the semiconductor substrate in the I/O device area;

forming a first fin structure located in the I/O device region on the semiconductor substrate, wherein the first fin structure is partially located on the first well region and partially located on the second well region;

an isolation structure is arranged on the semiconductor substrate outside the first fin structure, and the top surface of the isolation structure is lower than that of the first fin structure;

a dummy gate dielectric layer crossing over a portion of the first fin structures, wherein the dummy gate dielectric layer is located on a portion of the first fin structures above the first well region and the second well region, covers a first edge of the first fin structures above the second well region, and extends outward to a portion of the isolation structures outside the first edge;

a dummy gate material layer is arranged on part of the dummy gate dielectric layer, the dummy gate material layer is doped with impurities of a first conductivity type, the dummy gate material layer is arranged on part of the second well region, covers the first edge of the first fin structure on the second well region and extends outwards to the part of the isolation structure outside the first edge,

the thickness of the pseudo gate dielectric layer covered by the pseudo gate material layer is larger than that of the rest part of the pseudo gate dielectric layer, so that the pseudo gate dielectric layer is in a step shape;

and arranging a first metal gate structure crossing part of the first fin structures on the dummy gate dielectric layer, wherein part of the first metal gate structure is positioned on the dummy gate material layer.

Further, the semiconductor substrate further comprises a core device region, a second fin structure is arranged on the semiconductor substrate in the core device region, and a second metal gate structure crossing the second fin structure is arranged on the second fin structure.

Further, an interlayer dielectric layer is formed on the surface of the semiconductor substrate, the first metal gate structure is located in the interlayer dielectric layer, and the top surface of the interlayer dielectric layer is flush with the top surface of the first metal gate structure.

Further, a third fin structure located on the second well region is disposed on the semiconductor substrate, wherein the third fin structure and the first fin structure are disposed at an interval.

Further, a source is formed in a portion of the first fin structures that are above the first well region and a drain is formed in the third fin structures, wherein the source and the drain are of a second conductivity type.

Further, the first metal gate structure includes a high-k dielectric layer, a work function layer, and a gate electrode layer, which are sequentially stacked.

Furthermore, side walls are arranged on two side walls of the first metal gate structure, wherein the side walls close to the pseudo gate material layer are positioned on the isolation structure.

Further, the first conductive type impurity includes boron.

Further, the material of the dummy gate material layer is amorphous silicon.

In another aspect, the present invention provides an electronic device including the semiconductor device.

According to the manufacturing method of the invention, the step-type pseudo gate dielectric layer is formed in the I/O device region (namely LDMOS device region) of the FinFET device, and the thicker pseudo gate dielectric layer is reserved in the extension region (namely the region of the first fin structure corresponding to the second well region) of the LDMOS device region, so that the breakdown voltage of the device is enhanced, and the overall performance of the device is improved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIGS. 1A-1C are schematic diagrams illustrating a conventional LDMOS device structure of a FinFET, wherein FIG. 1A is a top view and FIGS. 1B and 1C are cross-sectional views;

fig. 2A to 2F are cross-sectional views showing structures formed at steps relevant to a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 3 shows a schematic flow chart of a method of manufacturing a semiconductor device of an embodiment of the present invention;

FIG. 4 illustrates a cross-sectional view of an LDMOS device of a FinFET in accordance with an embodiment of the present invention;

fig. 5 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Fig. 1A is a schematic top view of an LDMOS device of a FinFET manufactured according to the prior art, and fig. 1B is a schematic cross-sectional structure of the LDMOS device of the FinFET obtained by cross-section along a section line in fig. 1A. As shown in fig. 1A and fig. 1B, taking an NLDMOS device as an example, an LDMOS device of a FinFET includes a semiconductor substrate 100, a P-well (PW) and an N-well (NW) are disposed in the semiconductor substrate 100, a first fin structure 1011 is disposed on the semiconductor substrate 100, wherein the first fin structure is partially disposed on the P-well and partially disposed on the N-well, a second fin structure 1012 spaced apart from the first fin structure 1011, a gate structure 102 crossing the first fin structure 1011, and the gate structure 102 covers an edge of the first fin structure 1011 and extends to a portion of a shallow trench isolation Structure (STI), the gate structure 102 includes a dummy gate dielectric layer (i.e., gate oxide) 1021 and a gate material layer 1022 disposed on the dummy gate dielectric layer 1021, the gate material layer 1022 is a polysilicon layer, a source electrode 1031 is formed in the first fin structure 1011 not covered by the gate structure 102, a drain 1032 is formed in the second fin structure 1012, as shown in fig. 1C, another P-well is also formed in the semiconductor substrate 100 on one side of the drain, another gate structure 104 is also disposed on the P-well, and another source 1033 is formed in the P-well, and metal interconnection structures can be patterned on the source, the drain, and the gate to extract the source, the drain, and the gate, respectively.

When the LDMOS device is structurally designed, the polysilicon gate stack on the STI region is very important for enhancing the breakdown characteristic of gate oxide, but in the LDMOS device of the FinFET, the oxide in the shallow trench isolation Structure (STI) is recessed in the STI regions at the source and drain sides, and the gate oxide at the bottom of the STI is easily broken down, so that the Breakdown Voltage (BVDs) performance of the LDMOS device is reduced, and the overall performance of the LDMOS device is further influenced.

Example one

In view of the above problems, the present invention proposes a method for manufacturing a semiconductor device, as shown in fig. 3, the method comprising the following main steps:

in step S301, a semiconductor substrate is provided, the semiconductor substrate includes an I/O device region and a core device region, a first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor substrate within the I/O device region;

in step S302, a first fin structure and a second fin structure respectively located in the I/O device region and the core device region are formed on the semiconductor substrate, wherein the first fin structure is partially located on the first well region and partially located on the second well region;

in step S303, forming an isolation structure on the semiconductor substrate outside the first fin structure and the second fin structure, wherein a top surface of the isolation structure is lower than top surfaces of the first fin structure and the second fin structure;

in step S304, forming a first dummy gate structure crossing over a portion of the first fin structures and a second dummy gate structure crossing over the second fin structures, wherein the first dummy gate structure includes a first dummy gate dielectric layer and a first dummy gate material layer stacked from bottom to top, the first dummy gate structure covers a first edge of the first fin structures on the second well region and extends outward to a portion of the isolation structure outside the first edge, and the second dummy gate structure includes a second dummy gate dielectric layer and a second dummy gate material layer stacked from bottom to top;

in step S305, forming an interlayer dielectric layer on the semiconductor substrate to expose top surfaces of the first dummy gate structure and the second dummy gate structure;

in step S306, a patterned mask layer is formed on the interlayer dielectric layer, a portion of the first dummy gate structure and the second dummy gate structure, and the patterned mask layer exposes a portion of the first dummy gate structure above the second well region;

in step S307, ion implantation of a first conductive type impurity is performed on the exposed first dummy gate material layer with the mask layer as a mask;

in step S308, removing the second dummy gate material layer and a portion of the first dummy gate material layer, wherein a portion of the first dummy gate material layer located over the first well region is completely removed, and a portion of the first dummy gate material layer doped with the first conductivity-type impurities located over the second well region remains;

in step S309, removing the second dummy gate dielectric layer and a portion of the first dummy gate dielectric layer by using the remaining first dummy gate material layer as a mask to form a first gate trench and a second gate trench respectively located in the I/O device region and the core device region, wherein the remaining first dummy gate dielectric layer is step-shaped;

in step S310, a metal gate structure is formed in the first gate trench and the second gate trench.

According to the manufacturing method, the step-type pseudo gate dielectric layer is formed in the I/O device region (namely LDMOS device region) of the FinFET device, so that the breakdown voltage of the device is enhanced, and the overall performance of the device is improved.

A method for manufacturing a semiconductor device according to an embodiment of the present invention is described below with reference to fig. 2A to 2F, where fig. 2A to 2F are cross-sectional views of structures formed in steps related to the method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in fig. 2A, a semiconductor substrate 200 is provided, the semiconductor substrate 200 includes an I/O device region 10 (input/output device region) and a CORE device region (CORE), a first well region 2011 having a first conductivity type and a second well region 2012 having a second conductivity type are formed in the semiconductor substrate 200 within the I/O device region 10.

The semiconductor substrate 200 may be at least one of the following materials in this step: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment, the semiconductor substrate 200 is a silicon substrate.

It should be noted that the first conductivity type is P-type, the second conductivity type is N-type, or the first conductivity type may be N-type and the second conductivity type is P-type, which are reasonably set according to the type of the device to be manufactured, for example, for an NLDMOS device, the first conductivity type is P-type and the second conductivity type is N-type.

In this embodiment, I/O device region 10 comprises an LDMOS device region where an LDMOS device may be formed.

In which various types of well regions may be formed in the semiconductor substrate 200 by ion implantation, in one example, the first conductivity type is P-type, and the second conductivity type is N-type, P-well regions may be formed by ion implantation of P-type impurities, such as boron, etc., into the semiconductor substrate 200, and N-well regions may be formed by ion implantation of N-type impurities, such as phosphorus, arsenic, etc., into the semiconductor substrate 200.

Illustratively, the depth of the first well region 2011 and the second well region 2022 is greater than the height of the fin structure to be formed, and is set appropriately according to the requirements of the actual device.

Still further, as shown in fig. 2D, forming a third well region 2013 having the first conductivity type in the semiconductor substrate 200 in the core device region 20 is further included, for example, the third well region 2013 may be a P-well region.

Next, with continued reference to fig. 2A and 2D, a first fin structure 2021 and a second fin structure 2022 respectively located in the I/O device region 10 and the core device region 20 are formed on the semiconductor substrate 200, wherein the first fin structure 2021 is partially located on the first well region 2011 and partially located on the second well region 2012.

In one example, a step of simultaneously forming a third fin structure 2023 on the second well region 2012 on the semiconductor substrate 200 is further included, wherein the third fin structure 2023 is spaced apart from the first fin structure 2021.

The fin structures may be formed on the semiconductor substrate at the same time, and the width and length of the fin structures may be all the same or the fin structures may be divided into a plurality of fin structure groups having different widths and lengths. The fin structure is a plurality of strip-shaped structures formed on the semiconductor substrate 200.

Specifically, the forming method of the first fin structures 2021, the second fin structures 2022, and the third fin structures 2023 is not limited to a certain one, and an exemplary forming method is given below: forming a hard mask layer (not shown) on the semiconductor substrate 200, wherein the hard mask layer may be formed by using various suitable processes, such as a chemical vapor deposition process, which are well known to those skilled in the art, and the hard mask layer may be a bottom-up stacked oxide layer and a silicon nitride layer; patterning the hard mask layer, forming a plurality of mutually isolated masks for etching the semiconductor substrate to form fin structures thereon, wherein the patterned hard mask layer defines a width, a length, a position and the like including the fin structures; in one embodiment, the patterning process is performed using a self-aligned double patterning (SADP) process; the semiconductor substrate 200 is etched by using the patterned hard mask layer as a mask to form the first fin structure 2021, the second fin structure 2022, and the third fin structure 2023 thereon, which may be performed by dry etching or wet etching, wherein the dry etching process may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination thereof. A single etching method may also be used, or more than one etching method may also be used.

The first fin structures 2021 are partially located on the first well region 2011, partially located on the second well region 2012, and the third fin structures 2023 are located on the second well region 2012, so that the correspondingly formed first fin structures 2021 include portions having the same conductivity type as the first well region 2011 and portions having the same conductivity type as the second well region 2012 since various well regions are already formed in the semiconductor substrate 200 before the first fin structures 2021, the second fin structures 2022, and the third fin structures 2023 are formed, the third fin structures 2023 have the same conductivity type as the second well region 2012, and the second fin structures 2022 have the same conductivity type as the third well region 2013.

Next, as shown in fig. 2A, an isolation structure 204 is formed on the semiconductor substrate outside the first fin structures 2021 and the second fin structures 2022, and a top surface of the isolation structure 202 is lower than top surfaces of the first fin structures 2021 and the second fin structures 2022.

Specifically, a layer of spacer material is deposited to completely fill the gaps between all fin structures on the semiconductor substrate. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer may be selected from oxides, such as High Aspect Ratio Process (HARP) oxide, and may specifically be silicon oxide.

The layer of spacer material is then etched back to the target height of the fin structures (first fin structure, second fin structure) to form the spacer structures 204. Specifically, the isolation material layer is etched back to expose a part of the fin structure, so as to form the fin structure with a specific height.

With continued reference to fig. 2A and 2D, a first dummy gate structure 203 spanning a portion of the first fin structure 2021 and a second dummy gate structure spanning the second fin structure 2022 are formed, wherein the first dummy gate structure 203 includes a first dummy gate dielectric layer 2031 and a first dummy gate material layer 2032 stacked from bottom to top, the first dummy gate structure 203 covers a first edge of the first fin structure 2021 on the second well region 2012 and extends outward to a portion of the isolation structure 204 outside the first edge, and the second dummy gate structure includes a second dummy gate dielectric layer 2081 and a second dummy gate material layer stacked from bottom to top.

It is noted that the term "cross over" as used in the present invention, such as a dummy gate structure that crosses over a fin structure (e.g., a first fin structure, a second fin structure, etc.), means that the dummy gate structure is formed on both the top surface and the side surface of a portion of the fin structure, and the dummy gate structure is also formed on a portion of the surface of the semiconductor substrate. The explanation here for "cross-over" applies equally to the metal gate structures, etc., that cross over the fin structures mentioned below.

In one example, a dummy gate dielectric layer and a dummy gate material layer may be deposited sequentially on a semiconductor substrate.

The dummy gate dielectric layer can be made of common oxide, such as SiO₂The dummy gate material layer may be made of a semiconductor material commonly used in the art, such as polysilicon, etc., but is not limited to one of them,

The deposition method of the dummy gate material layer can be chemical vapor deposition or atomic layer deposition.

The dummy gate dielectric layer and the dummy gate material layer are then patterned to form the first dummy gate structure 203 and a second dummy gate structure. Specifically, a photoresist layer is formed on the dummy gate material layer, and then exposed and developed to form an opening, and then the dummy gate material layer is etched using the photoresist layer as a mask.

Then, optionally, a Spacer (Spacer)2033 is formed on the sidewalls of the first dummy gate structure 203 and the second dummy gate structure.

Specifically, the sidewall 2033 may be made of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. As an embodiment of this embodiment, the sidewall is formed by silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer are formed over the semiconductor substrate, and then the spacers 2033 are formed by an etching method. Alternatively, the sidewall material layer may be formed on both the top surfaces and the sidewalls of the first dummy gate structure 203 and the second dummy gate structure, and in a subsequent step, the sidewall material layer on the top surfaces is removed by a planarization method, such as chemical mechanical polishing, to form the sidewall 2033 only on the sidewalls.

Thereafter, it is also possible: a source 2051 is formed in a portion of the first fin structure 2021 that is above the first well region 2011 and a drain 2052 is formed in the third fin 2023, wherein the source 2051 and the drain 2052 have a second conductivity type.

The method of forming the source 2051 and the drain 2052 includes: the regions where the source and drain are to be formed are ion-implanted, wherein an appropriate doping impurity is selected according to the type of the device to be formed, for example, for NMOS devices, the regions where the source and drain are to be formed may be ion-implanted with an N-type impurity (e.g., boron), and for PMOS devices, the regions where the source and drain are to be formed may be ion-implanted with a P-type impurity, which may include phosphorus, arsenic, or the like.

In one example, a layer of semiconductor material may also be epitaxially grown over the source 2051 region in the first fin structures 2021 and the drain 2052 region in the third fins 2023 to form raised source and drain regions.

Optionally, for a PMOS device, a recess may be formed in the source 2051 region and the drain 2052 region, the recess may preferably be a "sigma" shaped recess, and then a stress layer may be epitaxially grown in the recess to form a PMOS source and drain, and for the PMOS device, the stress layer may be SiGe, and in the present invention, the epitaxy may be one of reduced pressure epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy, and molecular beam epitaxy.

In another example, for an NMOS device, a recess is formed in each of the source 2051 region and the drain 2052 region, and a stress layer is epitaxially grown in the recess to form an NMOS source and drain, and SiP, SiC, or other suitable material that can provide tensile stress may be used as the stress layer of the NMOS, and one of reduced pressure epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, and molecular beam epitaxy may be used to form the stress layer.

It should be noted that a second source and a second drain may be simultaneously formed in the second fin structures on both sides of the second dummy gate structure in the core device region, where the second source and the second drain may be a source and a drain of an NMOS device, such as an N-type source and a drain, and a stress layer may also be epitaxially grown, which is not described herein.

Next, an interlayer dielectric layer 206 is deposited to cover the semiconductor substrate 200 and fill the gaps between adjacent dummy gate structures.

The interlayer dielectric layer 206 may be made of a dielectric material commonly used in the art, such as various oxides, and the interlayer dielectric layer 206 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 206 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

Thus, a structure as shown in fig. 2A is obtained.

Next, as shown in fig. 2B, the interlayer dielectric layer 206 is planarized, stopping on the top surface of the first dummy gate structure 203.

Planarization of the surface may be achieved using planarization methods that are conventional in the semiconductor fabrication art. Non-limiting examples of the planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method (CMP). Chemical mechanical polishing planarization methods are more commonly used.

Finally, an interlayer dielectric layer 206 exposing top surfaces of the first dummy gate structure 203 and the second dummy gate structure is formed.

And the film layers such as the side wall and the like on the top surface of the pseudo gate structure can be removed together in the planarization process.

Next, as shown in fig. 2C, a patterned mask layer 207 is formed on the interlayer dielectric layer 206, a portion of the first dummy gate structure 203 and the second dummy gate structure, wherein the patterned mask layer 207 exposes a portion of the first dummy gate structure 203 over the second well region 2012.

In particular, the mask layer 207 may generally comprise any of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. Preferably, the mask layer comprises a photoresist mask material. The photoresist mask material may include a photoresist material selected from the group consisting of a positive photoresist material, a negative photoresist material, and a hybrid photoresist material. Typically, the mask layer comprises a positive photoresist material or a negative photoresist material having a thickness of from about 2000 to about 5000 angstroms.

In one example, a photoresist mask material may be formed on the semiconductor substrate 200 by spin coating, and then patterned by a photolithography process including exposure and development to form a patterned mask layer 207 that exposes a portion of the first dummy gate structure 203 over the second well region 2012.

Next, with the mask layer 207 as a mask, ion implantation of a first conductive type impurity is performed on the exposed first dummy gate material layer 2032, so that the first dummy gate material layer 2032 including the impurity has a lower wet etching rate than other undoped dummy gate material layers.

Specifically, the first conductivity type impurity used in the ion implantation in this step may be appropriately selected according to the type of the device, and for example, for an NMOS device, a P-type impurity such as boron or the like may be used as the first conductivity type impurity. For PMOS devices, N-type impurities such as phosphorus or arsenic can be used for the first conductivity type impurities.

In one example, the first conductivity type impurity includes boron, and the portion of the first dummy gate material layer 2032 located above the second well region 2012 is ion implanted using, for example, boron or boron fluoride, and the portion of the first dummy gate material layer 2032 after doping has a lower etching rate in a wet etching (e.g., a wet etching of a tetramethylammonium hydroxide solution) than other regions, such as the portion of the first dummy gate material layer 2032 on the first well region 2011 and the portion of the dummy gate material layer 2032 in the core device region that is not doped, and the like.

The doped first dummy gate material layer 2032 may be amorphous silicon, and the undoped dummy gate material layer is mostly polysilicon.

Next, as shown in fig. 2D, the second dummy gate material layer in the core device region 20 and a portion of the first dummy gate material layer 2032 in the I/O device region are removed simultaneously, wherein a portion of the first dummy gate material layer 2032 located on the first well region 2011 is completely removed, and a portion of the first dummy gate material layer 2032 doped with the first conductive type impurities is remained located on the second well region 2012.

The second dummy gate material layer and a portion of the first dummy gate material layer 2032 may be removed by any suitable wet etching method known to those skilled in the art, and in one example, a tetramethylammonium hydroxide (TMAH) solution is preferably used as an etching solution for the wet etching.

Since the doped (e.g., boron doped) first dummy gate material layer 2032 has a lower etching rate in the TMAH solution than the undoped dummy gate material layer, when the second dummy gate material layer in the core device region 20 and the portion of the first dummy gate material layer 2032 on the first well region 2011 are completely removed, the doped first dummy gate material layer 2032 still remains on the second well region 2012, as shown in fig. 2D.

Wherein removing the second dummy gate material layer exposes the second dummy gate dielectric layer 2081 within the core device region 20, and removing a portion of the first dummy gate material layer exposes a portion of the first dummy gate dielectric layer 2031 within the I/O device region 10.

Next, as shown in fig. 2E, the remaining first dummy gate material layer 2032 is used as a mask, and the second dummy gate dielectric layer 2081 and a portion of the first dummy gate dielectric layer 2031 are removed at the same time to form a first gate trench 2091 and a second gate trench 2092 respectively located in the I/O device region 10 and the core device region 20, wherein the remaining first dummy gate dielectric layer 2031 is stepped.

Specifically, the second dummy gate dielectric layer 2081 and a portion of the first dummy gate dielectric layer 2031 may be removed by dry etching or wet etching. The dry etching can employ an anisotropic etching method based on a carbon fluoride gas. The wet etching can employ a hydrofluoric acid solution, such as a Buffered Oxide Etchant (BOE) or a buffered hydrofluoric acid (BHF).

Since the thickness of the first dummy gate dielectric layer 2031 is greater than that of the second dummy gate dielectric layer 2081, when the second dummy gate dielectric layer 2081 is completely removed, only the exposed portion of the first dummy gate dielectric layer 2031 is removed, and the portion of the first dummy gate dielectric layer 2031 covered by the remaining first dummy gate material layer 2032 is not etched, so that a stepped first dummy gate dielectric layer 2031 is finally formed, and the thickness of the portion of the first dummy gate dielectric layer 2031 covered by the remaining first dummy gate material layer 2032 is greater than the thickness of the portion not covered by the first dummy gate material layer 2032.

Subsequently, as shown in fig. 2F, a metal gate structure 210 is formed in the first gate trench 2091 and the second gate trench 2092.

In one example, the step of forming the metal gate structure 210 includes:

sequentially forming a high-k dielectric layer 2101 and a work function layer 2102 on the bottom and the side walls of the first gate trench and the second gate trench; a gate electrode layer 2103 is filled in the first gate trench and the second gate trench.

Optionally, before forming the high-k dielectric layer 2101, a step of forming an interface layer (not shown) at the bottom of the first gate trench and the second gate trench is further included.

For simplicity, fig. 2F only shows a schematic diagram of forming the metal gate structure 210 in the first gate trench 2091, and substantially the same process may be performed in the second gate trench 2092 to form the metal gate structure, which is not described herein again.

The Interface (IL) layer is formed of a material including silicon oxide (SiOx) and is formed to improve the interface characteristics between the high-k dielectric layer and the semiconductor substrate. The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a suitable process such as thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The interfacial layer has a thickness in the range of 5 angstroms to 10 angstroms.

The k value (dielectric constant) of high-k dielectric layer 2101 is usually 3.9 or more, and its constituent materials include hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-k dielectric layer 2101 may be formed using a suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The thickness of the high-k dielectric layer 2101 ranges from 10 to 30 angstroms.

In one example, for a PMOS device, the work function layer 2102 may be a P-type work function layer (PWF) of a material selected from, but not limited to, TixN1-x, TaC, MoN, TaN, or a combination thereof or other suitable thin film layer. The P-type work function layer may be formed using a suitable process such as CVD, ALD, or PVD. The P-type work function layer has a thickness ranging from 10 angstroms to 580 angstroms.

In another example, for an NMOS device, the work function layer 2102 may be an N-type work function layer (NWF), and the material of the N-type work function layer may be selected from, but not limited to, TaAlC, TaC, Ti, Al, TixAl1-x, or other suitable thin film layers. The material of the N-type work function layer is preferably TiAl. The N-type work function layer may be formed using a suitable process such as CVD, ALD, or PVD. The thickness of the N-type work function layer ranges from 10 angstroms to 80 angstroms.

The material of the gate electrode layer 2103 can be selected as, but not limited to, Al, W, or other suitable thin film layers. The gate electrode layer 2103 can be formed by a suitable process such as CVD, ALD, or PVD.

In one example, a chemical vapor phase is usedThe deposition process forms a metal W as the gate electrode layer 2103. Wherein the CVD process uses WF₆Decomposing WF as a reaction gas₆Depositing to form the metal W.

Illustratively, the gate electrode layer is deposited to fill all the gate recesses and overflow over the surface of the interlayer dielectric layer 206, and a planarization process, such as chemical mechanical polishing or wet etching, is performed until the surface of the interlayer dielectric layer 206 is exposed, during which the plurality of layers deposited on the surface of the interlayer dielectric layer 206 in the previous steps may be removed together.

Since the partially doped first dummy gate material layer is also remained under the metal gate structure, the material of the partially doped first dummy gate material layer comprises amorphous silicon (a-Si), and the amorphous silicon replaces part of the metal gate structure to serve as the gate structure of the LDMOS device.

Thus, the introduction of the key steps of the manufacturing method of the semiconductor device of the invention is completed, and other steps are required for the complete device manufacturing, for example, the manufacturing of the metal interconnection structure for leading out the source electrode, the drain electrode and the gate electrode in the back-end process, and the like, and the details are not repeated herein.

In summary, according to the manufacturing method of the present invention, the step-type dummy gate dielectric layer is formed in the I/O device region (i.e., the LDMOS device region) of the FinFET device, and a thicker dummy gate dielectric layer is reserved in the extension region of the LDMOS device region (i.e., the region where the first fin structure is located on the second well region), so that the breakdown voltage of the device is enhanced, and the overall performance of the device is improved.

Example two

The invention also provides a semiconductor device formed by the manufacturing method in the first embodiment, wherein the semiconductor device comprises an LDMOS device of a FinFET.

Referring to fig. 4, the structure of the semiconductor device of the present invention will be described in detail, the semiconductor device of the present invention including: a semiconductor substrate 300.

The semiconductor substrate 300 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment, the semiconductor substrate 300 is a silicon substrate.

In this embodiment, the I/O device region includes an LDMOS device region in which an LDMOS device is formed.

In one example, the first well region 3011 is a P-type well region and the second well region 3012 is an N-type well region.

First fin structures 3021 located in the I/O device region are formed on the semiconductor substrate 300, wherein the first fin structures 3021 are partially located on the first well region 3011 and partially located on the second well region 3012.

In one example, the semiconductor substrate further includes a core device region, a second fin structure is disposed on the semiconductor substrate in the core device region, a third well region having the first conductivity type is further formed in the semiconductor substrate corresponding to the core device region, and the second fin structure is located on the third well region.

Illustratively, a third fin structure 3023 is disposed on the semiconductor substrate 300 and located on the second well region 3012, wherein the third fin structure 3023 is spaced apart from the first fin structure 3021.

Wherein the plurality of fin structures formed on the semiconductor substrate may all be the same in width and length, or the fin structures may be divided into a plurality of fin structure groups having different widths and lengths. Each fin structure may be a strip-shaped structure formed on the semiconductor substrate 300.

Wherein the first fin structures 3021 are partially located on the first well region 3011, partially located on the second well region 3012, and the third fin structures 3023 are located on the second well region 3012, since various well regions are already formed in the semiconductor substrate 300 before the first fin structures 3021, the second fin structures, and the third fin structures 3023 are formed, the correspondingly formed first fin structures 3021 include portions of the same conductivity type as the first well region 3011 and portions of the same conductivity type as the second well region 3012, and the third fin structures 3023 include portions of the same conductivity type as the second well region 3012, and the second fin structures 3023 include the same conductivity type as the third well region.

Wherein an isolation structure 304 is disposed on the semiconductor substrate 300 outside the first fin structures 3021, and a top surface of the isolation structure 304 is lower than a top surface of the first fin structures 3021.

Further, the isolation structures 304 fill portions of the gaps between all adjacent fin structures on the semiconductor substrate 300, and have top surfaces that are lower than the top surfaces of any of the fin structures.

The isolation structure 304 may be made of an oxide, such as a High Aspect Ratio Process (HARP) oxide, specifically, silicon oxide deposited by a flowable chemical vapor deposition process, or the like.

The semiconductor device of the present invention further comprises: a dummy gate dielectric layer 3031 spanning a portion of the first fin structures 3021, wherein the dummy gate dielectric layer 3031 is located on the first fin structures 3021 over portions of the first well region 3011 and the second well region 3012, and covers a first edge of the first fin structures 3021 over the second well region 3012 and extends outward to a portion of the isolation structure 304 outside the first edge.

A dummy gate material layer 3032 is disposed on a portion of the dummy gate dielectric layer 3031, the dummy gate material layer 3032 is doped with impurities of the first conductivity type, and the dummy gate material layer 3032 is located on a portion of the second well region 3012, covers a first edge of the first fin structure 3021 located on the second well region 3012, and extends outward to a portion of the isolation structure 304 outside the first edge.

The thickness of the dummy gate dielectric layer 3031 covered by the dummy gate material layer 3032 is greater than that of the rest of the dummy gate dielectric layer 3031, so that the dummy gate dielectric layer 3031 is stepped.

The dummy gate dielectric layer 3031 may be a commonly used oxide such as SiO₂The dummy gate material layer 3032 may be made of a semiconductor material commonly used in the art, which is not limited to a specific one, and is not listed here, wherein the dummy gate material layer 3032 is doped with a first conductivity type impurity, which may be an N-type impurity, such as boron, that is, the dummy gate material layer 3032 is amorphous silicon doped with boron.

A first metal gate structure 310 is disposed on the dummy gate dielectric layer 3031 and spans a portion of the first fin structure 3021, wherein a portion of the first metal gate structure 310 is located on the dummy gate material layer 3032.

Further, a second metal gate structure crossing the second fin structure is arranged on the second fin structure in the core device area.

Each metal gate structure (e.g., a first metal gate structure and a second metal gate structure) includes a high-k dielectric layer 3101, a work function layer 3102, and a gate electrode layer 3103, which are sequentially formed.

Here, the stack of the high-k dielectric layer 3101 and the work function layer 3102 surrounds the bottom and the side wall of the gate electrode layer 3103.

In one example, an interfacial layer (not shown) is also disposed between the dummy gate dielectric layer 3031 and the high-k dielectric layer 3101.

The Interface (IL) layer is formed of a material including silicon oxide (SiOx) and is formed to improve the interface characteristics between the high-k dielectric layer and the semiconductor substrate. The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer has a thickness in the range of 5 angstroms to 10 angstroms.

High-k dielectric layer 3101 has a k value (dielectric constant) of usually 3.9 or more, and its constituent material includes hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., preferably hafnium oxide, zirconium oxide, or aluminum oxide. The thickness of high-k dielectric layer 3101 ranges from 10 angstroms to 30 angstroms.

In one example, for a PMOS device, the work function layer 3102 may be a P-type work function layer (PWF), the material of which may be selected to be, but is not limited to, TixN1-x, TaC, MoN, TaN, or a combination thereof, or other suitable thin film layer. The P-type work function layer has a thickness ranging from 10 angstroms to 580 angstroms.

In another example, for an NMOS device, the work function layer 3102 may be an N-type work function layer (NWF), and the material of the N-type work function layer may be selected from, but not limited to, TaAlC, TaC, Ti, Al, TixAl1-x, or other suitable thin film layers. The material of the N-type work function layer is preferably TiAl. The thickness of the N-type work function layer ranges from 10 angstroms to 80 angstroms.

The material of the gate electrode layer 3103 can be selected as, but not limited to, Al, W, or other suitable thin film layers.

Side walls 3033 are disposed on two side walls of the first metal gate structure 310, wherein the side wall 3033 close to the dummy gate material layer 3032 is located on the isolation structure 304.

The side wall 3033 may be made of one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the sidewall spacers are formed by silicon oxide and silicon nitride

Further, a source 3051 is formed in a portion of the first fin structure that is above the first well region 3011 and a drain 3052 is formed in the third fin structure 3023, wherein the source 3051 and the drain 3052 are of a second conductivity type, e.g., they are N-type sources and drains. The source 3051 is formed in a partial region of the first fin structure not covered by the first metal gate structure 310 and the sidewall 3033.

The source 3051 and drain 3052 regions may also be provided with epitaxially grown stress layers, the material of the stress layers may be different according to the type of the device, for an NMOS device, the stress layer may be SiP, SiC, or other material capable of providing tensile stress, for a PMOS device, the stress layer is preferably "Σ" type, and the material thereof may be SiGe material capable of providing compressive stress.

It should be noted that a second source and a second drain are formed in the second fin structures on two sides of the second dummy gate structure in the core device region, where the second source and the second drain may be a source and a drain of an NMOS device, such as an N-type source and a drain, and a stress layer may also be epitaxially grown, which is not described herein.

An interlayer dielectric layer 306 is formed on the surface of the semiconductor substrate 300, the first metal gate structure 310 is located in the interlayer dielectric layer 306, and the top surface of the interlayer dielectric layer 306 is flush with the top surface of the first metal gate structure.

The interlayer dielectric layer 306 may be made of dielectric materials commonly used in the art, such as various oxides, and the interlayer dielectric layer 306 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 306 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

The complete device may further include other elements, such as a metal interconnection structure for leading out a source, a drain, a gate, and the like, which are not described herein again.

The semiconductor device is manufactured by the manufacturing method, and when the manufacturing method has excellent effects, the formed semiconductor device has the same technical effects.

EXAMPLE III

The invention also provides an electronic device comprising the semiconductor device of the second embodiment, and the semiconductor device is prepared according to the method of the first embodiment.

The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the circuit.

Wherein figure 5 shows an example of a mobile telephone handset. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.

Wherein the mobile phone handset comprises the semiconductor device of embodiment two, the semiconductor device comprising:

a dummy gate dielectric layer and a dummy gate material layer are arranged to cross over a part of the first fin structures, the dummy gate material layer is doped with impurities of a first conductivity type, wherein the dummy gate dielectric layer is arranged above a part of the first well region and the second well region, the dummy gate material is arranged above the dummy gate dielectric layer, the dummy gate material layer is arranged on a part of the second well region, covers a first edge of the first fin structures on the second well region and extends outwards to a part of the isolation structure outside the first edge, and the thickness of the dummy gate dielectric layer covered by the dummy gate material layer is larger than that of the rest part of the dummy gate dielectric layer, so that the dummy gate dielectric layer is in a step shape;

a first metal gate structure is disposed across a portion of the first fin structure, wherein the first metal gate structure is on the dummy gate dielectric layer and the dummy gate material layer.

Because the step-type pseudo gate dielectric layer is formed in the LDMOS device region of the semiconductor device, the semiconductor device has stronger breakdown voltage and higher performance, and an electronic device comprising the semiconductor device also has correspondingly higher performance.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

removing the second dummy gate dielectric layer and part of the first dummy gate dielectric layer by taking the remaining first dummy gate material layer as a mask to form a first gate trench and a second gate trench which are respectively positioned in the I/O device area and the core device area, wherein the remaining first dummy gate dielectric layer is of a step type, and the thickness of the part of the first dummy gate dielectric layer covered by the remaining first dummy gate material layer is larger than that of the part of the first dummy gate dielectric layer not covered by the first dummy gate material layer;

forming a metal gate structure in the first and second gate trenches.

2. The method of manufacturing of claim 1, further comprising, prior to forming the first fin structures and the second fin structures, forming a third well region having the first conductivity type within the semiconductor substrate within the core device region.

3. The method of manufacturing of claim 2, wherein the second fin structures are formed over the third well regions.

4. The method of manufacturing of claim 1, wherein a thickness of the first dummy gate dielectric layer is greater than a thickness of the second dummy gate dielectric layer.

5. The method of manufacturing of claim 1, when forming the first fin structures and the second fin structures, further comprising: and forming a third fin structure on the semiconductor substrate and on the second well region, wherein the third fin structure and the first fin structure are arranged at intervals.

6. The method of manufacturing of claim 5, wherein after forming the first dummy gate structure and before forming the interlayer dielectric layer, further comprising forming a source in a portion of the first fin structures over the first well region and forming a drain in the third fin structures, wherein the source and the drain are of a second conductivity type.

7. The method of claim 6, further comprising a step of forming spacers on sidewalls of the first dummy gate structure before forming the source and drain.

8. The method of manufacturing of claim 1, wherein forming the metal gate structure comprises:

9. The method of manufacturing of claim 8, further comprising, prior to forming the high-k dielectric layer, the step of forming an interfacial layer at a bottom of the first gate trench and the second gate trench.

10. The method of manufacturing of claim 1, wherein in the first gate trench, the remaining first dummy gate material layer is amorphous silicon.

11. The method of manufacturing of claim 1, wherein the second dummy gate material layer and a portion of the first dummy gate material layer are removed using a wet etch.

12. The manufacturing method according to claim 11, wherein a tetramethylammonium hydroxide solution is used as an etching liquid for the wet etching.

13. The manufacturing method according to any one of claims 1 to 12, wherein the first conductivity type is a P-type and the second conductivity type is an N-type, or wherein the first conductivity type is an N-type and the second conductivity type is a P-type.

14. The manufacturing method according to claim 1, wherein the first conductivity type impurity includes boron.

15. A semiconductor device, comprising:

16. The semiconductor device of claim 15, wherein the semiconductor substrate further comprises a core device region, wherein a second fin structure is disposed on the semiconductor substrate within the core device region, and wherein a second metal gate structure is disposed on the second fin structure across the second fin structure.

17. The semiconductor device of claim 15, wherein an interlayer dielectric layer is formed on the surface of the semiconductor substrate, wherein the first metal gate structure is located in the interlayer dielectric layer, and wherein a top surface of the interlayer dielectric layer is flush with a top surface of the first metal gate structure.

18. The semiconductor device of claim 15, wherein a third fin structure is disposed on the semiconductor substrate over the second well region, wherein the third fin structure is spaced apart from the first fin structure.

19. The semiconductor device of claim 18, wherein a source is formed in a portion of the first fin structures that is above the first well region and a drain is formed in the third fin structures, wherein the source and the drain are of a second conductivity type.

20. The semiconductor device according to claim 15, wherein the first metal gate structure includes a high-k dielectric layer, a work function layer, and a gate electrode layer which are stacked in this order.

21. The semiconductor device according to claim 15, wherein side walls are disposed on two side walls of the first metal gate structure, wherein the side walls adjacent to the dummy gate material layer are disposed on the isolation structure.

22. The semiconductor device according to claim 15, wherein the first conductivity type impurity includes boron.

23. The semiconductor device of claim 15, wherein a material of the dummy gate material layer is amorphous silicon.

24. The semiconductor device according to any one of claims 15 to 23, wherein the first conductivity type is a P type and the second conductivity type is an N type, or wherein the first conductivity type is an N type and the second conductivity type is a P type.

25. An electronic device comprising the semiconductor device according to any one of claims 15 to 24.