CN107799471B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, and forming a first fin structure, a second fin structure and a third fin structure in the pull-up body tube area, the pull-down body tube area and the transfer gate transistor area on the semiconductor substrate respectively; removing the first dummy gate structure and the second dummy gate structure to form a first gate groove and a second gate groove; forming a first P-type work function layer on the bottom and the side wall of a first grid electrode groove in a pull-up body tube area; forming a second P-type work function layer on the bottom and the side wall of the first grid electrode groove; forming a third P-type work function layer on the bottom and the side wall of the first grid electrode groove and the second grid electrode groove in the lower crystal pulling body pipe area; and forming an N-type work function layer on the bottom and the side wall of the first grid electrode groove and the second grid electrode groove.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In the field of semiconductor technology, a Static Random Access Memory (SRAM) device is widely used as a typical semiconductor device in electronic devices such as computers, mobile phones, and digital cameras. Currently, there are designs that use fin field effect transistors (finfets) as the transistor devices of SRAM cells to improve SRAM density and performance.
In order to adjust the α ratio, β ratio, and gamma ratio of an SRAM device for better device performance, one approach in the prior art is to select different numbers of fin structures, e.g., 1, or 1, 2, 1, or 1, 3, 2, respectively, for the pull-up transistor (PU), the pull-down transistor (PD), and the pass-gate transistor (PG) of the SRAM device.
Different types of SRAM devices have different metal gate stack structures to meet the read and write margin requirements. In addition, threshold voltage (Vt) mismatch (mismatch) performance of different metal gate stack structures is different, and thus static noise margin (static noise margin) of the SRAM device is completely different, and the static noise margin is a critical parameter determining the SRAM yield.
The work function layer in the FinFET device is very important for adjusting the device, a post-metal gate process is usually selected to form the work function layer in the device preparation process, TiAlC is used as the work function layer for NMOS in order to meet the requirements of the device, but TiAlC is diffused differently at the boundary, so that the mismatch performance of the SRAM device is easily influenced by Al diffusion.
Therefore, in order to solve the above problems, it is necessary to provide a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the defects in the prior art, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a pull-up body tube area, a pull-down body tube area and a transmission gate transistor area, and a first fin structure, a second fin structure and a third fin structure are respectively formed in the pull-up body tube area, the pull-down body tube area and the transmission gate transistor area on the semiconductor substrate;
forming a first dummy gate structure spanning the first fin structure and the second fin structure, and a second dummy gate structure spanning the third fin structure;
removing the first dummy gate structure to form a first gate groove, and removing the second dummy gate structure to form a second gate groove;
forming a first P-type work function layer on the bottom and the side wall of the first grid electrode groove in the pull-up body tube area;
forming a second P-type work function layer on the bottom and the side wall of the first grid electrode groove;
forming a third P-type work function layer on the bottom and the side wall of the first gate groove and the second gate groove in the pull-down body tube region;
and forming an N-type work function layer on the bottom and the side wall of the first grid electrode groove and the second grid electrode groove.
Further, the third fin structure is connected with the second fin structure.
Furthermore, at least one fourth fin structure is formed on the lower crystal body tube area.
Further, the first gate recess exposes a portion of the fourth fin structures in an extending direction of the fourth fin structures.
Further, before forming the first P-type work function layer, the method further includes the steps of: and forming a high-k dielectric layer on the bottom and the side wall of the first gate groove and the second gate groove, and annealing the high-k dielectric layer.
Further, after the second P-type work function layer is formed and before the third work function layer is formed, a step of forming a first barrier layer on the second P-type work function layer in the pull-up body tube region and the pull-down body tube region is further included.
Further, the first P-type work function layer, the second P-type work function layer and the third P-type work function layer are made of TiN.
Further, the material of the N-type work function layer comprises one or a combination of TiAl and TiAl C.
Further, after the N-type work function layer is formed, the method further includes the steps of:
forming a second barrier layer on the N-type work function layer;
and filling metal gate electrode layers in the first gate groove and the second gate groove.
Further, the step of forming the metal gate electrode layer includes:
depositing and forming a metal material on the semiconductor substrate, and carrying out chemical mechanical polishing on the metal material to form the metal gate electrode layer, wherein the top surface of the metal gate electrode layer is flush with the tops of the first gate groove and the second gate groove.
Further, before the first gate groove and the second gate groove are formed, an isolation structure is further formed on the semiconductor substrate outside the first fin structure, the second fin structure and the third fin structure, and the top surface of the isolation structure is lower than the top surfaces of the first fin structure, the second fin structure and the third fin structure.
Further, before forming the high-k dielectric layer, a step of forming an interface layer at the bottom of the first gate groove and the second gate groove is also included.
Still another aspect of the present invention provides a semiconductor device including:
the semiconductor substrate comprises a pull-up body tube area, a pull-down body tube area and a transmission gate transistor area, wherein a first fin structure, a second fin structure and a third fin structure are respectively formed in the pull-up body tube area, the pull-down body tube area and the transmission gate transistor area on the semiconductor substrate;
the first metal grid laminated structure is formed in the crystal pulling body tube area and stretches across the first fin structure and comprises a first P-type work function layer, a second P-type work function layer and an N-type work function layer which are sequentially laminated from bottom to top;
the second metal gate laminated structure is formed in the pull-down body tube area, spans the second fin structure, is connected with the first metal gate laminated structure, and comprises a second P-type work function layer, a third P-type work function layer and an N-type work function layer which are sequentially laminated from bottom to top;
and the third metal gate laminated structure is formed in the transistor area of the transmission gate, spans the third fin structure and comprises a third P-type work function layer and an N-type work function layer which are sequentially laminated from bottom to top.
Further, the third fin structure is connected with the second fin structure.
Furthermore, at least one fourth fin structure is formed on the lower crystal body tube area.
Further, the second metal gate stack structure spans across the fourth fin structures.
Further, first barrier layers are further arranged between the second P-type work function layer and the N-type work function layer in the upper pulling body tube area and between the second P-type work function layer and the third P-type work function layer in the lower pulling body tube area.
Further, a second blocking layer is formed on the N-type work function layer, and a metal gate electrode layer is formed on the second blocking layer.
Further, isolation structures are formed on the semiconductor substrate outside the first fin structures, the second fin structures and the third fin structures, and top surfaces of the isolation structures are lower than top surfaces of the first fin structures, the second fin structures and the third fin structures.
In another aspect, the present invention provides an electronic device including the semiconductor device.
According to the manufacturing method, firstly, the boundaries of the pull-up PMOS and the pull-down NMOS are simpler and weaker in mutual influence, and the mismatch performance of the devices is improved; secondly, the metal gate lamination structure is simpler, and the combination with the number of the fins can easily enable the read-write margin to meet the requirements of the device; furthermore, the third P-type work function layer is formed below the N-type work function layer, so that aluminum diffusion is completely eliminated, and the mismatch performance of the device is improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1H illustrate cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device in an embodiment of the present invention;
fig. 2 shows a top view of a structure obtained by a method of manufacturing a semiconductor device in an embodiment of the invention;
FIG. 3 shows a schematic flow chart of a method of manufacturing a semiconductor device of an embodiment of the invention;
fig. 4 shows a schematic diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the existing technical problem, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 3, which mainly includes the following steps:
in step S301, a semiconductor substrate is provided, where the semiconductor substrate includes a pull-up transistor area, a pull-down transistor area, and a transfer gate transistor area, and a first fin structure, a second fin structure, and a third fin structure are respectively formed in the pull-up transistor area, the pull-down transistor area, and the transfer gate transistor area on the semiconductor substrate;
in step S302, forming a first dummy gate structure crossing over the first fin structures and the second fin structures, and a second dummy gate structure crossing over the third fin structures;
in step S303, removing the first dummy gate structure to form a first gate recess, and removing the second dummy gate structure to form a second gate recess;
in step S304, a first P-type work function layer is formed on the bottom and sidewalls of the first gate groove in the pull-up body tube region;
in step S305, forming a second P-type work function layer on the bottom and the sidewall of the first gate groove;
in step S306, forming a third P-type work function layer on the bottom and sidewalls of the first and second gate grooves in the pull-down body tube region;
in step S307, an N-type work function layer is formed on the bottom and sidewalls of the first and second gate grooves.
According to the manufacturing method, firstly, the boundaries (boundaries) of the pull-up transistor and the pull-down transistor are simpler and weaker in mutual influence, and the mismatch performance of the device is improved; secondly, the metal gate lamination structure is simpler, and the combination with the number of the fins can easily enable the read-write margin to meet the requirements of the device; furthermore, the third P-type work function layer is formed below the N-type work function layer, so that aluminum diffusion is completely eliminated, and the mismatch performance of the device is improved.
Example one
A method of manufacturing a semiconductor device according to the present invention is described in detail with reference to fig. 1A to 1H, in which fig. 1A to 1H show cross-sectional views of structures formed at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 2 shows a top view of a structure obtained by a method of manufacturing a semiconductor device in an embodiment of the present invention, and the structure obtained along the cross-sectional line in fig. 2 corresponds to the structure in fig. 1H.
Specifically, first, as shown in fig. 1A, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a pull-up body tube region, a pull-down body tube region, and a transfer gate transistor region, and a first fin structure 1021, a second fin structure 1022, and a third fin structure 1023 are formed in the pull-up body tube region, the pull-down body tube region, and the transfer gate transistor region on the semiconductor substrate, respectively.
Specifically, the semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment, the semiconductor substrate 100 uses a silicon substrate.
The semiconductor substrate 100 may include active regions for forming various constituent elements of the SRAM, for example, a pull-up transistor region for forming a pull-up transistor (PU) of the SRAM, a pull-down transistor region for forming a pull-down transistor (PD) of the SRAM, and a pass-gate transistor region for forming a pass-gate transistor (PG), wherein the pull-up transistor is PMOS, and the pull-down transistor and the pass-gate transistor are NMOS.
And then forming a Pad oxide layer (Pad oxide) on the semiconductor substrate, wherein the forming method of the Pad oxide layer (Pad oxide) can be formed by a deposition method, such as a chemical vapor deposition method, an atomic layer deposition method, and the like, and can also be formed by thermally oxidizing the surface of the semiconductor substrate, and details are not repeated here.
Further, the step may further include a step of performing ion implantation to form various well regions in the semiconductor substrate, for example, an N-type well region (NW) in the pull-up transistor region and a P-type well region (PW) in the pull-down transistor region and the transfer gate transistor region, wherein the implanted ion species and the implantation method may be methods commonly used in the art and are not described herein again.
A first fin structure 1021, a second fin structure 1022, and a third fin structure 1023 are formed in the pull-up body tube region, the pull-down body tube region, and the transfer gate transistor region, respectively, on the semiconductor substrate.
The first fin structure 1021, the second fin structure 1022, and the third fin structure 1023 all extend a certain length in the same direction on the semiconductor substrate, and each fin structure may also be a plurality of strip structures formed on the semiconductor substrate 100.
Further, at least a fourth fin structure 1024 parallel to the second fin structure 1022 is formed in the pull-down transistor area, and the fourth fin structure 1024 and the second fin structure 1022 are both used for forming a pull-down transistor of the SRAM.
In one example, second fin structure 1022 and third fin structure 1023 are connected, which can be different portions of the same fin structure within a pull down transistor region and a pass gate transistor region, respectively.
In one example, to obtain the structure shown in fig. 1A, the following process steps may be performed:
first, step 1011 is performed to form a plurality of fin structures, such as a first fin structure 1021, a second fin structure 1022, a third fin structure 1023, and a fourth fin structure 1024, on the semiconductor substrate, wherein the widths of the fin structures are all the same, or the fins are divided into a plurality of fin structure groups with different widths, and the lengths of the fin structures may be different.
Specifically, the formation method of the fin structure is not limited to a certain one, and an exemplary formation method is given below: forming a hard mask layer (not shown) on the semiconductor substrate, wherein the hard mask layer may be formed by using various suitable processes, such as a chemical vapor deposition process, which are familiar to those skilled in the art, and the hard mask layer may be a bottom-up stacked oxide layer and a silicon nitride layer; patterning the hard mask layer, forming a plurality of isolated masks for etching the semiconductor substrate to form fins thereon, in one embodiment, the patterning is performed using a self-aligned double pattern (SADP) process; the semiconductor substrate is etched to form fin structures thereon.
Subsequently, step 1012 may be further performed to form an isolation structure 101 on the semiconductor substrate outside the first fin structures 1021, the second fin structures 1022, and the third fin structures 1023, wherein a top surface of the isolation structure 101 is lower than top surfaces of the first fin structures, the second fin structures, and the third fin structures.
Specifically, a layer of spacer material is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer may be selected from oxides, such as High Aspect Ratio Process (HARP) oxide, and may specifically be silicon oxide.
The layer of spacer material is then etched back to the target height of the fin structure to form the isolation structure 101. Specifically, the isolation material layer is etched back to expose a portion of the fin, thereby forming a fin with a specific height.
Next, step 1013 is performed to form a first dummy gate structure crossing over the first fin structures 1021, the fourth fin structures 1024, and the second fin structures 1022, and also simultaneously form a second dummy gate structure crossing over the third fin structures 1023, wherein the dummy gate structure includes a dummy gate dielectric layer and a dummy gate material layer.
It is noted that the term "cross over" as used in the present invention, such as a dummy gate structure that crosses over a fin structure (e.g., a first fin structure, a second fin structure, etc.), means that the dummy gate structure is formed on both the top surface and the side surface of a portion of the fin structure, and the dummy gate structure is also formed on a portion of the surface of the semiconductor substrate. The explanation here for "cross-over" applies equally to the metal gate stack structure, etc., that is referred to below as cross-over fin structures.
In one example, a dummy gate dielectric layer and a dummy gate material layer may be deposited sequentially on a semiconductor substrate.
The dummy gate dielectric layer can be made of common oxide, such as SiO2The dummy gate material layer may be made of a semiconductor material commonly used in the art, such as polysilicon, but not limited to one of the above materialsThis is not to be enumerated.
The deposition method of the dummy gate material layer can be chemical vapor deposition or atomic layer deposition.
The dummy gate dielectric layer and the dummy gate material layer are then patterned to form the first dummy gate structure and the second dummy gate structure. Specifically, a photoresist layer is formed on the dummy gate material layer, and then exposed and developed to form an opening, and then the dummy gate material layer is etched using the photoresist layer as a mask.
And then, optionally, forming offset side walls (spacers) on the side walls of the first dummy gate structure and the second dummy gate structure.
Specifically, the offset spacer may be formed of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. As an implementation manner of this embodiment, the offset spacer is composed of silicon oxide and silicon nitride, and the specific process includes: and forming a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer on the semiconductor substrate, and then forming the offset side wall by adopting an etching method. Or forming offset sidewall material layers on the top surfaces and the sidewalls of the first dummy gate structure and the second dummy gate structure, and removing the offset sidewall material layers on the top surfaces by a planarization method, such as chemical mechanical polishing, in a subsequent step to form the offset sidewalls only on the sidewalls.
Optionally, LDD ion implantation steps are performed and activated on both sides of the NMOS dummy gate structure and the PMOS dummy gate structure.
Optionally, a spacer is formed on the offset spacers of the NMOS dummy gate structure and the PMOS dummy gate structure.
Specifically, spacers (spacers) are formed on the offset sidewalls, and the spacers may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are formed on a semiconductor substrate, and then a spacer is formed by an etching method.
Next, step 1014 is executed to perform source-drain ion implantation, and form respective source-drain electrodes in the first fin structure 1021, the second fin structure 1022, and the fourth fin structure 1024 on the two sides of the first dummy gate structure, and form a source-drain electrode of the pass-gate transistor in the third fin structure 1023 on the two sides of the second dummy gate structure, where when the second fin structure 1022 and the third fin structure 1023 are connected, a drain electrode of the pass-gate transistor is electrically connected with a drain electrode of the pull-down transistor formed on the second fin structure 1022, or share the same drain electrode.
Next, step 1015 is performed to deposit the interlayer dielectric layer (not shown) and planarize to fill the gaps between the dummy gate structures.
Specifically, an interlayer dielectric layer is deposited and planarized, and the pair of interlayer dielectric layers is planarized to the top of the dummy gate structure.
The interlayer dielectric layer may be made of dielectric materials commonly used in the art, such as various oxides, etc., and in this embodiment, the interlayer dielectric layer may be made of SiO2The thickness is not limited to a certain value.
Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method.
And then, as shown in fig. 1A, removing the first dummy gate structure and the second dummy gate structure to form a first gate groove and a second gate groove on the semiconductor substrate.
And removing the first dummy gate structure to form a first gate groove, removing the second dummy gate structure to form a second gate groove, wherein the first gate groove is located in the pull-up body tube region and the pull-down body tube region and exposes a portion of the first fin structure and the second fin structure in the extending direction of the first fin structure and the second fin structure, and further, when a fourth fin structure 1024 is formed in the pull-down body tube region, the first gate groove also exposes a portion of the fourth fin structure 1024.
The second gate recess is located in the transfer gate transistor region, and a portion of the third fin structure is exposed in an extending direction of the third fin structure, wherein in this embodiment, all of the diagrams shown in fig. 1A to 1H are cross-sectional views obtained by cutting a surface of the semiconductor device, which extends along the extending direction of the gate recess and is perpendicular to the surface of the semiconductor substrate.
Specifically, the dummy gate material layer may be removed first, and then the dummy gate dielectric layer may be removed.
Illustratively, the dummy gate material layer (e.g., polysilicon layer) is removed to form a trench. The removal method may be photolithography and etching. The gas used in the etching process includes HBr, which is the main etching gas; and further comprises O as an etching supplementary gas2Or Ar, which may improve the quality of the etch.
And then removing the dummy gate dielectric layer by using a SiCoNi method to expose the fin. In the step, in order to reduce the damage to other material layers in the process of removing the pseudo gate dielectric layer, HF is not selected for etching, but a SiCoNi process with higher selectivity is selected, and the pseudo gate dielectric layer is removed by the method without damaging a device.
Next, as shown in fig. 1A, a high-k dielectric layer 103 and a first P-type work function layer 1041 are sequentially formed on the bottom and the sidewall of the first gate recess and the second gate recess.
Optionally, before forming the high-k dielectric layer 103, a step of forming an interface layer (not shown) at the bottom of the first gate groove and the second gate groove is further included.
The Interface (IL) layer is formed of a material including silicon oxide (SiOx) and is formed to improve the interface characteristics between the high-k dielectric layer and the semiconductor substrate. The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a suitable process such as thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The interfacial layer has a thickness in the range of 5 angstroms to 10 angstroms.
High-k dielectric layer 103 has a k value (dielectric constant) of usually 3.9 or more, and is composed of a material such as hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-k dielectric layer 103 may be formed using a suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The thickness of the high-k dielectric layer 103 ranges from 10 angstroms to 30 angstroms.
Optionally, after the high-k dielectric layer 103 is formed, an annealing process may also be performed on the high-k dielectric layer 103. The annealing process may be any suitable annealing method known to those skilled in the art, such as rapid thermal annealing, furnace tube annealing, and the like. For example, hafnium oxide is deposited as the high-k dielectric layer 103 by using atomic layer deposition, and in order to obtain a pure crystalline structure of hafnium oxide, the high-k dielectric layer needs to be annealed, for example, at 400 to 600 ℃ for 30 to 600 seconds, which is called post-deposition annealing (PDA).
The material of the first P-type work function layer (PWF)1041 may be selected from, but not limited to, TixN1-x, TaC, MoN, TaN, or a combination thereof or other suitable thin film layer. Preferably, TiN may be used as the material of the first P-type work function layer. The first P-type work function layer 1041 may be formed using a suitable process such as CVD, ALD, or PVD. The first P-type work function layer 1041 has a thickness ranging from 10 to 580 angstroms.
Illustratively, in the pull-up and pull-down body tube regions, a high-k dielectric layer 103 and a first P-type work function layer 1041 are formed in the first gate recess and across the first fin structure 1021, the fourth fin structure 1024, and the second fin structure 1022, and in the pass gate transistor region, a high-k dielectric layer 103 and a first P-type work function layer 1041 are formed in the second gate recess and across the third fin structure 1023.
Next, as shown in fig. 1B, the first P-type work function layer 1041 in the pull-down body transistor region and the transfer gate transistor region is removed, and the high-k dielectric layer 103 is exposed to form a first P-type work function layer on the bottom and sidewalls of the first gate recess in the pull-up body transistor region.
Specifically, a patterned photoresist layer (not shown) exposing the first P-type work function layer 1041 in the pull-down body region and the transfer gate transistor region, covering the pull-up body region, is formed on the semiconductor substrate 100.
Thereafter, the removal of the first P-type work function layer 1041 in this step may be achieved using any etching method known to those skilled in the art, including but not limited to wet etching or dry etching. Preferably, dry etching is used, and the dry etching may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
Next, as shown in fig. 1C, a second P-type work function layer 1042 and a first blocking layer 105 are sequentially formed on the bottom and sidewalls of the first gate recess and the second gate recess.
Wherein the second P-type work function layer 1042 in the pull-up body tube region is formed over the first P-type work function layer 1041, and the second P-type work function layer 1042 in the pull-down body tube region and the transfer gate transistor region is formed over the high-k dielectric layer 103.
Specifically, the second P-type work function layer 1042 may be made of the same material as the first P-type work function layer 1041, for example, TiN, or a different material.
Wherein, the material of the second P-type work function layer 1042 can be selected from but not limited to TixN1-x, TaC, MoN, TaN or their combination or other suitable thin film layer. Preferably, TiN may be used for the second P-type work function layer 1042. The second P-type work function layer 1042 may be formed using a suitable process such as CVD, ALD, or PVD. The second P-type work function layer 1042 has a thickness in the range of 10 to 580 angstroms.
The material of the first barrier layer 105 includes one or more of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, and tungsten nitride, and in this embodiment, the first barrier layer 105 is preferably tantalum nitride (TaN).
The first barrier layer 105 may be formed by a process such as physical vapor deposition, atomic layer deposition, spin-on deposition (spin-on) deposition, or other suitable methods. The first barrier layer 105 may be formed at a temperature between-40 ℃ and 400 ℃ and a pressure between about 0.1 mTorr and 100 mTorr. In addition, the first barrier layer 105 may also include a plurality of layers.
Next, as shown in fig. 1D, the first blocking layer 105 and the second P-type work function layer 1042 in the pass gate transistor region are removed to expose the high-k dielectric layer 103, so as to form a second P-type work function layer only on the bottom and sidewalls of the first gate recess.
Specifically, a patterned photoresist layer (not shown) is formed on the semiconductor substrate 100, exposing the second P-type work function layer 1042 in the transfer gate transistor region, covering the pull-up body region and the pull-down body region.
After that, the first barrier layer 105 may be removed by etching, and then the second P-type work function layer 1042 may be removed by any etching method known to those skilled in the art, including but not limited to wet etching or dry etching, preferably dry etching, which may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination thereof. A single etching method may also be used, or more than one etching method may also be used.
Next, as shown in fig. 1E, a third P-type work function layer 1043 is formed on the bottom and sidewalls of the first and second gate grooves.
Wherein a third P-type work function layer 1043 in a pull-up body tube region and in the pull-down body tube region is formed over the first barrier layer 105, and a third P-type work function layer 1043 in the transfer gate transistor region is formed over the high-k dielectric layer 103.
Specifically, the third P-type work function layer 1043 may be made of the same material as the first P-type work function layer 1041 and the second P-type work function layer 1042, for example, TiN may be used, or a different material may be used.
The material of the third P-type work function layer 1043 can be selected from, but not limited to, TixN1-x, TaC, MoN, TaN, or their combination or other suitable thin film layer. Preferably, TiN may be used for the third P-type work function layer 1043. The third P-type work function layer 1043 may be formed by a suitable process such as CVD, ALD, or PVD. The third P-type work function layer 1043 has a thickness ranging from 10 to 580 angstroms.
Thereafter, as shown in fig. 1F, the third P-type work function layer 1043 in the pull-up body tube region is removed to form a third P-type work function layer on the bottom and sidewalls of the first and second gate grooves in the pull-down body tube region.
Specifically, a patterned photoresist layer (not shown) is formed on the semiconductor substrate 100, which exposes the second P-type work function layer 1042 in the pull-up body region, covering the transfer gate transistor region and the pull-down body region.
The removal of the third P-type work function layer 1043 in this step can be achieved by any etching method known to those skilled in the art, including but not limited to wet etching or dry etching, preferably dry etching, which can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
In this step, the third P-type work function layer 1043 in the pass gate transistor region and the pull-down transistor region is remained, and the third P-type work function layer 1043 may act as a barrier to aluminum in a subsequently formed N-type work function layer (e.g., TiAlC).
Next, as shown in fig. 1G, an N-type work function layer 106 is formed on the bottom and sidewalls of the first and second gate grooves.
The material of the N-type work function layer 106 may be selected from, but is not limited to, TaAlC, TaC, Ti, Al, TixAl1-x, or other suitable thin film layers. The material of the N-type work function layer 106 is preferably TiAlC. The N-type work function layer 106 may be formed using a suitable process such as CVD, ALD, or PVD. The thickness of the N-type work function layer 106 ranges from 10 angstroms to 80 angstroms.
An N-type work function layer 106 is formed on the bottom and sidewalls of the first and second gate grooves, that is, the N-type work function layer 106 is formed in each of the pull-up body transistor region, the pull-down body transistor region, and the transfer gate transistor region.
Finally, as shown in fig. 1H, the first gate recess and the second gate recess are filled with a metal gate electrode layer 107.
In one example, before forming the metal gate electrode layer 107, a step of forming a second blocking layer (not shown) on the N-type work function layer 106 is further included.
Wherein the material of the second barrier layer may comprise TiN or other suitable material.
The material of the metal gate electrode layer 107 may be selected as, but not limited to, Al, W, or other suitable thin film layers. The metal gate electrode layer 107 may be formed by a suitable process such as CVD, ALD, or PVD.
In one example, a metal W is formed as the metal gate electrode layer 107 using a chemical vapor deposition process. Wherein the CVD process uses WF6Decomposing WF as a reaction gas6Depositing to form the metal W.
Illustratively, the deposited metal gate electrode layer 107 fills all gate recesses and overflows over the surface of the interlayer dielectric layer, and a planarization process, such as chemical mechanical polishing or wet etching, is performed until the surface of the interlayer dielectric layer (not shown) is exposed, i.e., the top surface of the metal gate electrode layer 107 is flush with the tops of the first gate recess and the second gate recess. In the process, the plurality of films deposited on the surface of the interlayer dielectric layer in the previous step can be removed together.
Wherein, in one example, as shown in fig. 2, a portion of the metal gate electrode layer 107 located in the first gate recess spans the first fin structure 1021, the second fin structure 1022, and the fourth fin structure 1024.
Thus, the fabrication of the semiconductor device of the present invention, which may be an SRAM device including a pull-up transistor (PU) formed in a pull-up transistor region, a pull-down transistor (PD) formed in a pull-down transistor region, and a pass-gate transistor (PU) formed in a pass-gate transistor region, as shown in fig. 2, is completed.
In one example, a first metal gate stack structure of a pull-up transistor spans the first fin structure 1021, including an interfacial layer, a high-k dielectric layer 103, a first P-type work function layer 1041, a second P-type work function layer 1042, a first barrier layer 103, an N-type work function layer 106, a second barrier layer (not shown), and a metal gate electrode layer 107 stacked in this order from bottom to top; the second metal gate stack structure of the pull-down transistor spans the second fin structure 1022 and the fourth fin structure 1024 and is connected to the first metal gate stack structure of the pull-up transistor, and the second metal gate stack structure includes an interface layer, a high-k dielectric layer 103, a second P-type work function layer 1042, a first barrier layer 103, a third P-type work function layer 1043, an N-type work function layer 106, a second barrier layer (not shown) and a metal gate electrode layer 107, which are sequentially stacked from bottom to top, so that the metal gate stack structure of the pull-up transistor and the metal gate stack structure of the pull-down transistor are electrically connected; a third metal gate stack structure of the pass gate transistor crosses the third fin structures 1023, the third fin structures 1023 may be connected with the second fin structures 1022, and the third metal gate stack structure includes an interface layer (not shown), a high-k dielectric layer 103, a third P-type work function layer 1043, an N-type work function layer 106, a second barrier layer (not shown), and a metal gate electrode layer 107, which are sequentially stacked from bottom to top.
In summary, according to the manufacturing method of the present invention, firstly, the boundaries (boundaries) of the pull-up transistor and the pull-down transistor are simpler and weaker in mutual influence, and the mismatch performance of the device is improved; secondly, the metal gate lamination structure is simpler, and the combination with the number of the fins can easily enable the read-write margin to meet the requirements of the device; furthermore, the third P-type work function layer is formed below the N-type work function layer, so that aluminum diffusion is completely eliminated, and the mismatch performance of the device is improved.
Example two
The present invention also provides a semiconductor device, which may be an SRAM device, formed using the method of the previous implementation one.
Next, the semiconductor device of the present invention is described in detail with reference to fig. 1H and fig. 2.
First, the semiconductor device of the present invention includes: the semiconductor device includes a semiconductor substrate 100, wherein the semiconductor substrate 100 includes a pull-up body tube region, a pull-down body tube region and a transfer gate transistor region, and a first fin structure 1021, a second fin structure 1022 and a third fin structure 1023 are respectively formed in the pull-up body tube region, the pull-down body tube region and the transfer gate transistor region on the semiconductor substrate.
The semiconductor substrate 100 may include active regions for forming various constituent elements of the SRAM, for example, a PMOS device is formed in a pull-up transistor region as a pull-up transistor (PU) of the SRAM, an NMOS device is included in a pull-down transistor region as a pull-down transistor (PD) of the SRAM, and an NMOS device is included in a pass-gate transistor region as a pass-gate transistor (PG) of the SRAM.
Further, various well regions are formed in the semiconductor substrate 100, for example, an N-type well region (NW) is formed in a pull-up transistor region, and a P-type well region (PW) is formed in a pull-down transistor region and a transfer gate transistor region, wherein the implanted ion species and the implantation method can be methods commonly used in the art, and are not described herein again.
A first fin structure 1021, a second fin structure 1022, and a third fin structure 1023 are formed in the pull-up body tube region, the pull-down body tube region, and the transfer gate transistor region, respectively, on the semiconductor substrate.
The first fin structure 1021, the second fin structure 1022, and the third fin structure 1023 all extend a certain length in the same direction on the semiconductor substrate, and each fin structure may also be a plurality of strip structures formed on the semiconductor substrate 100.
Further, at least a fourth fin structure 1024 parallel to the second fin structure 1022 is formed in the pull-down transistor area, and the fourth fin structure 1024 and the second fin structure 1022 are both used for forming a pull-down transistor of the SRAM.
In one example, second fin structure 1022 and third fin structure 1023 are connected, which can be different portions of the same fin structure within a pull down transistor region and a pass gate transistor region, respectively.
The fin structures have the same width, or the fins are divided into a plurality of fin structure groups with different widths, and the lengths of the fin structures can be different.
Further, isolation structures 101 are formed on the semiconductor substrate 100 outside the first fin structures 1021, the second fin structures 1022, the third fin structures 1023, and the fourth fin structures 1024, and top surfaces of the isolation structures 101 are lower than top surfaces of the respective fin structures.
The material of the isolation structure 101 may be selected from an oxide, such as a High Aspect Ratio Process (HARP) oxide, specifically, silicon oxide deposited by a flowable chemical vapor deposition process, and the like.
The semiconductor device of the present invention further includes a first metal gate stack structure formed in the pull-up body tube region and crossing the first fin structure 1021, which includes a high-k dielectric layer 103, a first P-type work function layer 1041, a second P-type work function layer 1042, an N-type work function layer 106, and a metal gate electrode layer 107 stacked in sequence from bottom to top.
In one example, a first barrier layer 105 is also disposed between the second P-type work function layer 1042 and the N-type work function layer 106 in the pull-up body tube region.
Further, the semiconductor device of the present invention further includes a second metal gate stack structure formed in the pull-down body tube region, which crosses over the second fin structure 1022 and is connected to the first metal gate stack structure, and which includes the high-k dielectric layer 103, the second P-type work function layer 1042, the third P-type work function layer 1043, the N-type work function layer 106, and the metal gate electrode layer 107 stacked in sequence from bottom to top.
Illustratively, when the fourth fin structure 1024 is disposed within a pulldown body region on the semiconductor substrate, the second metal gate stack structure also spans the fourth fin structure 1024.
Further, the second P-type work function layer 1042 and the third P-type work function layer 1043 in the pull-down body tube region are also provided with the first barrier layer 105.
The first barrier layer 105 in the pull-up and pull-down tube regions continuously spans the first fin structure 1021 and the second fin structure 1022, and when a fourth fin structure 1024 is disposed outside the second fin structure, the fourth fin structure 1024 also spans the fourth fin structure 1024.
Further, the semiconductor device of the present invention further includes a third metal gate stack structure formed in the pass gate transistor region, which crosses over the third fin structure 1023, and includes the high-k dielectric layer 103, the third P-type work function layer 1043, the N-type work function layer 106, and the metal gate electrode layer 107 stacked in sequence from bottom to top.
Illustratively, an interface layer (not shown) is also disposed below the high-k dielectric layer 103, the interface layer being formed on a portion of the surface of the semiconductor substrate 100 and the surfaces of the first fin structure 1021, the second fin structure 1022, the third fin structure 1023, and the fourth fin structure 1024.
Further, in each of the first metal gate stack structure, the second metal gate stack structure and the third metal gate stack structure, a second blocking layer (not shown) is disposed between the metal gate electrode layer 107 and the N-type work function layer 106. Wherein the material of the second barrier layer may comprise TiN or other suitable material.
The Interface (IL) layer is formed of a material including silicon oxide (SiOx) and is formed to improve the interface characteristics between the high-k dielectric layer and the semiconductor substrate. The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a suitable process such as thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The interfacial layer has a thickness in the range of 5 angstroms to 10 angstroms.
High-k dielectric layer 103 has a k value (dielectric constant) of usually 3.9 or more, and is composed of a material such as hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-k dielectric layer 103 may be formed using a suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The thickness of the high-k dielectric layer 103 ranges from 10 angstroms to 30 angstroms.
The materials of the first P-type work function layer (PWF)1041, the second P-type work function layer (PWF)1042, and the third P-type work function layer (PWF)1043 may be selected as, but not limited to, TixN1-x, TaC, MoN, TaN, or combinations thereof or other suitable thin film layers. Preferably, TiN may be used as the material of each P-type work function layer. The P-type work function layer may be formed using a suitable process such as CVD, ALD, or PVD. Each P-type work function layer 1041 has a thickness ranging from 10 angstroms to 580 angstroms. Different materials and thicknesses of the P-type work function layers can be used.
The material of the first barrier layer 105 includes one or more of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, and tungsten nitride, and in this embodiment, the first barrier layer 105 is preferably tantalum nitride (TaN).
The first barrier layer 105 may be formed by a process such as physical vapor deposition, atomic layer deposition, spin-on deposition (spin-on) deposition, or other suitable methods. In addition, the first barrier layer 105 may also include a plurality of layers.
The material of the N-type work function layer 106 may be selected from, but is not limited to, TaAlC, TaC, Ti, Al, TixAl1-x, or other suitable thin film layers. The material of the N-type work function layer 106 is preferably TiAlC. The N-type work function layer 106 may be formed using a suitable process such as CVD, ALD, or PVD. The thickness of the N-type work function layer 106 ranges from 10 angstroms to 80 angstroms.
The material of the metal gate electrode layer 107 may be selected as, but not limited to, Al, W, or other suitable thin film layers. The metal gate electrode layer 107 may be formed by a suitable process such as CVD, ALD, or PVD.
In one example, a metal W is formed as the metal gate electrode layer 107 using a chemical vapor deposition process. Wherein the CVD process uses WF6Decomposing WF as a reaction gas6Depositing to form the metal W.
In one example, offset spacers (spacers) are formed on sidewalls of the first metal gate stack structure, the second metal gate stack structure, and the third metal gate stack structure.
Specifically, the offset spacer may be formed of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. As an implementation manner of this embodiment, the offset spacer is composed of silicon oxide and silicon nitride, and the specific process includes: and forming a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer on the semiconductor substrate, and then forming the offset side wall by adopting an etching method. Or forming offset sidewall material layers on the top surfaces and the sidewalls of the first dummy gate structure and the second dummy gate structure, and removing the offset sidewall material layers on the top surfaces by a planarization method, such as chemical mechanical polishing, in a subsequent step to form the offset sidewalls only on the sidewalls.
And forming a gap wall on the offset side walls of the first metal gate laminated structure, the second metal gate laminated structure and the third metal gate laminated structure.
Specifically, spacers (spacers) are formed on the offset sidewalls, and the spacers may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are formed on a semiconductor substrate, and then a spacer is formed by an etching method.
Further, a source and a drain of the pull-up transistor are also formed in the first fin structure 1021 at two sides of the first metal gate stack structure, a respective source and drain are respectively formed in the second fin structure 1022 and the fourth fin structure 1024 at two sides of the second metal gate stack structure, and a source and drain of the pass-gate transistor are formed in the third fin structure 1023 at two sides of the third metal gate stack structure, wherein when the second fin structure 1022 and the third fin structure 1023 are connected, the drain of the pass-gate transistor and the drain of the pull-down transistor formed on the second fin structure 1022 are electrically connected, or share the same drain.
An interlayer dielectric layer is formed on the surface of the semiconductor substrate, the first metal gate laminated structure, the second metal gate laminated structure and the third metal gate laminated structure are positioned in the interlayer dielectric layer, and the top surface of the interlayer dielectric layer is flush with the top surface of the metal gate laminated structure.
The interlayer dielectric layer may be made of dielectric materials commonly used in the art, such as various oxides, and may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.
The complete device may further include other elements, such as a metal interconnection structure for leading out a source, a drain, a gate, and the like, which are not described herein again.
The semiconductor device of the present invention may be an SRAM device, and as shown in fig. 2, the SRAM device includes a pull-up transistor (PU) formed in a pull-up transistor region, a pull-down transistor (PD) formed in a pull-down transistor region, and a pass-gate transistor (PG) formed in a pass-gate transistor region, wherein a first metal gate stack structure of the pull-up transistor and a second metal gate stack structure of the pull-down transistor are electrically connected, and a drain of at least one of the pull-down transistor and a drain of the pass-gate transistor are electrically connected or share a drain.
In summary, the semiconductor device of the present invention is prepared by the above manufacturing method, and therefore has corresponding advantages, first, the boundaries (boundaries) of the pull-up transistor and the pull-down transistor are simpler and less influenced, and the mismatch performance of the device is improved; secondly, the metal gate lamination structure is simpler, and the combination with the number of the fins can easily enable the read-write margin to meet the requirements of the device; furthermore, a third P-type work function layer is formed below the N-type work function layer, so that aluminum diffusion is completely eliminated, and the mismatch performance of the device is improved, so that the semiconductor device has higher performance.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device of the second embodiment, and the semiconductor device is prepared according to the method of the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the circuit.
Wherein figure 4 shows an example of a mobile telephone handset. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
Wherein the mobile phone handset comprises the semiconductor device of embodiment two, the semiconductor device comprising:
the semiconductor substrate comprises a pull-up body tube area, a pull-down body tube area and a transmission gate transistor area, wherein a first fin structure, a second fin structure and a third fin structure are respectively formed in the pull-up body tube area, the pull-down body tube area and the transmission gate transistor area on the semiconductor substrate;
the first metal gate laminated structure is formed in the pull-up body tube area and stretches across the first fin structure and comprises a high-k dielectric layer, a first P-type work function layer, a second P-type work function layer, an N-type work function layer and a metal gate electrode layer which are sequentially laminated from bottom to top;
a second metal gate stack structure formed in the pull-down body tube region, crossing over the second fin structure and connected to the first metal gate stack structure, and including the high-k dielectric layer, the second P-type work function layer, the third P-type work function layer, the N-type work function layer, and the metal gate electrode layer stacked in sequence from bottom to top;
and a third metal gate stack structure formed in the transmission gate transistor region and crossing the third fin structure, wherein the third metal gate stack structure includes the high-k dielectric layer, the third P-type work function layer, the N-type work function layer, and the metal gate electrode layer stacked in sequence from bottom to top.
The semiconductor device has the following advantages: firstly, the boundaries (boundaries) of the pull-up transistor and the pull-down transistor are simpler and weaker in mutual influence, and the mismatch performance of the devices is improved; secondly, the metal gate lamination structure is simpler, and the combination with the number of the fins can easily enable the read-write margin to meet the requirements of the device; furthermore, a third P-type work function layer is formed below the N-type work function layer, so that aluminum diffusion is completely eliminated, and the mismatch performance of the device is improved, so that the semiconductor device has higher performance.
Since the electronic apparatus of the present invention includes the aforementioned semiconductor device, the semiconductor device has advantages as well as the electronic apparatus.
Claims (20)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a pull-up body tube area, a pull-down body tube area and a transmission gate transistor area, and a first fin structure, a second fin structure and a third fin structure are respectively formed in the pull-up body tube area, the pull-down body tube area and the transmission gate transistor area on the semiconductor substrate;
forming a first dummy gate structure spanning the first fin structure and the second fin structure, and a second dummy gate structure spanning the third fin structure;
removing the first dummy gate structure to form a first gate groove, and removing the second dummy gate structure to form a second gate groove;
forming a first P-type work function layer on the bottom and the side wall of the first grid electrode groove in the pull-up body tube area;
forming a second P-type work function layer on the bottom and the side wall of the first grid electrode groove;
forming a third P-type work function layer on the bottom and the side wall of the first gate groove and the second gate groove in the pull-down body tube region;
and forming an N-type work function layer on the bottom and the side wall of the first grid electrode groove and the second grid electrode groove.
2. The method of manufacturing of claim 1, wherein the third fin structure and the second fin structure are connected.
3. The method of claim 1, further comprising forming at least a fourth fin structure on the pull down body tube region.
4. The method of manufacturing according to claim 3, wherein the first gate recess exposes a portion of the fourth fin structure in an extending direction of the fourth fin structure.
5. The manufacturing method according to claim 1, further comprising, before forming the first P-type work function layer, the steps of: and forming a high-k dielectric layer on the bottom and the side wall of the first gate groove and the second gate groove, and annealing the high-k dielectric layer.
6. The method of manufacturing of claim 1, further comprising a step of forming a first barrier layer on the second P-type work function layer in the pull-up and pull-down body tube regions after forming the second P-type work function layer and before forming the third P-type work function layer.
7. The method of manufacturing according to claim 1, wherein the materials of the first and second P-type work function layers and the third P-type work function each comprise TiN.
8. The manufacturing method according to claim 1, wherein a material of the N-type work function layer comprises one or a combination of TiAl or TiAlC.
9. The manufacturing method according to claim 1, further comprising, after forming the N-type work function layer, the steps of:
forming a second barrier layer on the N-type work function layer;
and filling metal gate electrode layers in the first gate groove and the second gate groove.
10. The manufacturing method according to claim 9, wherein the step of forming the metal gate electrode layer includes:
depositing and forming a metal material on the semiconductor substrate, and carrying out chemical mechanical polishing on the metal material to form the metal gate electrode layer, wherein the top surface of the metal gate electrode layer is flush with the tops of the first gate groove and the second gate groove.
11. The method of manufacturing according to claim 1, wherein before the first gate recess and the second gate recess are formed, isolation structures are further formed on the semiconductor substrate outside the first fin structure, the second fin structure, and the third fin structure, and top surfaces of the isolation structures are lower than top surfaces of the first fin structure, the second fin structure, and the third fin structure.
12. The method of manufacturing of claim 5, further comprising a step of forming an interfacial layer at a bottom of the first and second gate recesses prior to forming the high-k dielectric layer.
13. A semiconductor device, comprising:
the semiconductor substrate comprises a pull-up body tube area, a pull-down body tube area and a transmission gate transistor area, wherein a first fin structure, a second fin structure and a third fin structure are respectively formed in the pull-up body tube area, the pull-down body tube area and the transmission gate transistor area on the semiconductor substrate;
the first metal grid laminated structure is formed in the crystal pulling body tube area and stretches across the first fin structure and comprises a first P-type work function layer, a second P-type work function layer and an N-type work function layer which are sequentially laminated from bottom to top;
the second metal gate laminated structure is formed in the pull-down body tube area, spans the second fin structure, is connected with the first metal gate laminated structure, and comprises a second P-type work function layer, a third P-type work function layer and an N-type work function layer which are sequentially laminated from bottom to top;
and the third metal gate laminated structure is formed in the transistor area of the transmission gate, spans the third fin structure and comprises a third P-type work function layer and an N-type work function layer which are sequentially laminated from bottom to top.
14. The semiconductor device of claim 13, wherein the third fin structure and the second fin structure are connected.
15. The semiconductor device of claim 13, wherein at least a fourth fin structure is further formed over the pull down body tube region.
16. The semiconductor device of claim 15, wherein the second metal gate stack structure spans across the fourth fin structures.
17. The semiconductor device of claim 13, wherein a first barrier layer is further disposed between the second P-type work function layer and the N-type work function layer in the pull-up body tube region and the second P-type work function layer and the third P-type work function layer in the pull-down body tube region.
18. The semiconductor device according to claim 13, wherein a second barrier layer is formed over the N-type work function layer, and wherein a metal gate electrode layer is formed over the second barrier layer.
19. The semiconductor device of claim 13, wherein isolation structures are further formed on the semiconductor substrate outside the first fin structures, the second fin structures, and the third fin structures, wherein top surfaces of the isolation structures are lower than top surfaces of the first fin structures, the second fin structures, and the third fin structures.
20. An electronic device comprising the semiconductor device according to any one of claims 13 to 19.
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| CN104170091A (en) * | 2011-12-28 | 2014-11-26 | 英特尔公司 | Techniques and configurations for stacking transistors of integrated circuit devices |
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| CN104170091A (en) * | 2011-12-28 | 2014-11-26 | 英特尔公司 | Techniques and configurations for stacking transistors of integrated circuit devices |
| US9159626B2 (en) * | 2012-03-13 | 2015-10-13 | United Microelectronics Corp. | FinFET and fabricating method thereof |
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