CN103904028A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN103904028A
CN103904028A CN201310565657.8A CN201310565657A CN103904028A CN 103904028 A CN103904028 A CN 103904028A CN 201310565657 A CN201310565657 A CN 201310565657A CN 103904028 A CN103904028 A CN 103904028A
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pmos
nmos
work function
grid
regulating course
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李迪
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TANG ZONG
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TANG ZONG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps that a substrate is provided; pseudo grid stack of NMOS and PMOS, side walls of the NMOS and the PMOS, source/drain regions of the NMOS and the PMOS and interlayer dielectric layers are formed on the substrate respectively; the pseudo grid stack is removed to form a pseudo grid space, and a grid dielectric layer formed on the substrate is exposed or the grid dielectric layer is formed at the position, located in the pseudo grid space, of the substrate; PMOS work function adjusting layers are formed on an NMOS structure and a PMOS structure; barrier layers are formed on the NMOS structure and the PMOS structure; the barrier layer on the NMOS structure is removed; NMOS work function adjusting layers are formed on the NMOS structure and the PMOS structure; the NMOS work function adjusting layer on the PMOS structure is removed; contact metal layers are formed on the NMOS structure and the PMOS structure. Correspondingly, the invention further provides the semiconductor structure. In the semiconductor structure, only the PMOS work function adjusting layer exists in a PMOS grid stack layer, therefore, metal filling is easy to achieve, and meanwhile the PMOS grid resistance is also reduced.

Description

A kind of semiconductor structure and manufacture method thereof
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of semiconductor gate electrode structure and manufacture method thereof.
Background technology
In semicon industry prior art, grid technology generally adopts replacement gate process.Grid structure is made up of multilayer material conventionally, as gate dielectric layer, work function regulating course and gate metal layer.Due to size reduction, depth-width ratio increases, and the filling of grid is more and more difficult, thus cause grid be filled with hole (void), fill insufficiently, cause resistance to increase, reliability variation.
Due to type of device difference, the work function regulating course of PMOS and NMOS need to use different materials, and this has brought very large difficulty to IC technique.In prior art, the general work function regulating course material of TiN as PMOS that adopt, uses the work function regulating course material of TiN/TiAl as NMOS.On the make, in order to reduce process complexity, often the method for PMOS and NMOS deposit is simultaneously completed the making of work function regulating course, adopt separator that the TiAl layer on PMOS is separated with the work function regulating course of PMOS.
This manufacture method can increase the thickness of gate stack, and when deposit, the material layer thickness of gate lateral wall also increases thereupon, and this has further reduced effective packing space of gate metal.Along with the appearance of three-dimensional Finfet structure, and long constantly the reducing of grid, grid packing space also reduces thereupon, adopt after three-dimensional structure, need the grid opening degree of depth of filling to deepen, and top and sidewall all to be filled, make the filling of follow-up contacting metal become difficulty, also can make gate contact resistance increase simultaneously, increase device power consumption, affect device performance.
Summary of the invention
The invention provides a kind of semiconductor structure that can address the above problem and manufacture method thereof.
According to an aspect of the present invention, provide a kind of manufacture method of semiconductor structure, the method comprises the following steps:
A., substrate is provided;
B. on substrate, form respectively the pseudo-grid of NMOS and PMOS stacking and side wall, source/drain region and interlayer dielectric layer;
C. remove the pseudo-grid of the stacking formation of described pseudo-grid room, on the gate dielectric layer forming on exposure substrate or the substrate in pseudo-grid room, form gate dielectric layer;
D. in described NMOS and PMOS structure, form PMOS work function regulating course;
E. in described NMOS and PMOS structure, form barrier layer;
F. remove the structural barrier layer of NMOS;
G. in described NMOS and PMOS structure, form NMOS work function regulating course;
H. remove NMOS work function regulating course and barrier layer on PMOS;
I. in described NMOS and PMOS structure, form TiN lining and contact metal layer.
According to another aspect of the present invention, also provide a kind of semiconductor structure, having comprised:
Substrate;
Nmos device and PMOS device, it is formed on described substrate;
Described nmos device and PMOS device comprise respectively:
Grid are stacking, and it is positioned on described substrate;
In nmos device, described grid are stacking to be comprised from bottom to up successively: gate dielectric layer, PMOS work function regulating course, NMOS work function regulating course and contact metal layer;
In PMOS device, described grid are stacking to be comprised from bottom to up successively: gate dielectric layer, PMOS work function regulating course and contact metal layer;
Side wall, is positioned on the stacking sidewall of described grid;
Interlayer dielectric layer, is positioned on described substrate side wall both sides;
Source/drain region, is arranged in the substrate of the stacking both sides of described grid.
Compared with prior art, adopt technical scheme tool provided by the invention to have the following advantages: by having increased the etch step to the NMOS work function regulating course in PMOS, make in PMOS gate stack, to only have PMOS work function regulating course, effectively discharge space, make metal filled becoming easily, also reduced the resistance of PMOS simultaneously.
Brief description of the drawings
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become.
Fig. 1 is the flow chart of semiconductor structure manufacture method according to an embodiment of the invention;
Fig. 2 to Fig. 8 is according to the generalized section in each stage of the semiconductor structure of flow manufacturing shown in Fig. 1;
Fig. 9 and Figure 12 are respectively the FINFET 3 dimensional drawing of NMOS and PMOS in embodiments of the invention;
Figure 10, Figure 11, Figure 13 and Figure 14 are respectively the profile of Fig. 9 and Figure 12 different directions.
Embodiment
Describe embodiments of the invention below in detail.
The example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts to specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skill in the art can recognize the property of can be applicable to of other techniques and/or the use of other materials.
A kind of manufacture method of semiconductor structure is provided according to an aspect of the present invention.The method that by one embodiment of the present of invention, Fig. 1 is formed to semiconductor structure in connection with Fig. 2 to Fig. 8 below, is specifically described.As shown in Figure 1, manufacture method provided by the present invention comprises the following steps:
In step S101, provide substrate 100.
Particularly, first provide substrate 100.In the present embodiment, described substrate 100 be silicon substrate in other embodiments, described substrate 100 can comprise other basic semiconductor, for example germanium.Or substrate 100 can comprise compound semiconductor, for example GaAs, indium arsenide.
Then, in described substrate 100, form isolated area, for example shallow trench isolation is from (STI) structure 110, so that the adjacent FET device of electricity isolation.Device can be planar device, can be also the three-dimension device as FINFET.This method is more suitable for the three-dimension device as FINFET, is due in FINFET three-dimension device manufacture process, while adopting replacement gate process to carry out grid filling.Due to long constantly the reducing of grid, grid packing space also reduces thereupon, need the grid opening degree of depth of filling to deepen, and top and sidewall all will be filled, make the filling of follow-up contacting metal gate electrode become difficulty, also can make gate contact resistance increase simultaneously, increase device power consumption, affect device performance.
In step S102, on substrate, form respectively the pseudo-grid of NMOS and PMOS stacking and side wall, source/drain region and interlayer dielectric layer.Stacking high-K gate dielectric and the dummy grid of comprising of described pseudo-grid, dummy grid is made up of polysilicon conventionally.
Particularly, as shown in Figure 2, first, on substrate 100, form pseudo-grid.Wherein pseudo-grid comprise dummy grid 102, also can comprise high-K gate dielectric.Described dummy grid 102 is by deposit spathic silicon, polycrystal SiGe, amorphous silicon, and/or doping or unadulterated silica and silicon nitride, silicon oxynitride, carborundum, and even metal forms.Its material will have Etch selectivity with the material of interlayer dielectric layer.Then stacking as barrier layer using described pseudo-grid, by inject P type or N-type alloy or impurity in substrate 100, in formation source/drain region, the stacking both sides of described pseudo-grid.
Then form side wall in stacking 102 both sides of described pseudo-grid, the material of described side wall is SiO2, Si3N4, SiON.Finally on substrate 100, form interlayer dielectric layer 105, the material of described interlayer dielectric layer is SiO2, SiOF, SiCOH, SiO, SiCO, SiCON, SiON, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG.Form after interlayer dielectric layer 105 by deposit, can carry out a step CMP technique, make the upper surface flush of the stacking upper surface of pseudo-grid and interlayer dielectric layer, to facilitate ensuing technique.
In step S103, remove the pseudo-grid of the stacking formation of described pseudo-grid room, on the substrate in pseudo-grid room, form or expose high-K gate dielectric layer, or can comprise certain TiN above high-K gate dielectric layer, to protect high-K gate dielectric.
Particularly, first etch away stacking pseudo-grid by selective etch, until expose high-K gate dielectric layer (or can comprise certain TiN above high-K gate dielectric layer, to protect high-K gate dielectric), or expose substrate 100.Then at bottom deposit one deck gate dielectric layer in pseudo-grid room, can preferably use ALD, PVD etc., in the present embodiment, described gate dielectric layer can and be combined to form for silica or silicon nitride, in other embodiments, can be also high K dielectric, for example, and HfO 2, a kind of or its combination in HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, HfLaO, or comprise the combining structure of high K dielectric and silica or silicon nitride, its thickness can be 1nm-5nm.
In other embodiments; also can form pseudo-grid at step S102 and first form high-K gate dielectric layer before stacking; then in ensuing etch step; being etched to gate dielectric layer and protective layer thereof (or can comprise certain TiN above high-K gate dielectric layer, to protect high-K gate dielectric) stops all can.The effect that first formed grid high K dielectric layer before the pseudo-grid of formation are stacking can be slightly good, and reason is in this case, on the sidewall in pseudo-grid room, does not have high K dielectric layer.The filling meeting of gate electrode is more abundant.
In step S104, in described NMOS and PMOS structure, form PMOS work function regulating course.
Particularly, as shown in Figure 3, on the whole semiconductor structure surface of (comprising NMOS and PMOS device), now comprise that the surface of interlayer dielectric layer 105, side wall and gate dielectric layer forms one deck PMOS work function regulating course 201.Form technique and can select plating or the depositing operations such as PVD, CVD, ALD, PLD, MOCVD, PEALD, sputter, molecular beam deposition (MBE).The material of described PMOS work function regulating course is TiN in the present embodiment.Also can select in other embodiments other suitable material.
In step S105, in described NMOS and PMOS structure, form barrier layer.
Particularly, as shown in Figure 4, on the whole semiconductor structure surface of (comprising NMOS and PMOS device), now surface is the PMOS work function regulating course 201 of firm deposit, forms one deck barrier layer 202, and method can be ALD.In the present embodiment, described PMOS work function regulating course 201 is TiN or the material based on TiN; The material on described barrier layer 202 can be double-decker, and ground floor is thinner, is the lining based on Ta, and the second layer is thicker, is TiN, material based on TiN.In the design on barrier layer, consider the thickness at quarter excessively in successive process, also can select in other embodiments other suitable material.Mainly because the selectivity between TiN and Ta is good.Can adopt wet etching.Can etching must be more even, guarantee being also etched away on sidewall, thereby be that follow-up filling increases space.This point is particularly important for the processing procedure of FINFET, because the grid of FINFET form on the sidewall of FIN.Another one beneficial effect is can avoid dry etching time, to produce heavy plasma damage.This is particularly important in the place near gate medium.
In step S106, remove the barrier layer on NMOS.
Particularly, as shown in Figure 5, first the surface-coated one deck photoresist 300 in PMOS structure by patterned mode, then carries out etching using this photoresist as barrier layer to the barrier layer 202 in NMOS structure.Can be that dry wet method combines, final step be preferably wet etching.Beneficial effect be can etching must be more even, guarantee being also etched away on sidewall, thereby be that follow-up filling increases space.This point is particularly important for the processing procedure of FINFET.Lithographic method used is wet etching in the present embodiment, is etched to while exposing PMOS work function regulating course 201 and stops.
In step S107, in described NMOS and PMOS structure, form NMOS work function regulating course (being for example TiAl layer).
Concrete, first the photoresist of PMOS body structure surface is removed, then on the whole semiconductor structure surface of (comprising NMOS and PMOS device), now NMOS surface is PMOS work function regulating course 201, PMOS surface is barrier layer 202, deposit NMOS work function regulating course, as shown in Figure 6.Deposit NMOS work function regulating course 203, the material of NMOS work function regulating course 203 is TiAl.In follow-up technique, PMOS work function regulating course TiN201 and NMOS work function regulating course TiAl203 can make the diffusion of Al atom by heating, form the work function regulating course that is applicable to nmos device, i.e. TiAlN layer.Also can select in other embodiments other suitable work function regulating course.
In step S108, remove the NMOS work function regulating course on PMOS.
Concrete, as shown in Figure 7, first, at surface-coated one deck photoresist 305 of NMOS structure, then using this photoresist as barrier layer, the NMOS work function regulating course TiAl layer to PMOS surface and barrier layer (for example, being TiN layer) carries out etching.
In the present embodiment, concrete etching can be considered the lithographic method that the dry wet method of the following steps combines.Can first by dry etching, the NMOS work function regulating course on PMOS surface (for example, being TiAl layer) 203 be etched away.Can there is certain crossing to carve, ensure that TiAl carves completely, is parked on the TiN202 of barrier layer.While carving barrier layer TiN202, can use wet method, be parked on the lining containing Ta, be mainly because the selectivity between TiN and Ta is good.Stop when exposing PMOS work function regulating course 201.In other embodiments, those skilled in the art can be according to the actual needs and the stop position of the free selective etching of technological level, such as or be etched to barrier layer 202 and stop, can or stop while etching into certain one deck middle.
In step S109, in described NMOS and PMOS structure, form gate electrode metal layer.(because work function layer resistance is large) need to use low resistive metal, can use tungsten (W), can preferably deposit with ALD.
Concrete, first etching is removed the photoresist of NMOS body structure surface, as shown in Figure 8, then in the pseudo-grid space on the work function layer of nmos device and PMOS device, fill grid material and form gate stack, described gate stack can comprise TiN lining and W contact metal layer (wherein the effect of TiN lining is barrier grid electrode, such as the diffusion of metal W atom).
Compared with prior art, the present invention has the following advantages: by having increased the etch step to the NMOS work function regulating course in PMOS, make in PMOS gate stack, to only have PMOS work function regulating course, effectively discharge space, allowed the grid amount of metal of PMOS filling and the grid amount of metal that NMOS fills approach.Even more than NMOS.Because NMOS has TiAl and TiN.PMOS only has TiN.So, make that the grid of PMOS are metal filled to become easily, also reduce the resistance of PMOS simultaneously.
In another embodiment, the present invention also can be used for FINFET structure and manufacturing process thereof, by having increased the etch step to the NMOS work function regulating course in PMOS, make in P type FINFET gate stack, to only have P type work function regulating course, as shown in Fig. 9 and Figure 12, the stereogram of the FINFET three-dimensional structure that wherein Fig. 9 is NMOS; Figure 12 is the stereogram of the FINFET three-dimensional structure of PMOS.Can find out, compared with prior art, the number of plies of N-type and P type FINFET gate stack is all effectively reduced.Figure 10 is the profile along A-A direction in Fig. 9, and Figure 11 is the profile along B-B direction in Fig. 9, can find out, only has two-layer gate stack between gate metal and fin, i.e. P type work function regulating course 201 and N-type work function regulating course 203; Same, Figure 13 is the profile along A-A direction in Figure 12, Figure 14 is the profile along B-B direction in Figure 12, can find out, only has one deck gate stack between gate metal and fin, i.e. P type work function regulating course 201.By the method for the present embodiment, can effectively discharge space, make metal filled becoming easily, also reduce the resistance of PMOS simultaneously.According to another aspect of the present invention, also provide a kind of semiconductor structure, please refer to Fig. 8.As shown in the figure, this semiconductor structure comprises:
Substrate 100;
Grid are stacking, are positioned on described substrate 100;
In NMOS, described grid are stacking to be comprised from bottom to up successively: gate dielectric layer, NMOS work function regulating course and contact metal layer 205;
In PMOS, described grid are stacking to be comprised from bottom to up successively: gate dielectric layer, PMOS work function regulating course 201 and contact metal layer 205;
Side wall 104, is positioned on the stacking sidewall of described grid;
Interlayer dielectric layer 105, is positioned on described substrate 100 side wall 104 both sides;
Source/drain region, is arranged in the substrate 100 of the stacking both sides of described grid.
Particularly, in the present embodiment, described substrate 100 is silicon substrate (for example silicon wafer).In other embodiments, described substrate 100 can comprise other basic semiconductors (as III-V family material), for example germanium.Or substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide.Typically, substrate 100 can have but be not limited to the thickness of about hundreds of micron, for example can be in the thickness range of 400 μ m-800 μ m.In described substrate 100, have isolated area, for example shallow trench isolation is from (STI) structure 110, so that the continuous FET device of electricity isolation.
Described grid are stacking to be positioned on described substrate 100.As shown in the figure, the contact metal layer 205 that is wherein positioned at the stacking undermost gate dielectric layer of grid and the superiors is identical for nmos device structure and PMOS device architecture.The material of described gate dielectric layer is high K dielectric, for example HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, HfLaO, in a kind of or its combination, or comprise the combining structure of high K dielectric and silica or silicon nitride, its thickness range is 1nm-5nm.Described contact metal layer 205 is metal or metal alloy, comprises Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La and combination thereof.
Work function regulating course is for being different for nmos device structure and PMOS device architecture.Concrete, the work function regulating course of nmos device comprises the first work function regulating course TiN and the second work function regulating course TiAl in the present embodiment, and in follow-up heating process, because this two-layer work function regulating course of diffusion of Al atom can form TiAlN layer, i.e. NMOS work function regulating course.And the work function regulating course of PMOS only includes one deck TiN.In other embodiments, the work function regulating course of nmos device and PMOS device also can be selected other suitable material.
According to the difference of etching depth, above PMOS work function regulating course, can also select to leave all or part of barrier layer 202, or etch away completely.
On the stacking sidewall of described grid, have side wall, the material of described side wall 220 comprises silicon nitride, silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials form.
Described side wall both sides be interlayer dielectric layer 105, the material of described interlayer dielectric layer is SiO2, SiOF, SiCOH, SiO, SiCO, SiCON, SiON, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG.The upper surface flush that the upper surface of interlayer dielectric layer 105 and grid are stacking.
Described source/drain region is arranged in the substrate 100 of the stacking both sides of described grid.According to the type of semiconductor structure, (for example,, for PMOS device, impurity is boron in described source/leakage expansion area, to comprise P type or N-type alloy or impurity; For nmos device, impurity is arsenic).
Semiconductor structure provided by the present invention, has removed the work function layer of NMOS in PMOS, has realized PMOS and NMOS and can fill similar same grid metal.Even PMOS can also fill manyly.In the volume that has increased contact metal layer, reduce the resistance of PMOS.
Although describe in detail about example embodiment and advantage thereof, be to be understood that the protection range in the case of not departing from spirit of the present invention and claims restriction, can carry out various variations, substitutions and modifications to these embodiment.For other examples, those of ordinary skill in the art should easily understand in keeping in protection range of the present invention, and the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for had or be about at present technique, mechanism, manufacture, material composition, means, method or the step developed later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, can apply them according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.

Claims (12)

1. a manufacture method for semiconductor structure, the method comprises the following steps:
A., substrate (100) is provided;
B. on substrate, form respectively pseudo-grid stacking (102) and side wall (104), source/drain region and the interlayer dielectric layer (105) of NMOS and PMOS;
C. remove the pseudo-grid of the stacking formation of described pseudo-grid room, on the gate dielectric layer forming on exposure substrate or the substrate in pseudo-grid room, form gate dielectric layer;
D. in described NMOS and PMOS structure, form PMOS work function regulating course (201);
E. in described NMOS and PMOS structure, form barrier layer (202);
F. remove the structural barrier layer of NMOS (202);
G. in described NMOS and PMOS structure, form NMOS work function regulating course (203);
H. remove the NMOS work function regulating course (203) on PMOS;
I. in described NMOS and PMOS structure, form contact metal layer (205).
2. manufacture method according to claim 1, is characterized in that, the material of described PMOS work function regulating course (201) is TiN or the material based on TiN;
The material on described barrier layer (202) is double-decker, and ground floor is thinner, is the lining based on Ta, and the second layer is thicker, is TiN or the material based on TiN.
3. manufacture method according to claim 1, is characterized in that, the material of described NMOS work function regulating course (203) is TiAl or the material that comprises Al.
4. manufacture method according to claim 1, is characterized in that, after the NMOS work function regulating course (203) of removing on described PMOS, continues to remove the barrier layer (202) of lower floor.
5. according to the manufacture method described in any one in claim 1 to 4, it is characterized in that, described semiconductor structure is MOSFET.
6. according to the manufacture method described in any one in claim 1 to 4, it is characterized in that, described semiconductor structure is FINFET.
7. in the manufacture method described in claim 1, wherein, before forming contact metal layer, first form lining.
8. a semiconductor structure, comprising:
Substrate (100);
Nmos device and PMOS device, it is formed on described substrate (100);
Described nmos device and PMOS device comprise respectively:
Grid are stacking, and it is positioned on described substrate (100);
In nmos device, described grid are stacking to be comprised from bottom to up successively: gate dielectric layer, PMOS work function regulating course (201), NMOS work function regulating course (203) and contact metal layer (205), and wherein PMOS work function regulating course contains from NMOS work function regulating course and spreads the Al atom of coming;
In PMOS device, described grid are stacking to be comprised from bottom to up successively: gate dielectric layer, PMOS work function regulating course (201) and contact metal layer (205);
Side wall (104), is positioned on the stacking sidewall of described grid;
Interlayer dielectric layer (105), is positioned on described substrate (100), side wall (104) both sides;
Source/drain region, is arranged in the substrate (100) of the stacking both sides of described grid.
9. semiconductor structure according to claim 8 during the grid of wherein said PMOS are stacking, has barrier layer (202) on PMOS work function regulating course (201).
10. semiconductor structure according to claim 8, is characterized in that, the material of described PMOS work function regulating course (201) is TiN;
The material on described barrier layer (202) is double-decker, comprising: the lining based on Ta and TiN layer.
11. semiconductor structures according to claim 8, is characterized in that, the material of described NMOS work function regulating course (203) is TiAl.
12. semiconductor structures according to claim 8 have lining between NMOS work function regulating course (203) or PMOS work function regulating course (201) and contact metal layer.
CN201310565657.8A 2013-11-14 2013-11-14 Semiconductor structure and manufacturing method thereof Pending CN103904028A (en)

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